1 #ifndef MIPS_CPU_H 2 #define MIPS_CPU_H 3 4 #include "cpu-qom.h" 5 #include "exec/cpu-common.h" 6 #include "exec/cpu-defs.h" 7 #include "exec/cpu-interrupt.h" 8 #ifndef CONFIG_USER_ONLY 9 #include "system/memory.h" 10 #endif 11 #include "fpu/softfloat-types.h" 12 #include "hw/clock.h" 13 #include "mips-defs.h" 14 15 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 16 17 /* MSA Context */ 18 #define MSA_WRLEN (128) 19 20 typedef union wr_t wr_t; 21 union wr_t { 22 int8_t b[MSA_WRLEN / 8]; 23 int16_t h[MSA_WRLEN / 16]; 24 int32_t w[MSA_WRLEN / 32]; 25 int64_t d[MSA_WRLEN / 64]; 26 }; 27 28 typedef union fpr_t fpr_t; 29 union fpr_t { 30 float64 fd; /* ieee double precision */ 31 float32 fs[2];/* ieee single precision */ 32 uint64_t d; /* binary double fixed-point */ 33 uint32_t w[2]; /* binary single fixed-point */ 34 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 35 wr_t wr; /* vector data */ 36 }; 37 /* 38 *define FP_ENDIAN_IDX to access the same location 39 * in the fpr_t union regardless of the host endianness 40 */ 41 #if HOST_BIG_ENDIAN 42 # define FP_ENDIAN_IDX 1 43 #else 44 # define FP_ENDIAN_IDX 0 45 #endif 46 47 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 48 struct CPUMIPSFPUContext { 49 /* Floating point registers */ 50 fpr_t fpr[32]; 51 float_status fp_status; 52 /* fpu implementation/revision register (fir) */ 53 uint32_t fcr0; 54 #define FCR0_FREP 29 55 #define FCR0_UFRP 28 56 #define FCR0_HAS2008 23 57 #define FCR0_F64 22 58 #define FCR0_L 21 59 #define FCR0_W 20 60 #define FCR0_3D 19 61 #define FCR0_PS 18 62 #define FCR0_D 17 63 #define FCR0_S 16 64 #define FCR0_PRID 8 65 #define FCR0_REV 0 66 /* fcsr */ 67 uint32_t fcr31_rw_bitmask; 68 uint32_t fcr31; 69 #define FCR31_FS 24 70 #define FCR31_ABS2008 19 71 #define FCR31_NAN2008 18 72 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ 73 ((num) ? (1 << ((num) + 24)) : \ 74 (1 << 23)); \ 75 } while (0) 76 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ 77 ~((num) ? (1 << ((num) + 24)) : \ 78 (1 << 23)); \ 79 } while (0) 80 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ 81 (((env).fcr31 >> 23) & 0x1)) 82 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 83 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 84 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 85 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ 86 ((v & 0x3f) << 12); \ 87 } while (0) 88 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ 89 ((v & 0x1f) << 7); \ 90 } while (0) 91 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ 92 ((v & 0x1f) << 2); \ 93 } while (0) 94 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) 95 #define FP_INEXACT 1 96 #define FP_UNDERFLOW 2 97 #define FP_OVERFLOW 4 98 #define FP_DIV0 8 99 #define FP_INVALID 16 100 #define FP_UNIMPLEMENTED 32 101 }; 102 103 #define TARGET_INSN_START_EXTRA_WORDS 2 104 105 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 106 struct CPUMIPSMVPContext { 107 int32_t CP0_MVPControl; 108 #define CP0MVPCo_CPA 3 109 #define CP0MVPCo_STLB 2 110 #define CP0MVPCo_VPC 1 111 #define CP0MVPCo_EVP 0 112 int32_t CP0_MVPConf0; 113 #define CP0MVPC0_M 31 114 #define CP0MVPC0_TLBS 29 115 #define CP0MVPC0_GS 28 116 #define CP0MVPC0_PCP 27 117 #define CP0MVPC0_PTLBE 16 118 #define CP0MVPC0_TCA 15 119 #define CP0MVPC0_PVPE 10 120 #define CP0MVPC0_PTC 0 121 int32_t CP0_MVPConf1; 122 #define CP0MVPC1_CIM 31 123 #define CP0MVPC1_CIF 30 124 #define CP0MVPC1_PCX 20 125 #define CP0MVPC1_PCP2 10 126 #define CP0MVPC1_PCP1 0 127 }; 128 129 typedef struct mips_def_t mips_def_t; 130 131 #define MIPS_SHADOW_SET_MAX 16 132 #define MIPS_TC_MAX 5 133 #define MIPS_FPU_MAX 1 134 #define MIPS_DSP_ACC 4 135 #define MIPS_KSCRATCH_NUM 6 136 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 137 138 139 /* 140 * Summary of CP0 registers 141 * ======================== 142 * 143 * 144 * Register 0 Register 1 Register 2 Register 3 145 * ---------- ---------- ---------- ---------- 146 * 147 * 0 Index Random EntryLo0 EntryLo1 148 * 1 MVPControl VPEControl TCStatus GlobalNumber 149 * 2 MVPConf0 VPEConf0 TCBind 150 * 3 MVPConf1 VPEConf1 TCRestart 151 * 4 VPControl YQMask TCHalt 152 * 5 VPESchedule TCContext 153 * 6 VPEScheFBack TCSchedule 154 * 7 VPEOpt TCScheFBack TCOpt 155 * 156 * 157 * Register 4 Register 5 Register 6 Register 7 158 * ---------- ---------- ---------- ---------- 159 * 160 * 0 Context PageMask Wired HWREna 161 * 1 ContextConfig PageGrain SRSConf0 162 * 2 UserLocal SegCtl0 SRSConf1 163 * 3 XContextConfig SegCtl1 SRSConf2 164 * 4 DebugContextID SegCtl2 SRSConf3 165 * 5 MemoryMapID PWBase SRSConf4 166 * 6 PWField PWCtl 167 * 7 PWSize 168 * 169 * 170 * Register 8 Register 9 Register 10 Register 11 171 * ---------- ---------- ----------- ----------- 172 * 173 * 0 BadVAddr Count EntryHi Compare 174 * 1 BadInstr 175 * 2 BadInstrP 176 * 3 BadInstrX 177 * 4 GuestCtl1 GuestCtl0Ext 178 * 5 GuestCtl2 179 * 6 SAARI GuestCtl3 180 * 7 SAAR 181 * 182 * 183 * Register 12 Register 13 Register 14 Register 15 184 * ----------- ----------- ----------- ----------- 185 * 186 * 0 Status Cause EPC PRId 187 * 1 IntCtl EBase 188 * 2 SRSCtl NestedEPC CDMMBase 189 * 3 SRSMap CMGCRBase 190 * 4 View_IPL View_RIPL BEVVA 191 * 5 SRSMap2 NestedExc 192 * 6 GuestCtl0 193 * 7 GTOffset 194 * 195 * 196 * Register 16 Register 17 Register 18 Register 19 197 * ----------- ----------- ----------- ----------- 198 * 199 * 0 Config LLAddr WatchLo0 WatchHi 200 * 1 Config1 MAAR WatchLo1 WatchHi 201 * 2 Config2 MAARI WatchLo2 WatchHi 202 * 3 Config3 WatchLo3 WatchHi 203 * 4 Config4 WatchLo4 WatchHi 204 * 5 Config5 WatchLo5 WatchHi 205 * 6 Config6 WatchLo6 WatchHi 206 * 7 Config7 WatchLo7 WatchHi 207 * 208 * 209 * Register 20 Register 21 Register 22 Register 23 210 * ----------- ----------- ----------- ----------- 211 * 212 * 0 XContext Debug 213 * 1 TraceControl 214 * 2 TraceControl2 215 * 3 UserTraceData1 216 * 4 TraceIBPC 217 * 5 TraceDBPC 218 * 6 Debug2 219 * 7 220 * 221 * 222 * Register 24 Register 25 Register 26 Register 27 223 * ----------- ----------- ----------- ----------- 224 * 225 * 0 DEPC PerfCnt ErrCtl CacheErr 226 * 1 PerfCnt 227 * 2 TraceControl3 PerfCnt 228 * 3 UserTraceData2 PerfCnt 229 * 4 PerfCnt 230 * 5 PerfCnt 231 * 6 PerfCnt 232 * 7 PerfCnt 233 * 234 * 235 * Register 28 Register 29 Register 30 Register 31 236 * ----------- ----------- ----------- ----------- 237 * 238 * 0 DataLo DataHi ErrorEPC DESAVE 239 * 1 TagLo TagHi 240 * 2 DataLo1 DataHi1 KScratch<n> 241 * 3 TagLo1 TagHi1 KScratch<n> 242 * 4 DataLo2 DataHi2 KScratch<n> 243 * 5 TagLo2 TagHi2 KScratch<n> 244 * 6 DataLo3 DataHi3 KScratch<n> 245 * 7 TagLo3 TagHi3 KScratch<n> 246 * 247 */ 248 #define CP0_REGISTER_00 0 249 #define CP0_REGISTER_01 1 250 #define CP0_REGISTER_02 2 251 #define CP0_REGISTER_03 3 252 #define CP0_REGISTER_04 4 253 #define CP0_REGISTER_05 5 254 #define CP0_REGISTER_06 6 255 #define CP0_REGISTER_07 7 256 #define CP0_REGISTER_08 8 257 #define CP0_REGISTER_09 9 258 #define CP0_REGISTER_10 10 259 #define CP0_REGISTER_11 11 260 #define CP0_REGISTER_12 12 261 #define CP0_REGISTER_13 13 262 #define CP0_REGISTER_14 14 263 #define CP0_REGISTER_15 15 264 #define CP0_REGISTER_16 16 265 #define CP0_REGISTER_17 17 266 #define CP0_REGISTER_18 18 267 #define CP0_REGISTER_19 19 268 #define CP0_REGISTER_20 20 269 #define CP0_REGISTER_21 21 270 #define CP0_REGISTER_22 22 271 #define CP0_REGISTER_23 23 272 #define CP0_REGISTER_24 24 273 #define CP0_REGISTER_25 25 274 #define CP0_REGISTER_26 26 275 #define CP0_REGISTER_27 27 276 #define CP0_REGISTER_28 28 277 #define CP0_REGISTER_29 29 278 #define CP0_REGISTER_30 30 279 #define CP0_REGISTER_31 31 280 281 282 /* CP0 Register 00 */ 283 #define CP0_REG00__INDEX 0 284 #define CP0_REG00__MVPCONTROL 1 285 #define CP0_REG00__MVPCONF0 2 286 #define CP0_REG00__MVPCONF1 3 287 #define CP0_REG00__VPCONTROL 4 288 /* CP0 Register 01 */ 289 #define CP0_REG01__RANDOM 0 290 #define CP0_REG01__VPECONTROL 1 291 #define CP0_REG01__VPECONF0 2 292 #define CP0_REG01__VPECONF1 3 293 #define CP0_REG01__YQMASK 4 294 #define CP0_REG01__VPESCHEDULE 5 295 #define CP0_REG01__VPESCHEFBACK 6 296 #define CP0_REG01__VPEOPT 7 297 /* CP0 Register 02 */ 298 #define CP0_REG02__ENTRYLO0 0 299 #define CP0_REG02__TCSTATUS 1 300 #define CP0_REG02__TCBIND 2 301 #define CP0_REG02__TCRESTART 3 302 #define CP0_REG02__TCHALT 4 303 #define CP0_REG02__TCCONTEXT 5 304 #define CP0_REG02__TCSCHEDULE 6 305 #define CP0_REG02__TCSCHEFBACK 7 306 /* CP0 Register 03 */ 307 #define CP0_REG03__ENTRYLO1 0 308 #define CP0_REG03__GLOBALNUM 1 309 #define CP0_REG03__TCOPT 7 310 /* CP0 Register 04 */ 311 #define CP0_REG04__CONTEXT 0 312 #define CP0_REG04__CONTEXTCONFIG 1 313 #define CP0_REG04__USERLOCAL 2 314 #define CP0_REG04__XCONTEXTCONFIG 3 315 #define CP0_REG04__DBGCONTEXTID 4 316 #define CP0_REG04__MMID 5 317 /* CP0 Register 05 */ 318 #define CP0_REG05__PAGEMASK 0 319 #define CP0_REG05__PAGEGRAIN 1 320 #define CP0_REG05__SEGCTL0 2 321 #define CP0_REG05__SEGCTL1 3 322 #define CP0_REG05__SEGCTL2 4 323 #define CP0_REG05__PWBASE 5 324 #define CP0_REG05__PWFIELD 6 325 #define CP0_REG05__PWSIZE 7 326 /* CP0 Register 06 */ 327 #define CP0_REG06__WIRED 0 328 #define CP0_REG06__SRSCONF0 1 329 #define CP0_REG06__SRSCONF1 2 330 #define CP0_REG06__SRSCONF2 3 331 #define CP0_REG06__SRSCONF3 4 332 #define CP0_REG06__SRSCONF4 5 333 #define CP0_REG06__PWCTL 6 334 /* CP0 Register 07 */ 335 #define CP0_REG07__HWRENA 0 336 /* CP0 Register 08 */ 337 #define CP0_REG08__BADVADDR 0 338 #define CP0_REG08__BADINSTR 1 339 #define CP0_REG08__BADINSTRP 2 340 #define CP0_REG08__BADINSTRX 3 341 /* CP0 Register 09 */ 342 #define CP0_REG09__COUNT 0 343 #define CP0_REG09__SAARI 6 344 #define CP0_REG09__SAAR 7 345 /* CP0 Register 10 */ 346 #define CP0_REG10__ENTRYHI 0 347 #define CP0_REG10__GUESTCTL1 4 348 #define CP0_REG10__GUESTCTL2 5 349 #define CP0_REG10__GUESTCTL3 6 350 /* CP0 Register 11 */ 351 #define CP0_REG11__COMPARE 0 352 #define CP0_REG11__GUESTCTL0EXT 4 353 /* CP0 Register 12 */ 354 #define CP0_REG12__STATUS 0 355 #define CP0_REG12__INTCTL 1 356 #define CP0_REG12__SRSCTL 2 357 #define CP0_REG12__SRSMAP 3 358 #define CP0_REG12__VIEW_IPL 4 359 #define CP0_REG12__SRSMAP2 5 360 #define CP0_REG12__GUESTCTL0 6 361 #define CP0_REG12__GTOFFSET 7 362 /* CP0 Register 13 */ 363 #define CP0_REG13__CAUSE 0 364 #define CP0_REG13__VIEW_RIPL 4 365 #define CP0_REG13__NESTEDEXC 5 366 /* CP0 Register 14 */ 367 #define CP0_REG14__EPC 0 368 #define CP0_REG14__NESTEDEPC 2 369 /* CP0 Register 15 */ 370 #define CP0_REG15__PRID 0 371 #define CP0_REG15__EBASE 1 372 #define CP0_REG15__CDMMBASE 2 373 #define CP0_REG15__CMGCRBASE 3 374 #define CP0_REG15__BEVVA 4 375 /* CP0 Register 16 */ 376 #define CP0_REG16__CONFIG 0 377 #define CP0_REG16__CONFIG1 1 378 #define CP0_REG16__CONFIG2 2 379 #define CP0_REG16__CONFIG3 3 380 #define CP0_REG16__CONFIG4 4 381 #define CP0_REG16__CONFIG5 5 382 #define CP0_REG16__CONFIG6 6 383 #define CP0_REG16__CONFIG7 7 384 /* CP0 Register 17 */ 385 #define CP0_REG17__LLADDR 0 386 #define CP0_REG17__MAAR 1 387 #define CP0_REG17__MAARI 2 388 /* CP0 Register 18 */ 389 #define CP0_REG18__WATCHLO0 0 390 #define CP0_REG18__WATCHLO1 1 391 #define CP0_REG18__WATCHLO2 2 392 #define CP0_REG18__WATCHLO3 3 393 #define CP0_REG18__WATCHLO4 4 394 #define CP0_REG18__WATCHLO5 5 395 #define CP0_REG18__WATCHLO6 6 396 #define CP0_REG18__WATCHLO7 7 397 /* CP0 Register 19 */ 398 #define CP0_REG19__WATCHHI0 0 399 #define CP0_REG19__WATCHHI1 1 400 #define CP0_REG19__WATCHHI2 2 401 #define CP0_REG19__WATCHHI3 3 402 #define CP0_REG19__WATCHHI4 4 403 #define CP0_REG19__WATCHHI5 5 404 #define CP0_REG19__WATCHHI6 6 405 #define CP0_REG19__WATCHHI7 7 406 /* CP0 Register 20 */ 407 #define CP0_REG20__XCONTEXT 0 408 /* CP0 Register 21 */ 409 /* CP0 Register 22 */ 410 /* CP0 Register 23 */ 411 #define CP0_REG23__DEBUG 0 412 #define CP0_REG23__TRACECONTROL 1 413 #define CP0_REG23__TRACECONTROL2 2 414 #define CP0_REG23__USERTRACEDATA1 3 415 #define CP0_REG23__TRACEIBPC 4 416 #define CP0_REG23__TRACEDBPC 5 417 #define CP0_REG23__DEBUG2 6 418 /* CP0 Register 24 */ 419 #define CP0_REG24__DEPC 0 420 /* CP0 Register 25 */ 421 #define CP0_REG25__PERFCTL0 0 422 #define CP0_REG25__PERFCNT0 1 423 #define CP0_REG25__PERFCTL1 2 424 #define CP0_REG25__PERFCNT1 3 425 #define CP0_REG25__PERFCTL2 4 426 #define CP0_REG25__PERFCNT2 5 427 #define CP0_REG25__PERFCTL3 6 428 #define CP0_REG25__PERFCNT3 7 429 /* CP0 Register 26 */ 430 #define CP0_REG26__ERRCTL 0 431 /* CP0 Register 27 */ 432 #define CP0_REG27__CACHERR 0 433 /* CP0 Register 28 */ 434 #define CP0_REG28__TAGLO 0 435 #define CP0_REG28__DATALO 1 436 #define CP0_REG28__TAGLO1 2 437 #define CP0_REG28__DATALO1 3 438 #define CP0_REG28__TAGLO2 4 439 #define CP0_REG28__DATALO2 5 440 #define CP0_REG28__TAGLO3 6 441 #define CP0_REG28__DATALO3 7 442 /* CP0 Register 29 */ 443 #define CP0_REG29__TAGHI 0 444 #define CP0_REG29__DATAHI 1 445 #define CP0_REG29__TAGHI1 2 446 #define CP0_REG29__DATAHI1 3 447 #define CP0_REG29__TAGHI2 4 448 #define CP0_REG29__DATAHI2 5 449 #define CP0_REG29__TAGHI3 6 450 #define CP0_REG29__DATAHI3 7 451 /* CP0 Register 30 */ 452 #define CP0_REG30__ERROREPC 0 453 /* CP0 Register 31 */ 454 #define CP0_REG31__DESAVE 0 455 #define CP0_REG31__KSCRATCH1 2 456 #define CP0_REG31__KSCRATCH2 3 457 #define CP0_REG31__KSCRATCH3 4 458 #define CP0_REG31__KSCRATCH4 5 459 #define CP0_REG31__KSCRATCH5 6 460 #define CP0_REG31__KSCRATCH6 7 461 462 463 typedef struct TCState TCState; 464 struct TCState { 465 target_ulong gpr[32]; 466 #if defined(TARGET_MIPS64) 467 /* 468 * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[]) 469 * and the upper halves in gpr_hi[]. 470 */ 471 uint64_t gpr_hi[32]; 472 #endif /* TARGET_MIPS64 */ 473 target_ulong PC; 474 target_ulong HI[MIPS_DSP_ACC]; 475 target_ulong LO[MIPS_DSP_ACC]; 476 target_ulong ACX[MIPS_DSP_ACC]; 477 target_ulong DSPControl; 478 int32_t CP0_TCStatus; 479 #define CP0TCSt_TCU3 31 480 #define CP0TCSt_TCU2 30 481 #define CP0TCSt_TCU1 29 482 #define CP0TCSt_TCU0 28 483 #define CP0TCSt_TMX 27 484 #define CP0TCSt_RNST 23 485 #define CP0TCSt_TDS 21 486 #define CP0TCSt_DT 20 487 #define CP0TCSt_DA 15 488 #define CP0TCSt_A 13 489 #define CP0TCSt_TKSU 11 490 #define CP0TCSt_IXMT 10 491 #define CP0TCSt_TASID 0 492 int32_t CP0_TCBind; 493 #define CP0TCBd_CurTC 21 494 #define CP0TCBd_TBE 17 495 #define CP0TCBd_CurVPE 0 496 target_ulong CP0_TCHalt; 497 target_ulong CP0_TCContext; 498 target_ulong CP0_TCSchedule; 499 target_ulong CP0_TCScheFBack; 500 int32_t CP0_Debug_tcstatus; 501 target_ulong CP0_UserLocal; 502 503 int32_t msacsr; 504 505 #define MSACSR_FS 24 506 #define MSACSR_FS_MASK (1 << MSACSR_FS) 507 #define MSACSR_NX 18 508 #define MSACSR_NX_MASK (1 << MSACSR_NX) 509 #define MSACSR_CEF 2 510 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 511 #define MSACSR_RM 0 512 #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 513 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 514 MSACSR_FS_MASK) 515 516 float_status msa_fp_status; 517 518 #define NUMBER_OF_MXU_REGISTERS 16 519 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; 520 target_ulong mxu_cr; 521 #define MXU_CR_LC 31 522 #define MXU_CR_RC 30 523 #define MXU_CR_BIAS 2 524 #define MXU_CR_RD_EN 1 525 #define MXU_CR_MXU_EN 0 526 527 }; 528 529 struct MIPSITUState; 530 typedef struct CPUArchState { 531 TCState active_tc; 532 CPUMIPSFPUContext active_fpu; 533 534 uint32_t current_tc; 535 536 uint32_t SEGBITS; 537 uint32_t PABITS; 538 #if defined(TARGET_MIPS64) 539 # define PABITS_BASE 36 540 #else 541 # define PABITS_BASE 32 542 #endif 543 target_ulong SEGMask; 544 uint64_t PAMask; 545 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 546 547 int32_t msair; 548 #define MSAIR_ProcID 8 549 #define MSAIR_Rev 0 550 551 /* 552 * CP0 Register 0 553 */ 554 int32_t CP0_Index; 555 /* CP0_MVP* are per MVP registers. */ 556 int32_t CP0_VPControl; 557 #define CP0VPCtl_DIS 0 558 /* 559 * CP0 Register 1 560 */ 561 int32_t CP0_Random; 562 int32_t CP0_VPEControl; 563 #define CP0VPECo_YSI 21 564 #define CP0VPECo_GSI 20 565 #define CP0VPECo_EXCPT 16 566 #define CP0VPECo_TE 15 567 #define CP0VPECo_TargTC 0 568 int32_t CP0_VPEConf0; 569 #define CP0VPEC0_M 31 570 #define CP0VPEC0_XTC 21 571 #define CP0VPEC0_TCS 19 572 #define CP0VPEC0_SCS 18 573 #define CP0VPEC0_DSC 17 574 #define CP0VPEC0_ICS 16 575 #define CP0VPEC0_MVP 1 576 #define CP0VPEC0_VPA 0 577 int32_t CP0_VPEConf1; 578 #define CP0VPEC1_NCX 20 579 #define CP0VPEC1_NCP2 10 580 #define CP0VPEC1_NCP1 0 581 target_ulong CP0_YQMask; 582 target_ulong CP0_VPESchedule; 583 target_ulong CP0_VPEScheFBack; 584 int32_t CP0_VPEOpt; 585 #define CP0VPEOpt_IWX7 15 586 #define CP0VPEOpt_IWX6 14 587 #define CP0VPEOpt_IWX5 13 588 #define CP0VPEOpt_IWX4 12 589 #define CP0VPEOpt_IWX3 11 590 #define CP0VPEOpt_IWX2 10 591 #define CP0VPEOpt_IWX1 9 592 #define CP0VPEOpt_IWX0 8 593 #define CP0VPEOpt_DWX7 7 594 #define CP0VPEOpt_DWX6 6 595 #define CP0VPEOpt_DWX5 5 596 #define CP0VPEOpt_DWX4 4 597 #define CP0VPEOpt_DWX3 3 598 #define CP0VPEOpt_DWX2 2 599 #define CP0VPEOpt_DWX1 1 600 #define CP0VPEOpt_DWX0 0 601 /* 602 * CP0 Register 2 603 */ 604 uint64_t CP0_EntryLo0; 605 /* 606 * CP0 Register 3 607 */ 608 uint64_t CP0_EntryLo1; 609 #if defined(TARGET_MIPS64) 610 # define CP0EnLo_RI 63 611 # define CP0EnLo_XI 62 612 #else 613 # define CP0EnLo_RI 31 614 # define CP0EnLo_XI 30 615 #endif 616 int32_t CP0_GlobalNumber; 617 #define CP0GN_VPId 0 618 /* 619 * CP0 Register 4 620 */ 621 target_ulong CP0_Context; 622 int32_t CP0_MemoryMapID; 623 /* 624 * CP0 Register 5 625 */ 626 int32_t CP0_PageMask; 627 #define CP0PM_MASK 13 628 int32_t CP0_PageGrain_rw_bitmask; 629 int32_t CP0_PageGrain; 630 #define CP0PG_RIE 31 631 #define CP0PG_XIE 30 632 #define CP0PG_ELPA 29 633 #define CP0PG_IEC 27 634 target_ulong CP0_SegCtl0; 635 target_ulong CP0_SegCtl1; 636 target_ulong CP0_SegCtl2; 637 #define CP0SC_PA 9 638 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) 639 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) 640 #define CP0SC_AM 4 641 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) 642 #define CP0SC_AM_UK 0ULL 643 #define CP0SC_AM_MK 1ULL 644 #define CP0SC_AM_MSK 2ULL 645 #define CP0SC_AM_MUSK 3ULL 646 #define CP0SC_AM_MUSUK 4ULL 647 #define CP0SC_AM_USK 5ULL 648 #define CP0SC_AM_UUSK 7ULL 649 #define CP0SC_EU 3 650 #define CP0SC_EU_MASK (1ULL << CP0SC_EU) 651 #define CP0SC_C 0 652 #define CP0SC_C_MASK (0x7ULL << CP0SC_C) 653 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 654 CP0SC_PA_MASK) 655 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 656 CP0SC_PA_1GMASK) 657 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) 658 #define CP0SC1_XAM 59 659 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) 660 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) 661 #define CP0SC2_XR 56 662 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) 663 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) 664 target_ulong CP0_PWBase; 665 target_ulong CP0_PWField; 666 #if defined(TARGET_MIPS64) 667 #define CP0PF_BDI 32 /* 37..32 */ 668 #define CP0PF_GDI 24 /* 29..24 */ 669 #define CP0PF_UDI 18 /* 23..18 */ 670 #define CP0PF_MDI 12 /* 17..12 */ 671 #define CP0PF_PTI 6 /* 11..6 */ 672 #define CP0PF_PTEI 0 /* 5..0 */ 673 #else 674 #define CP0PF_GDW 24 /* 29..24 */ 675 #define CP0PF_UDW 18 /* 23..18 */ 676 #define CP0PF_MDW 12 /* 17..12 */ 677 #define CP0PF_PTW 6 /* 11..6 */ 678 #define CP0PF_PTEW 0 /* 5..0 */ 679 #endif 680 target_ulong CP0_PWSize; 681 #if defined(TARGET_MIPS64) 682 #define CP0PS_BDW 32 /* 37..32 */ 683 #endif 684 #define CP0PS_PS 30 685 #define CP0PS_GDW 24 /* 29..24 */ 686 #define CP0PS_UDW 18 /* 23..18 */ 687 #define CP0PS_MDW 12 /* 17..12 */ 688 #define CP0PS_PTW 6 /* 11..6 */ 689 #define CP0PS_PTEW 0 /* 5..0 */ 690 /* 691 * CP0 Register 6 692 */ 693 int32_t CP0_Wired; 694 int32_t CP0_PWCtl; 695 #define CP0PC_PWEN 31 696 #if defined(TARGET_MIPS64) 697 #define CP0PC_PWDIREXT 30 698 #define CP0PC_XK 28 699 #define CP0PC_XS 27 700 #define CP0PC_XU 26 701 #endif 702 #define CP0PC_DPH 7 703 #define CP0PC_HUGEPG 6 704 #define CP0PC_PSN 0 /* 5..0 */ 705 int32_t CP0_SRSConf0_rw_bitmask; 706 int32_t CP0_SRSConf0; 707 #define CP0SRSC0_M 31 708 #define CP0SRSC0_SRS3 20 709 #define CP0SRSC0_SRS2 10 710 #define CP0SRSC0_SRS1 0 711 int32_t CP0_SRSConf1_rw_bitmask; 712 int32_t CP0_SRSConf1; 713 #define CP0SRSC1_M 31 714 #define CP0SRSC1_SRS6 20 715 #define CP0SRSC1_SRS5 10 716 #define CP0SRSC1_SRS4 0 717 int32_t CP0_SRSConf2_rw_bitmask; 718 int32_t CP0_SRSConf2; 719 #define CP0SRSC2_M 31 720 #define CP0SRSC2_SRS9 20 721 #define CP0SRSC2_SRS8 10 722 #define CP0SRSC2_SRS7 0 723 int32_t CP0_SRSConf3_rw_bitmask; 724 int32_t CP0_SRSConf3; 725 #define CP0SRSC3_M 31 726 #define CP0SRSC3_SRS12 20 727 #define CP0SRSC3_SRS11 10 728 #define CP0SRSC3_SRS10 0 729 int32_t CP0_SRSConf4_rw_bitmask; 730 int32_t CP0_SRSConf4; 731 #define CP0SRSC4_SRS15 20 732 #define CP0SRSC4_SRS14 10 733 #define CP0SRSC4_SRS13 0 734 /* 735 * CP0 Register 7 736 */ 737 int32_t CP0_HWREna; 738 /* 739 * CP0 Register 8 740 */ 741 target_ulong CP0_BadVAddr; 742 uint32_t CP0_BadInstr; 743 uint32_t CP0_BadInstrP; 744 uint32_t CP0_BadInstrX; 745 /* 746 * CP0 Register 9 747 */ 748 int32_t CP0_Count; 749 #define CP0SAARI_TARGET 0 /* 5..0 */ 750 #define CP0SAAR_BASE 12 /* 43..12 */ 751 #define CP0SAAR_SIZE 1 /* 5..1 */ 752 #define CP0SAAR_EN 0 753 /* 754 * CP0 Register 10 755 */ 756 target_ulong CP0_EntryHi; 757 #define CP0EnHi_EHINV 10 758 target_ulong CP0_EntryHi_ASID_mask; 759 /* 760 * CP0 Register 11 761 */ 762 int32_t CP0_Compare; 763 /* 764 * CP0 Register 12 765 */ 766 int32_t CP0_Status; 767 #define CP0St_CU3 31 768 #define CP0St_CU2 30 769 #define CP0St_CU1 29 770 #define CP0St_CU0 28 771 #define CP0St_RP 27 772 #define CP0St_FR 26 773 #define CP0St_RE 25 774 #define CP0St_MX 24 775 #define CP0St_PX 23 776 #define CP0St_BEV 22 777 #define CP0St_TS 21 778 #define CP0St_SR 20 779 #define CP0St_NMI 19 780 #define CP0St_IM 8 781 #define CP0St_KX 7 782 #define CP0St_SX 6 783 #define CP0St_UX 5 784 #define CP0St_KSU 3 785 #define CP0St_ERL 2 786 #define CP0St_EXL 1 787 #define CP0St_IE 0 788 int32_t CP0_IntCtl; 789 #define CP0IntCtl_IPTI 29 790 #define CP0IntCtl_IPPCI 26 791 #define CP0IntCtl_VS 5 792 int32_t CP0_SRSCtl; 793 #define CP0SRSCtl_HSS 26 794 #define CP0SRSCtl_EICSS 18 795 #define CP0SRSCtl_ESS 12 796 #define CP0SRSCtl_PSS 6 797 #define CP0SRSCtl_CSS 0 798 int32_t CP0_SRSMap; 799 #define CP0SRSMap_SSV7 28 800 #define CP0SRSMap_SSV6 24 801 #define CP0SRSMap_SSV5 20 802 #define CP0SRSMap_SSV4 16 803 #define CP0SRSMap_SSV3 12 804 #define CP0SRSMap_SSV2 8 805 #define CP0SRSMap_SSV1 4 806 #define CP0SRSMap_SSV0 0 807 /* 808 * CP0 Register 13 809 */ 810 int32_t CP0_Cause; 811 #define CP0Ca_BD 31 812 #define CP0Ca_TI 30 813 #define CP0Ca_CE 28 814 #define CP0Ca_DC 27 815 #define CP0Ca_PCI 26 816 #define CP0Ca_IV 23 817 #define CP0Ca_WP 22 818 #define CP0Ca_IP 8 819 #define CP0Ca_IP_mask 0x0000FF00 820 #define CP0Ca_EC 2 821 /* 822 * CP0 Register 14 823 */ 824 target_ulong CP0_EPC; 825 /* 826 * CP0 Register 15 827 */ 828 int32_t CP0_PRid; 829 target_ulong CP0_EBase; 830 target_ulong CP0_EBaseWG_rw_bitmask; 831 #define CP0EBase_WG 11 832 target_ulong CP0_CMGCRBase; 833 /* 834 * CP0 Register 16 (after Release 1) 835 */ 836 int32_t CP0_Config0; 837 #define CP0C0_M 31 838 #define CP0C0_K23 28 /* 30..28 */ 839 #define CP0C0_KU 25 /* 27..25 */ 840 #define CP0C0_MDU 20 841 #define CP0C0_MM 18 842 #define CP0C0_BM 16 843 #define CP0C0_Impl 16 /* 24..16 */ 844 #define CP0C0_BE 15 845 #define CP0C0_AT 13 /* 14..13 */ 846 #define CP0C0_AR 10 /* 12..10 */ 847 #define CP0C0_MT 7 /* 9..7 */ 848 #define CP0C0_VI 3 849 #define CP0C0_K0 0 /* 2..0 */ 850 #define CP0C0_AR_LENGTH 3 851 /* 852 * CP0 Register 16 (before Release 1) 853 */ 854 #define CP0C0_Impl 16 /* 24..16 */ 855 #define CP0C0_IC 9 /* 11..9 */ 856 #define CP0C0_DC 6 /* 8..6 */ 857 #define CP0C0_IB 5 858 #define CP0C0_DB 4 859 int32_t CP0_Config1; 860 #define CP0C1_M 31 861 #define CP0C1_MMU 25 /* 30..25 */ 862 #define CP0C1_IS 22 /* 24..22 */ 863 #define CP0C1_IL 19 /* 21..19 */ 864 #define CP0C1_IA 16 /* 18..16 */ 865 #define CP0C1_DS 13 /* 15..13 */ 866 #define CP0C1_DL 10 /* 12..10 */ 867 #define CP0C1_DA 7 /* 9..7 */ 868 #define CP0C1_C2 6 869 #define CP0C1_MD 5 870 #define CP0C1_PC 4 871 #define CP0C1_WR 3 872 #define CP0C1_CA 2 873 #define CP0C1_EP 1 874 #define CP0C1_FP 0 875 int32_t CP0_Config2; 876 #define CP0C2_M 31 877 #define CP0C2_TU 28 /* 30..28 */ 878 #define CP0C2_TS 24 /* 27..24 */ 879 #define CP0C2_TL 20 /* 23..20 */ 880 #define CP0C2_TA 16 /* 19..16 */ 881 #define CP0C2_SU 12 /* 15..12 */ 882 #define CP0C2_SS 8 /* 11..8 */ 883 #define CP0C2_SL 4 /* 7..4 */ 884 #define CP0C2_SA 0 /* 3..0 */ 885 int32_t CP0_Config3; 886 #define CP0C3_M 31 887 #define CP0C3_BPG 30 888 #define CP0C3_CMGCR 29 889 #define CP0C3_MSAP 28 890 #define CP0C3_BP 27 891 #define CP0C3_BI 26 892 #define CP0C3_SC 25 893 #define CP0C3_PW 24 894 #define CP0C3_VZ 23 895 #define CP0C3_IPLV 21 /* 22..21 */ 896 #define CP0C3_MMAR 18 /* 20..18 */ 897 #define CP0C3_MCU 17 898 #define CP0C3_ISA_ON_EXC 16 899 #define CP0C3_ISA 14 /* 15..14 */ 900 #define CP0C3_ULRI 13 901 #define CP0C3_RXI 12 902 #define CP0C3_DSP2P 11 903 #define CP0C3_DSPP 10 904 #define CP0C3_CTXTC 9 905 #define CP0C3_ITL 8 906 #define CP0C3_LPA 7 907 #define CP0C3_VEIC 6 908 #define CP0C3_VInt 5 909 #define CP0C3_SP 4 910 #define CP0C3_CDMM 3 911 #define CP0C3_MT 2 912 #define CP0C3_SM 1 913 #define CP0C3_TL 0 914 int32_t CP0_Config4; 915 int32_t CP0_Config4_rw_bitmask; 916 #define CP0C4_M 31 917 #define CP0C4_IE 29 /* 30..29 */ 918 #define CP0C4_AE 28 919 #define CP0C4_VTLBSizeExt 24 /* 27..24 */ 920 #define CP0C4_KScrExist 16 921 #define CP0C4_MMUExtDef 14 922 #define CP0C4_FTLBPageSize 8 /* 12..8 */ 923 /* bit layout if MMUExtDef=1 */ 924 #define CP0C4_MMUSizeExt 0 /* 7..0 */ 925 /* bit layout if MMUExtDef=2 */ 926 #define CP0C4_FTLBWays 4 /* 7..4 */ 927 #define CP0C4_FTLBSets 0 /* 3..0 */ 928 int32_t CP0_Config5; 929 int32_t CP0_Config5_rw_bitmask; 930 #define CP0C5_M 31 931 #define CP0C5_K 30 932 #define CP0C5_CV 29 933 #define CP0C5_EVA 28 934 #define CP0C5_MSAEn 27 935 #define CP0C5_PMJ 23 /* 25..23 */ 936 #define CP0C5_WR2 22 937 #define CP0C5_NMS 21 938 #define CP0C5_ULS 20 939 #define CP0C5_XPA 19 940 #define CP0C5_CRCP 18 941 #define CP0C5_MI 17 942 #define CP0C5_GI 15 /* 16..15 */ 943 #define CP0C5_CA2 14 944 #define CP0C5_XNP 13 945 #define CP0C5_DEC 11 946 #define CP0C5_L2C 10 947 #define CP0C5_UFE 9 948 #define CP0C5_FRE 8 949 #define CP0C5_VP 7 950 #define CP0C5_SBRI 6 951 #define CP0C5_MVH 5 952 #define CP0C5_LLB 4 953 #define CP0C5_MRP 3 954 #define CP0C5_UFR 2 955 #define CP0C5_NFExists 0 956 int32_t CP0_Config6; 957 int32_t CP0_Config6_rw_bitmask; 958 #define CP0C6_BPPASS 31 959 #define CP0C6_KPOS 24 960 #define CP0C6_KE 23 961 #define CP0C6_VTLBONLY 22 962 #define CP0C6_LASX 21 963 #define CP0C6_SSEN 20 964 #define CP0C6_DISDRTIME 19 965 #define CP0C6_PIXNUEN 18 966 #define CP0C6_SCRAND 17 967 #define CP0C6_LLEXCEN 16 968 #define CP0C6_DISVC 15 969 #define CP0C6_VCLRU 14 970 #define CP0C6_DCLRU 13 971 #define CP0C6_PIXUEN 12 972 #define CP0C6_DISBLKLYEN 11 973 #define CP0C6_UMEMUALEN 10 974 #define CP0C6_SFBEN 8 975 #define CP0C6_FLTINT 7 976 #define CP0C6_VLTINT 6 977 #define CP0C6_DISBTB 5 978 #define CP0C6_STPREFCTL 2 979 #define CP0C6_INSTPREF 1 980 #define CP0C6_DATAPREF 0 981 int32_t CP0_Config7; 982 int64_t CP0_Config7_rw_bitmask; 983 #define CP0C7_WII 31 984 #define CP0C7_NAPCGEN 2 985 #define CP0C7_UNIMUEN 1 986 #define CP0C7_VFPUCGEN 0 987 uint64_t CP0_LLAddr; 988 uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 989 int32_t CP0_MAARI; 990 /* XXX: Maybe make LLAddr per-TC? */ 991 /* 992 * CP0 Register 17 993 */ 994 target_ulong lladdr; /* LL virtual address compared against SC */ 995 target_ulong llval; 996 uint64_t llval_wp; 997 uint32_t llnewval_wp; 998 uint64_t CP0_LLAddr_rw_bitmask; 999 int CP0_LLAddr_shift; 1000 /* 1001 * CP0 Register 18 1002 */ 1003 target_ulong CP0_WatchLo[8]; 1004 /* 1005 * CP0 Register 19 1006 */ 1007 uint64_t CP0_WatchHi[8]; 1008 #define CP0WH_ASID 16 1009 #define CP0WH_M 31 1010 /* 1011 * CP0 Register 20 1012 */ 1013 target_ulong CP0_XContext; 1014 int32_t CP0_Framemask; 1015 /* 1016 * CP0 Register 23 1017 */ 1018 int32_t CP0_Debug; 1019 #define CP0DB_DBD 31 1020 #define CP0DB_DM 30 1021 #define CP0DB_LSNM 28 1022 #define CP0DB_Doze 27 1023 #define CP0DB_Halt 26 1024 #define CP0DB_CNT 25 1025 #define CP0DB_IBEP 24 1026 #define CP0DB_DBEP 21 1027 #define CP0DB_IEXI 20 1028 #define CP0DB_VER 15 1029 #define CP0DB_DEC 10 1030 #define CP0DB_SSt 8 1031 #define CP0DB_DINT 5 1032 #define CP0DB_DIB 4 1033 #define CP0DB_DDBS 3 1034 #define CP0DB_DDBL 2 1035 #define CP0DB_DBp 1 1036 #define CP0DB_DSS 0 1037 /* 1038 * CP0 Register 24 1039 */ 1040 target_ulong CP0_DEPC; 1041 /* 1042 * CP0 Register 25 1043 */ 1044 int32_t CP0_Performance0; 1045 /* 1046 * CP0 Register 26 1047 */ 1048 int32_t CP0_ErrCtl; 1049 #define CP0EC_WST 29 1050 #define CP0EC_SPR 28 1051 #define CP0EC_ITC 26 1052 /* 1053 * CP0 Register 28 1054 */ 1055 uint64_t CP0_TagLo; 1056 int32_t CP0_DataLo; 1057 /* 1058 * CP0 Register 29 1059 */ 1060 int32_t CP0_TagHi; 1061 int32_t CP0_DataHi; 1062 /* 1063 * CP0 Register 30 1064 */ 1065 target_ulong CP0_ErrorEPC; 1066 /* 1067 * CP0 Register 31 1068 */ 1069 int32_t CP0_DESAVE; 1070 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 1071 /* 1072 * Loongson CSR CPUCFG registers 1073 */ 1074 uint32_t lcsr_cpucfg1; 1075 #define CPUCFG1_FP 0 1076 #define CPUCFG1_FPREV 1 1077 #define CPUCFG1_MMI 4 1078 #define CPUCFG1_MSA1 5 1079 #define CPUCFG1_MSA2 6 1080 #define CPUCFG1_LSLDR0 16 1081 #define CPUCFG1_LSPERF 17 1082 #define CPUCFG1_LSPERFX 18 1083 #define CPUCFG1_LSSYNCI 19 1084 #define CPUCFG1_LLEXC 20 1085 #define CPUCFG1_SCRAND 21 1086 #define CPUCFG1_MUALP 25 1087 #define CPUCFG1_KMUALEN 26 1088 #define CPUCFG1_ITLBT 27 1089 #define CPUCFG1_SFBP 29 1090 #define CPUCFG1_CDMAP 30 1091 uint32_t lcsr_cpucfg2; 1092 #define CPUCFG2_LEXT1 0 1093 #define CPUCFG2_LEXT2 1 1094 #define CPUCFG2_LEXT3 2 1095 #define CPUCFG2_LSPW 3 1096 #define CPUCFG2_LCSRP 27 1097 #define CPUCFG2_LDISBLIKELY 28 1098 1099 /* We waste some space so we can handle shadow registers like TCs. */ 1100 TCState tcs[MIPS_SHADOW_SET_MAX]; 1101 CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 1102 /* QEMU */ 1103 int error_code; 1104 #define EXCP_TLB_NOMATCH 0x1 1105 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 1106 uint32_t hflags; /* CPU State */ 1107 /* TMASK defines different execution modes */ 1108 #define MIPS_HFLAG_TMASK 0x3F5807FF 1109 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 1110 /* 1111 * The KSU flags must be the lowest bits in hflags. The flag order 1112 * must be the same as defined for CP0 Status. This allows to use 1113 * the bits as the value of mmu_idx. 1114 */ 1115 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 1116 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 1117 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 1118 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 1119 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 1120 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 1121 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 1122 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 1123 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 1124 /* 1125 * True if the MIPS IV COP1X instructions can be used. This also 1126 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 1127 * and RSQRT.D. 1128 */ 1129 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 1130 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 1131 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 1132 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 1133 #define MIPS_HFLAG_M16_SHIFT 10 1134 /* 1135 * If translation is interrupted between the branch instruction and 1136 * the delay slot, record what type of branch it is so that we can 1137 * resume translation properly. It might be possible to reduce 1138 * this from three bits to two. 1139 */ 1140 #define MIPS_HFLAG_BMASK_BASE 0x803800 1141 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 1142 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 1143 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 1144 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 1145 /* Extra flags about the current pending branch. */ 1146 #define MIPS_HFLAG_BMASK_EXT 0x7C000 1147 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 1148 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 1149 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 1150 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 1151 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 1152 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 1153 /* MIPS DSP resources access. */ 1154 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ 1155 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ 1156 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ 1157 /* Extra flag about HWREna register. */ 1158 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 1159 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 1160 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 1161 #define MIPS_HFLAG_MSA 0x1000000 1162 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 1163 #define MIPS_HFLAG_ELPA 0x4000000 1164 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 1165 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ 1166 target_ulong btarget; /* Jump / branch target */ 1167 target_ulong bcond; /* Branch condition (if needed) */ 1168 1169 int SYNCI_Step; /* Address step size for SYNCI */ 1170 int CCRes; /* Cycle count resolution/divisor */ 1171 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 1172 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 1173 uint64_t insn_flags; /* Supported instruction set */ 1174 1175 /* Fields up to this point are cleared by a CPU reset */ 1176 struct {} end_reset_fields; 1177 1178 /* Fields from here on are preserved across CPU reset. */ 1179 CPUMIPSMVPContext *mvp; 1180 #if !defined(CONFIG_USER_ONLY) 1181 CPUMIPSTLBContext *tlb; 1182 qemu_irq irq[8]; 1183 MemoryRegion *itc_tag; /* ITC Configuration Tags */ 1184 1185 /* Loongson IOCSR memory */ 1186 struct { 1187 AddressSpace as; 1188 MemoryRegion mr; 1189 } iocsr; 1190 #endif 1191 1192 const mips_def_t *cpu_model; 1193 QEMUTimer *timer; /* Internal timer */ 1194 Clock *count_clock; /* CP0_Count clock */ 1195 target_ulong exception_base; /* ExceptionBase input to the core */ 1196 } CPUMIPSState; 1197 1198 /** 1199 * MIPSCPU: 1200 * @env: #CPUMIPSState 1201 * @clock: this CPU input clock (may be connected 1202 * to an output clock from another device). 1203 * 1204 * A MIPS CPU. 1205 */ 1206 struct ArchCPU { 1207 CPUState parent_obj; 1208 1209 CPUMIPSState env; 1210 1211 Clock *clock; 1212 Clock *count_div; /* Divider for CP0_Count clock */ 1213 1214 /* Properties */ 1215 bool is_big_endian; 1216 }; 1217 1218 /** 1219 * MIPSCPUClass: 1220 * @parent_realize: The parent class' realize handler. 1221 * @parent_phases: The parent class' reset phase handlers. 1222 * 1223 * A MIPS CPU model. 1224 */ 1225 struct MIPSCPUClass { 1226 CPUClass parent_class; 1227 1228 DeviceRealize parent_realize; 1229 ResettablePhases parent_phases; 1230 const struct mips_def_t *cpu_def; 1231 1232 /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ 1233 bool no_data_aborts; 1234 }; 1235 1236 void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 1237 uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 1238 1239 /* 1240 * MMU modes definitions. We carefully match the indices with our 1241 * hflags layout. 1242 */ 1243 #define MMU_KERNEL_IDX 0 1244 #define MMU_USER_IDX 2 1245 #define MMU_ERL_IDX 3 1246 1247 static inline int hflags_mmu_index(uint32_t hflags) 1248 { 1249 if (hflags & MIPS_HFLAG_ERL) { 1250 return MMU_ERL_IDX; 1251 } else { 1252 return hflags & MIPS_HFLAG_KSU; 1253 } 1254 } 1255 1256 static inline int mips_env_mmu_index(CPUMIPSState *env) 1257 { 1258 return hflags_mmu_index(env->hflags); 1259 } 1260 1261 /* Exceptions */ 1262 enum { 1263 EXCP_NONE = -1, 1264 EXCP_RESET = 0, 1265 EXCP_SRESET, 1266 EXCP_DSS, 1267 EXCP_DINT, 1268 EXCP_DDBL, 1269 EXCP_DDBS, 1270 EXCP_NMI, 1271 EXCP_MCHECK, 1272 EXCP_EXT_INTERRUPT, /* 8 */ 1273 EXCP_DFWATCH, 1274 EXCP_DIB, 1275 EXCP_IWATCH, 1276 EXCP_AdEL, 1277 EXCP_AdES, 1278 EXCP_TLBF, 1279 EXCP_IBE, 1280 EXCP_DBp, /* 16 */ 1281 EXCP_SYSCALL, 1282 EXCP_BREAK, 1283 EXCP_CpU, 1284 EXCP_RI, 1285 EXCP_OVERFLOW, 1286 EXCP_TRAP, 1287 EXCP_FPE, 1288 EXCP_DWATCH, /* 24 */ 1289 EXCP_LTLBL, 1290 EXCP_TLBL, 1291 EXCP_TLBS, 1292 EXCP_DBE, 1293 EXCP_THREAD, 1294 EXCP_MDMX, 1295 EXCP_C2E, 1296 EXCP_CACHE, /* 32 */ 1297 EXCP_DSPDIS, 1298 EXCP_MSADIS, 1299 EXCP_MSAFPE, 1300 EXCP_TLBXI, 1301 EXCP_TLBRI, 1302 EXCP_SEMIHOST, 1303 1304 EXCP_LAST = EXCP_SEMIHOST, 1305 }; 1306 1307 /* 1308 * This is an internally generated WAKE request line. 1309 * It is driven by the CPU itself. Raised when the MT 1310 * block wants to wake a VPE from an inactive state and 1311 * cleared when VPE goes from active to inactive. 1312 */ 1313 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 1314 1315 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 1316 1317 bool cpu_type_supports_cps_smp(const char *cpu_type); 1318 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); 1319 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); 1320 1321 /* Check presence of MIPS-3D ASE */ 1322 static inline bool ase_3d_available(const CPUMIPSState *env) 1323 { 1324 return env->active_fpu.fcr0 & (1 << FCR0_3D); 1325 } 1326 1327 /* Check presence of MSA implementation */ 1328 static inline bool ase_msa_available(CPUMIPSState *env) 1329 { 1330 return env->CP0_Config3 & (1 << CP0C3_MSAP); 1331 } 1332 1333 /* Check presence of Loongson CSR instructions */ 1334 static inline bool ase_lcsr_available(CPUMIPSState *env) 1335 { 1336 return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP); 1337 } 1338 1339 /* Check presence of multi-threading ASE implementation */ 1340 static inline bool ase_mt_available(CPUMIPSState *env) 1341 { 1342 return env->CP0_Config3 & (1 << CP0C3_MT); 1343 } 1344 1345 static inline bool cpu_type_is_64bit(const char *cpu_type) 1346 { 1347 return cpu_type_supports_isa(cpu_type, CPU_MIPS64); 1348 } 1349 1350 void cpu_set_exception_base(int vp_index, target_ulong address); 1351 1352 /* addr.c */ 1353 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); 1354 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); 1355 1356 uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr); 1357 uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); 1358 1359 #if !defined(CONFIG_USER_ONLY) 1360 1361 /* HW declaration specific to the MIPS target */ 1362 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 1363 void cpu_mips_irq_init_cpu(MIPSCPU *cpu); 1364 void cpu_mips_clock_init(MIPSCPU *cpu); 1365 1366 #endif /* !CONFIG_USER_ONLY */ 1367 1368 /* helper.c */ 1369 target_ulong exception_resume_pc(CPUMIPSState *env); 1370 1371 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, 1372 uint64_t *cs_base, uint32_t *flags) 1373 { 1374 *pc = env->active_tc.PC; 1375 *cs_base = 0; 1376 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 1377 MIPS_HFLAG_HWRENA_ULR); 1378 } 1379 1380 /** 1381 * mips_cpu_create_with_clock: 1382 * @typename: a MIPS CPU type. 1383 * @cpu_refclk: this cpu input clock (an output clock of another device) 1384 * @is_big_endian: whether this CPU is configured in big endianness 1385 * 1386 * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk, 1387 * then realizes the CPU. 1388 * 1389 * Returns: A #CPUState or %NULL if an error occurred. 1390 */ 1391 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, 1392 bool is_big_endian); 1393 1394 #endif /* MIPS_CPU_H */ 1395