1 #ifndef MIPS_CPU_H 2 #define MIPS_CPU_H 3 4 #include "cpu-qom.h" 5 #include "exec/cpu-defs.h" 6 #ifndef CONFIG_USER_ONLY 7 #include "exec/memory.h" 8 #endif 9 #include "fpu/softfloat-types.h" 10 #include "hw/clock.h" 11 #include "mips-defs.h" 12 13 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 14 15 /* MSA Context */ 16 #define MSA_WRLEN (128) 17 18 typedef union wr_t wr_t; 19 union wr_t { 20 int8_t b[MSA_WRLEN / 8]; 21 int16_t h[MSA_WRLEN / 16]; 22 int32_t w[MSA_WRLEN / 32]; 23 int64_t d[MSA_WRLEN / 64]; 24 }; 25 26 typedef union fpr_t fpr_t; 27 union fpr_t { 28 float64 fd; /* ieee double precision */ 29 float32 fs[2];/* ieee single precision */ 30 uint64_t d; /* binary double fixed-point */ 31 uint32_t w[2]; /* binary single fixed-point */ 32 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 33 wr_t wr; /* vector data */ 34 }; 35 /* 36 *define FP_ENDIAN_IDX to access the same location 37 * in the fpr_t union regardless of the host endianness 38 */ 39 #if HOST_BIG_ENDIAN 40 # define FP_ENDIAN_IDX 1 41 #else 42 # define FP_ENDIAN_IDX 0 43 #endif 44 45 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 46 struct CPUMIPSFPUContext { 47 /* Floating point registers */ 48 fpr_t fpr[32]; 49 float_status fp_status; 50 /* fpu implementation/revision register (fir) */ 51 uint32_t fcr0; 52 #define FCR0_FREP 29 53 #define FCR0_UFRP 28 54 #define FCR0_HAS2008 23 55 #define FCR0_F64 22 56 #define FCR0_L 21 57 #define FCR0_W 20 58 #define FCR0_3D 19 59 #define FCR0_PS 18 60 #define FCR0_D 17 61 #define FCR0_S 16 62 #define FCR0_PRID 8 63 #define FCR0_REV 0 64 /* fcsr */ 65 uint32_t fcr31_rw_bitmask; 66 uint32_t fcr31; 67 #define FCR31_FS 24 68 #define FCR31_ABS2008 19 69 #define FCR31_NAN2008 18 70 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ 71 ((num) ? (1 << ((num) + 24)) : \ 72 (1 << 23)); \ 73 } while (0) 74 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ 75 ~((num) ? (1 << ((num) + 24)) : \ 76 (1 << 23)); \ 77 } while (0) 78 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ 79 (((env).fcr31 >> 23) & 0x1)) 80 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 81 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 82 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 83 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ 84 ((v & 0x3f) << 12); \ 85 } while (0) 86 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ 87 ((v & 0x1f) << 7); \ 88 } while (0) 89 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ 90 ((v & 0x1f) << 2); \ 91 } while (0) 92 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) 93 #define FP_INEXACT 1 94 #define FP_UNDERFLOW 2 95 #define FP_OVERFLOW 4 96 #define FP_DIV0 8 97 #define FP_INVALID 16 98 #define FP_UNIMPLEMENTED 32 99 }; 100 101 #define TARGET_INSN_START_EXTRA_WORDS 2 102 103 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 104 struct CPUMIPSMVPContext { 105 int32_t CP0_MVPControl; 106 #define CP0MVPCo_CPA 3 107 #define CP0MVPCo_STLB 2 108 #define CP0MVPCo_VPC 1 109 #define CP0MVPCo_EVP 0 110 int32_t CP0_MVPConf0; 111 #define CP0MVPC0_M 31 112 #define CP0MVPC0_TLBS 29 113 #define CP0MVPC0_GS 28 114 #define CP0MVPC0_PCP 27 115 #define CP0MVPC0_PTLBE 16 116 #define CP0MVPC0_TCA 15 117 #define CP0MVPC0_PVPE 10 118 #define CP0MVPC0_PTC 0 119 int32_t CP0_MVPConf1; 120 #define CP0MVPC1_CIM 31 121 #define CP0MVPC1_CIF 30 122 #define CP0MVPC1_PCX 20 123 #define CP0MVPC1_PCP2 10 124 #define CP0MVPC1_PCP1 0 125 }; 126 127 typedef struct mips_def_t mips_def_t; 128 129 #define MIPS_SHADOW_SET_MAX 16 130 #define MIPS_TC_MAX 5 131 #define MIPS_FPU_MAX 1 132 #define MIPS_DSP_ACC 4 133 #define MIPS_KSCRATCH_NUM 6 134 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 135 136 137 /* 138 * Summary of CP0 registers 139 * ======================== 140 * 141 * 142 * Register 0 Register 1 Register 2 Register 3 143 * ---------- ---------- ---------- ---------- 144 * 145 * 0 Index Random EntryLo0 EntryLo1 146 * 1 MVPControl VPEControl TCStatus GlobalNumber 147 * 2 MVPConf0 VPEConf0 TCBind 148 * 3 MVPConf1 VPEConf1 TCRestart 149 * 4 VPControl YQMask TCHalt 150 * 5 VPESchedule TCContext 151 * 6 VPEScheFBack TCSchedule 152 * 7 VPEOpt TCScheFBack TCOpt 153 * 154 * 155 * Register 4 Register 5 Register 6 Register 7 156 * ---------- ---------- ---------- ---------- 157 * 158 * 0 Context PageMask Wired HWREna 159 * 1 ContextConfig PageGrain SRSConf0 160 * 2 UserLocal SegCtl0 SRSConf1 161 * 3 XContextConfig SegCtl1 SRSConf2 162 * 4 DebugContextID SegCtl2 SRSConf3 163 * 5 MemoryMapID PWBase SRSConf4 164 * 6 PWField PWCtl 165 * 7 PWSize 166 * 167 * 168 * Register 8 Register 9 Register 10 Register 11 169 * ---------- ---------- ----------- ----------- 170 * 171 * 0 BadVAddr Count EntryHi Compare 172 * 1 BadInstr 173 * 2 BadInstrP 174 * 3 BadInstrX 175 * 4 GuestCtl1 GuestCtl0Ext 176 * 5 GuestCtl2 177 * 6 SAARI GuestCtl3 178 * 7 SAAR 179 * 180 * 181 * Register 12 Register 13 Register 14 Register 15 182 * ----------- ----------- ----------- ----------- 183 * 184 * 0 Status Cause EPC PRId 185 * 1 IntCtl EBase 186 * 2 SRSCtl NestedEPC CDMMBase 187 * 3 SRSMap CMGCRBase 188 * 4 View_IPL View_RIPL BEVVA 189 * 5 SRSMap2 NestedExc 190 * 6 GuestCtl0 191 * 7 GTOffset 192 * 193 * 194 * Register 16 Register 17 Register 18 Register 19 195 * ----------- ----------- ----------- ----------- 196 * 197 * 0 Config LLAddr WatchLo0 WatchHi 198 * 1 Config1 MAAR WatchLo1 WatchHi 199 * 2 Config2 MAARI WatchLo2 WatchHi 200 * 3 Config3 WatchLo3 WatchHi 201 * 4 Config4 WatchLo4 WatchHi 202 * 5 Config5 WatchLo5 WatchHi 203 * 6 Config6 WatchLo6 WatchHi 204 * 7 Config7 WatchLo7 WatchHi 205 * 206 * 207 * Register 20 Register 21 Register 22 Register 23 208 * ----------- ----------- ----------- ----------- 209 * 210 * 0 XContext Debug 211 * 1 TraceControl 212 * 2 TraceControl2 213 * 3 UserTraceData1 214 * 4 TraceIBPC 215 * 5 TraceDBPC 216 * 6 Debug2 217 * 7 218 * 219 * 220 * Register 24 Register 25 Register 26 Register 27 221 * ----------- ----------- ----------- ----------- 222 * 223 * 0 DEPC PerfCnt ErrCtl CacheErr 224 * 1 PerfCnt 225 * 2 TraceControl3 PerfCnt 226 * 3 UserTraceData2 PerfCnt 227 * 4 PerfCnt 228 * 5 PerfCnt 229 * 6 PerfCnt 230 * 7 PerfCnt 231 * 232 * 233 * Register 28 Register 29 Register 30 Register 31 234 * ----------- ----------- ----------- ----------- 235 * 236 * 0 DataLo DataHi ErrorEPC DESAVE 237 * 1 TagLo TagHi 238 * 2 DataLo1 DataHi1 KScratch<n> 239 * 3 TagLo1 TagHi1 KScratch<n> 240 * 4 DataLo2 DataHi2 KScratch<n> 241 * 5 TagLo2 TagHi2 KScratch<n> 242 * 6 DataLo3 DataHi3 KScratch<n> 243 * 7 TagLo3 TagHi3 KScratch<n> 244 * 245 */ 246 #define CP0_REGISTER_00 0 247 #define CP0_REGISTER_01 1 248 #define CP0_REGISTER_02 2 249 #define CP0_REGISTER_03 3 250 #define CP0_REGISTER_04 4 251 #define CP0_REGISTER_05 5 252 #define CP0_REGISTER_06 6 253 #define CP0_REGISTER_07 7 254 #define CP0_REGISTER_08 8 255 #define CP0_REGISTER_09 9 256 #define CP0_REGISTER_10 10 257 #define CP0_REGISTER_11 11 258 #define CP0_REGISTER_12 12 259 #define CP0_REGISTER_13 13 260 #define CP0_REGISTER_14 14 261 #define CP0_REGISTER_15 15 262 #define CP0_REGISTER_16 16 263 #define CP0_REGISTER_17 17 264 #define CP0_REGISTER_18 18 265 #define CP0_REGISTER_19 19 266 #define CP0_REGISTER_20 20 267 #define CP0_REGISTER_21 21 268 #define CP0_REGISTER_22 22 269 #define CP0_REGISTER_23 23 270 #define CP0_REGISTER_24 24 271 #define CP0_REGISTER_25 25 272 #define CP0_REGISTER_26 26 273 #define CP0_REGISTER_27 27 274 #define CP0_REGISTER_28 28 275 #define CP0_REGISTER_29 29 276 #define CP0_REGISTER_30 30 277 #define CP0_REGISTER_31 31 278 279 280 /* CP0 Register 00 */ 281 #define CP0_REG00__INDEX 0 282 #define CP0_REG00__MVPCONTROL 1 283 #define CP0_REG00__MVPCONF0 2 284 #define CP0_REG00__MVPCONF1 3 285 #define CP0_REG00__VPCONTROL 4 286 /* CP0 Register 01 */ 287 #define CP0_REG01__RANDOM 0 288 #define CP0_REG01__VPECONTROL 1 289 #define CP0_REG01__VPECONF0 2 290 #define CP0_REG01__VPECONF1 3 291 #define CP0_REG01__YQMASK 4 292 #define CP0_REG01__VPESCHEDULE 5 293 #define CP0_REG01__VPESCHEFBACK 6 294 #define CP0_REG01__VPEOPT 7 295 /* CP0 Register 02 */ 296 #define CP0_REG02__ENTRYLO0 0 297 #define CP0_REG02__TCSTATUS 1 298 #define CP0_REG02__TCBIND 2 299 #define CP0_REG02__TCRESTART 3 300 #define CP0_REG02__TCHALT 4 301 #define CP0_REG02__TCCONTEXT 5 302 #define CP0_REG02__TCSCHEDULE 6 303 #define CP0_REG02__TCSCHEFBACK 7 304 /* CP0 Register 03 */ 305 #define CP0_REG03__ENTRYLO1 0 306 #define CP0_REG03__GLOBALNUM 1 307 #define CP0_REG03__TCOPT 7 308 /* CP0 Register 04 */ 309 #define CP0_REG04__CONTEXT 0 310 #define CP0_REG04__CONTEXTCONFIG 1 311 #define CP0_REG04__USERLOCAL 2 312 #define CP0_REG04__XCONTEXTCONFIG 3 313 #define CP0_REG04__DBGCONTEXTID 4 314 #define CP0_REG04__MMID 5 315 /* CP0 Register 05 */ 316 #define CP0_REG05__PAGEMASK 0 317 #define CP0_REG05__PAGEGRAIN 1 318 #define CP0_REG05__SEGCTL0 2 319 #define CP0_REG05__SEGCTL1 3 320 #define CP0_REG05__SEGCTL2 4 321 #define CP0_REG05__PWBASE 5 322 #define CP0_REG05__PWFIELD 6 323 #define CP0_REG05__PWSIZE 7 324 /* CP0 Register 06 */ 325 #define CP0_REG06__WIRED 0 326 #define CP0_REG06__SRSCONF0 1 327 #define CP0_REG06__SRSCONF1 2 328 #define CP0_REG06__SRSCONF2 3 329 #define CP0_REG06__SRSCONF3 4 330 #define CP0_REG06__SRSCONF4 5 331 #define CP0_REG06__PWCTL 6 332 /* CP0 Register 07 */ 333 #define CP0_REG07__HWRENA 0 334 /* CP0 Register 08 */ 335 #define CP0_REG08__BADVADDR 0 336 #define CP0_REG08__BADINSTR 1 337 #define CP0_REG08__BADINSTRP 2 338 #define CP0_REG08__BADINSTRX 3 339 /* CP0 Register 09 */ 340 #define CP0_REG09__COUNT 0 341 #define CP0_REG09__SAARI 6 342 #define CP0_REG09__SAAR 7 343 /* CP0 Register 10 */ 344 #define CP0_REG10__ENTRYHI 0 345 #define CP0_REG10__GUESTCTL1 4 346 #define CP0_REG10__GUESTCTL2 5 347 #define CP0_REG10__GUESTCTL3 6 348 /* CP0 Register 11 */ 349 #define CP0_REG11__COMPARE 0 350 #define CP0_REG11__GUESTCTL0EXT 4 351 /* CP0 Register 12 */ 352 #define CP0_REG12__STATUS 0 353 #define CP0_REG12__INTCTL 1 354 #define CP0_REG12__SRSCTL 2 355 #define CP0_REG12__SRSMAP 3 356 #define CP0_REG12__VIEW_IPL 4 357 #define CP0_REG12__SRSMAP2 5 358 #define CP0_REG12__GUESTCTL0 6 359 #define CP0_REG12__GTOFFSET 7 360 /* CP0 Register 13 */ 361 #define CP0_REG13__CAUSE 0 362 #define CP0_REG13__VIEW_RIPL 4 363 #define CP0_REG13__NESTEDEXC 5 364 /* CP0 Register 14 */ 365 #define CP0_REG14__EPC 0 366 #define CP0_REG14__NESTEDEPC 2 367 /* CP0 Register 15 */ 368 #define CP0_REG15__PRID 0 369 #define CP0_REG15__EBASE 1 370 #define CP0_REG15__CDMMBASE 2 371 #define CP0_REG15__CMGCRBASE 3 372 #define CP0_REG15__BEVVA 4 373 /* CP0 Register 16 */ 374 #define CP0_REG16__CONFIG 0 375 #define CP0_REG16__CONFIG1 1 376 #define CP0_REG16__CONFIG2 2 377 #define CP0_REG16__CONFIG3 3 378 #define CP0_REG16__CONFIG4 4 379 #define CP0_REG16__CONFIG5 5 380 #define CP0_REG16__CONFIG6 6 381 #define CP0_REG16__CONFIG7 7 382 /* CP0 Register 17 */ 383 #define CP0_REG17__LLADDR 0 384 #define CP0_REG17__MAAR 1 385 #define CP0_REG17__MAARI 2 386 /* CP0 Register 18 */ 387 #define CP0_REG18__WATCHLO0 0 388 #define CP0_REG18__WATCHLO1 1 389 #define CP0_REG18__WATCHLO2 2 390 #define CP0_REG18__WATCHLO3 3 391 #define CP0_REG18__WATCHLO4 4 392 #define CP0_REG18__WATCHLO5 5 393 #define CP0_REG18__WATCHLO6 6 394 #define CP0_REG18__WATCHLO7 7 395 /* CP0 Register 19 */ 396 #define CP0_REG19__WATCHHI0 0 397 #define CP0_REG19__WATCHHI1 1 398 #define CP0_REG19__WATCHHI2 2 399 #define CP0_REG19__WATCHHI3 3 400 #define CP0_REG19__WATCHHI4 4 401 #define CP0_REG19__WATCHHI5 5 402 #define CP0_REG19__WATCHHI6 6 403 #define CP0_REG19__WATCHHI7 7 404 /* CP0 Register 20 */ 405 #define CP0_REG20__XCONTEXT 0 406 /* CP0 Register 21 */ 407 /* CP0 Register 22 */ 408 /* CP0 Register 23 */ 409 #define CP0_REG23__DEBUG 0 410 #define CP0_REG23__TRACECONTROL 1 411 #define CP0_REG23__TRACECONTROL2 2 412 #define CP0_REG23__USERTRACEDATA1 3 413 #define CP0_REG23__TRACEIBPC 4 414 #define CP0_REG23__TRACEDBPC 5 415 #define CP0_REG23__DEBUG2 6 416 /* CP0 Register 24 */ 417 #define CP0_REG24__DEPC 0 418 /* CP0 Register 25 */ 419 #define CP0_REG25__PERFCTL0 0 420 #define CP0_REG25__PERFCNT0 1 421 #define CP0_REG25__PERFCTL1 2 422 #define CP0_REG25__PERFCNT1 3 423 #define CP0_REG25__PERFCTL2 4 424 #define CP0_REG25__PERFCNT2 5 425 #define CP0_REG25__PERFCTL3 6 426 #define CP0_REG25__PERFCNT3 7 427 /* CP0 Register 26 */ 428 #define CP0_REG26__ERRCTL 0 429 /* CP0 Register 27 */ 430 #define CP0_REG27__CACHERR 0 431 /* CP0 Register 28 */ 432 #define CP0_REG28__TAGLO 0 433 #define CP0_REG28__DATALO 1 434 #define CP0_REG28__TAGLO1 2 435 #define CP0_REG28__DATALO1 3 436 #define CP0_REG28__TAGLO2 4 437 #define CP0_REG28__DATALO2 5 438 #define CP0_REG28__TAGLO3 6 439 #define CP0_REG28__DATALO3 7 440 /* CP0 Register 29 */ 441 #define CP0_REG29__TAGHI 0 442 #define CP0_REG29__DATAHI 1 443 #define CP0_REG29__TAGHI1 2 444 #define CP0_REG29__DATAHI1 3 445 #define CP0_REG29__TAGHI2 4 446 #define CP0_REG29__DATAHI2 5 447 #define CP0_REG29__TAGHI3 6 448 #define CP0_REG29__DATAHI3 7 449 /* CP0 Register 30 */ 450 #define CP0_REG30__ERROREPC 0 451 /* CP0 Register 31 */ 452 #define CP0_REG31__DESAVE 0 453 #define CP0_REG31__KSCRATCH1 2 454 #define CP0_REG31__KSCRATCH2 3 455 #define CP0_REG31__KSCRATCH3 4 456 #define CP0_REG31__KSCRATCH4 5 457 #define CP0_REG31__KSCRATCH5 6 458 #define CP0_REG31__KSCRATCH6 7 459 460 461 typedef struct TCState TCState; 462 struct TCState { 463 target_ulong gpr[32]; 464 #if defined(TARGET_MIPS64) 465 /* 466 * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[]) 467 * and the upper halves in gpr_hi[]. 468 */ 469 uint64_t gpr_hi[32]; 470 #endif /* TARGET_MIPS64 */ 471 target_ulong PC; 472 target_ulong HI[MIPS_DSP_ACC]; 473 target_ulong LO[MIPS_DSP_ACC]; 474 target_ulong ACX[MIPS_DSP_ACC]; 475 target_ulong DSPControl; 476 int32_t CP0_TCStatus; 477 #define CP0TCSt_TCU3 31 478 #define CP0TCSt_TCU2 30 479 #define CP0TCSt_TCU1 29 480 #define CP0TCSt_TCU0 28 481 #define CP0TCSt_TMX 27 482 #define CP0TCSt_RNST 23 483 #define CP0TCSt_TDS 21 484 #define CP0TCSt_DT 20 485 #define CP0TCSt_DA 15 486 #define CP0TCSt_A 13 487 #define CP0TCSt_TKSU 11 488 #define CP0TCSt_IXMT 10 489 #define CP0TCSt_TASID 0 490 int32_t CP0_TCBind; 491 #define CP0TCBd_CurTC 21 492 #define CP0TCBd_TBE 17 493 #define CP0TCBd_CurVPE 0 494 target_ulong CP0_TCHalt; 495 target_ulong CP0_TCContext; 496 target_ulong CP0_TCSchedule; 497 target_ulong CP0_TCScheFBack; 498 int32_t CP0_Debug_tcstatus; 499 target_ulong CP0_UserLocal; 500 501 int32_t msacsr; 502 503 #define MSACSR_FS 24 504 #define MSACSR_FS_MASK (1 << MSACSR_FS) 505 #define MSACSR_NX 18 506 #define MSACSR_NX_MASK (1 << MSACSR_NX) 507 #define MSACSR_CEF 2 508 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 509 #define MSACSR_RM 0 510 #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 511 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 512 MSACSR_FS_MASK) 513 514 float_status msa_fp_status; 515 516 #define NUMBER_OF_MXU_REGISTERS 16 517 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; 518 target_ulong mxu_cr; 519 #define MXU_CR_LC 31 520 #define MXU_CR_RC 30 521 #define MXU_CR_BIAS 2 522 #define MXU_CR_RD_EN 1 523 #define MXU_CR_MXU_EN 0 524 525 }; 526 527 struct MIPSITUState; 528 typedef struct CPUArchState { 529 TCState active_tc; 530 CPUMIPSFPUContext active_fpu; 531 532 uint32_t current_tc; 533 534 uint32_t SEGBITS; 535 uint32_t PABITS; 536 #if defined(TARGET_MIPS64) 537 # define PABITS_BASE 36 538 #else 539 # define PABITS_BASE 32 540 #endif 541 target_ulong SEGMask; 542 uint64_t PAMask; 543 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 544 545 int32_t msair; 546 #define MSAIR_ProcID 8 547 #define MSAIR_Rev 0 548 549 /* 550 * CP0 Register 0 551 */ 552 int32_t CP0_Index; 553 /* CP0_MVP* are per MVP registers. */ 554 int32_t CP0_VPControl; 555 #define CP0VPCtl_DIS 0 556 /* 557 * CP0 Register 1 558 */ 559 int32_t CP0_Random; 560 int32_t CP0_VPEControl; 561 #define CP0VPECo_YSI 21 562 #define CP0VPECo_GSI 20 563 #define CP0VPECo_EXCPT 16 564 #define CP0VPECo_TE 15 565 #define CP0VPECo_TargTC 0 566 int32_t CP0_VPEConf0; 567 #define CP0VPEC0_M 31 568 #define CP0VPEC0_XTC 21 569 #define CP0VPEC0_TCS 19 570 #define CP0VPEC0_SCS 18 571 #define CP0VPEC0_DSC 17 572 #define CP0VPEC0_ICS 16 573 #define CP0VPEC0_MVP 1 574 #define CP0VPEC0_VPA 0 575 int32_t CP0_VPEConf1; 576 #define CP0VPEC1_NCX 20 577 #define CP0VPEC1_NCP2 10 578 #define CP0VPEC1_NCP1 0 579 target_ulong CP0_YQMask; 580 target_ulong CP0_VPESchedule; 581 target_ulong CP0_VPEScheFBack; 582 int32_t CP0_VPEOpt; 583 #define CP0VPEOpt_IWX7 15 584 #define CP0VPEOpt_IWX6 14 585 #define CP0VPEOpt_IWX5 13 586 #define CP0VPEOpt_IWX4 12 587 #define CP0VPEOpt_IWX3 11 588 #define CP0VPEOpt_IWX2 10 589 #define CP0VPEOpt_IWX1 9 590 #define CP0VPEOpt_IWX0 8 591 #define CP0VPEOpt_DWX7 7 592 #define CP0VPEOpt_DWX6 6 593 #define CP0VPEOpt_DWX5 5 594 #define CP0VPEOpt_DWX4 4 595 #define CP0VPEOpt_DWX3 3 596 #define CP0VPEOpt_DWX2 2 597 #define CP0VPEOpt_DWX1 1 598 #define CP0VPEOpt_DWX0 0 599 /* 600 * CP0 Register 2 601 */ 602 uint64_t CP0_EntryLo0; 603 /* 604 * CP0 Register 3 605 */ 606 uint64_t CP0_EntryLo1; 607 #if defined(TARGET_MIPS64) 608 # define CP0EnLo_RI 63 609 # define CP0EnLo_XI 62 610 #else 611 # define CP0EnLo_RI 31 612 # define CP0EnLo_XI 30 613 #endif 614 int32_t CP0_GlobalNumber; 615 #define CP0GN_VPId 0 616 /* 617 * CP0 Register 4 618 */ 619 target_ulong CP0_Context; 620 int32_t CP0_MemoryMapID; 621 /* 622 * CP0 Register 5 623 */ 624 int32_t CP0_PageMask; 625 #define CP0PM_MASK 13 626 int32_t CP0_PageGrain_rw_bitmask; 627 int32_t CP0_PageGrain; 628 #define CP0PG_RIE 31 629 #define CP0PG_XIE 30 630 #define CP0PG_ELPA 29 631 #define CP0PG_IEC 27 632 target_ulong CP0_SegCtl0; 633 target_ulong CP0_SegCtl1; 634 target_ulong CP0_SegCtl2; 635 #define CP0SC_PA 9 636 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) 637 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) 638 #define CP0SC_AM 4 639 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) 640 #define CP0SC_AM_UK 0ULL 641 #define CP0SC_AM_MK 1ULL 642 #define CP0SC_AM_MSK 2ULL 643 #define CP0SC_AM_MUSK 3ULL 644 #define CP0SC_AM_MUSUK 4ULL 645 #define CP0SC_AM_USK 5ULL 646 #define CP0SC_AM_UUSK 7ULL 647 #define CP0SC_EU 3 648 #define CP0SC_EU_MASK (1ULL << CP0SC_EU) 649 #define CP0SC_C 0 650 #define CP0SC_C_MASK (0x7ULL << CP0SC_C) 651 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 652 CP0SC_PA_MASK) 653 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 654 CP0SC_PA_1GMASK) 655 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) 656 #define CP0SC1_XAM 59 657 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) 658 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) 659 #define CP0SC2_XR 56 660 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) 661 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) 662 target_ulong CP0_PWBase; 663 target_ulong CP0_PWField; 664 #if defined(TARGET_MIPS64) 665 #define CP0PF_BDI 32 /* 37..32 */ 666 #define CP0PF_GDI 24 /* 29..24 */ 667 #define CP0PF_UDI 18 /* 23..18 */ 668 #define CP0PF_MDI 12 /* 17..12 */ 669 #define CP0PF_PTI 6 /* 11..6 */ 670 #define CP0PF_PTEI 0 /* 5..0 */ 671 #else 672 #define CP0PF_GDW 24 /* 29..24 */ 673 #define CP0PF_UDW 18 /* 23..18 */ 674 #define CP0PF_MDW 12 /* 17..12 */ 675 #define CP0PF_PTW 6 /* 11..6 */ 676 #define CP0PF_PTEW 0 /* 5..0 */ 677 #endif 678 target_ulong CP0_PWSize; 679 #if defined(TARGET_MIPS64) 680 #define CP0PS_BDW 32 /* 37..32 */ 681 #endif 682 #define CP0PS_PS 30 683 #define CP0PS_GDW 24 /* 29..24 */ 684 #define CP0PS_UDW 18 /* 23..18 */ 685 #define CP0PS_MDW 12 /* 17..12 */ 686 #define CP0PS_PTW 6 /* 11..6 */ 687 #define CP0PS_PTEW 0 /* 5..0 */ 688 /* 689 * CP0 Register 6 690 */ 691 int32_t CP0_Wired; 692 int32_t CP0_PWCtl; 693 #define CP0PC_PWEN 31 694 #if defined(TARGET_MIPS64) 695 #define CP0PC_PWDIREXT 30 696 #define CP0PC_XK 28 697 #define CP0PC_XS 27 698 #define CP0PC_XU 26 699 #endif 700 #define CP0PC_DPH 7 701 #define CP0PC_HUGEPG 6 702 #define CP0PC_PSN 0 /* 5..0 */ 703 int32_t CP0_SRSConf0_rw_bitmask; 704 int32_t CP0_SRSConf0; 705 #define CP0SRSC0_M 31 706 #define CP0SRSC0_SRS3 20 707 #define CP0SRSC0_SRS2 10 708 #define CP0SRSC0_SRS1 0 709 int32_t CP0_SRSConf1_rw_bitmask; 710 int32_t CP0_SRSConf1; 711 #define CP0SRSC1_M 31 712 #define CP0SRSC1_SRS6 20 713 #define CP0SRSC1_SRS5 10 714 #define CP0SRSC1_SRS4 0 715 int32_t CP0_SRSConf2_rw_bitmask; 716 int32_t CP0_SRSConf2; 717 #define CP0SRSC2_M 31 718 #define CP0SRSC2_SRS9 20 719 #define CP0SRSC2_SRS8 10 720 #define CP0SRSC2_SRS7 0 721 int32_t CP0_SRSConf3_rw_bitmask; 722 int32_t CP0_SRSConf3; 723 #define CP0SRSC3_M 31 724 #define CP0SRSC3_SRS12 20 725 #define CP0SRSC3_SRS11 10 726 #define CP0SRSC3_SRS10 0 727 int32_t CP0_SRSConf4_rw_bitmask; 728 int32_t CP0_SRSConf4; 729 #define CP0SRSC4_SRS15 20 730 #define CP0SRSC4_SRS14 10 731 #define CP0SRSC4_SRS13 0 732 /* 733 * CP0 Register 7 734 */ 735 int32_t CP0_HWREna; 736 /* 737 * CP0 Register 8 738 */ 739 target_ulong CP0_BadVAddr; 740 uint32_t CP0_BadInstr; 741 uint32_t CP0_BadInstrP; 742 uint32_t CP0_BadInstrX; 743 /* 744 * CP0 Register 9 745 */ 746 int32_t CP0_Count; 747 #define CP0SAARI_TARGET 0 /* 5..0 */ 748 #define CP0SAAR_BASE 12 /* 43..12 */ 749 #define CP0SAAR_SIZE 1 /* 5..1 */ 750 #define CP0SAAR_EN 0 751 /* 752 * CP0 Register 10 753 */ 754 target_ulong CP0_EntryHi; 755 #define CP0EnHi_EHINV 10 756 target_ulong CP0_EntryHi_ASID_mask; 757 /* 758 * CP0 Register 11 759 */ 760 int32_t CP0_Compare; 761 /* 762 * CP0 Register 12 763 */ 764 int32_t CP0_Status; 765 #define CP0St_CU3 31 766 #define CP0St_CU2 30 767 #define CP0St_CU1 29 768 #define CP0St_CU0 28 769 #define CP0St_RP 27 770 #define CP0St_FR 26 771 #define CP0St_RE 25 772 #define CP0St_MX 24 773 #define CP0St_PX 23 774 #define CP0St_BEV 22 775 #define CP0St_TS 21 776 #define CP0St_SR 20 777 #define CP0St_NMI 19 778 #define CP0St_IM 8 779 #define CP0St_KX 7 780 #define CP0St_SX 6 781 #define CP0St_UX 5 782 #define CP0St_KSU 3 783 #define CP0St_ERL 2 784 #define CP0St_EXL 1 785 #define CP0St_IE 0 786 int32_t CP0_IntCtl; 787 #define CP0IntCtl_IPTI 29 788 #define CP0IntCtl_IPPCI 26 789 #define CP0IntCtl_VS 5 790 int32_t CP0_SRSCtl; 791 #define CP0SRSCtl_HSS 26 792 #define CP0SRSCtl_EICSS 18 793 #define CP0SRSCtl_ESS 12 794 #define CP0SRSCtl_PSS 6 795 #define CP0SRSCtl_CSS 0 796 int32_t CP0_SRSMap; 797 #define CP0SRSMap_SSV7 28 798 #define CP0SRSMap_SSV6 24 799 #define CP0SRSMap_SSV5 20 800 #define CP0SRSMap_SSV4 16 801 #define CP0SRSMap_SSV3 12 802 #define CP0SRSMap_SSV2 8 803 #define CP0SRSMap_SSV1 4 804 #define CP0SRSMap_SSV0 0 805 /* 806 * CP0 Register 13 807 */ 808 int32_t CP0_Cause; 809 #define CP0Ca_BD 31 810 #define CP0Ca_TI 30 811 #define CP0Ca_CE 28 812 #define CP0Ca_DC 27 813 #define CP0Ca_PCI 26 814 #define CP0Ca_IV 23 815 #define CP0Ca_WP 22 816 #define CP0Ca_IP 8 817 #define CP0Ca_IP_mask 0x0000FF00 818 #define CP0Ca_EC 2 819 /* 820 * CP0 Register 14 821 */ 822 target_ulong CP0_EPC; 823 /* 824 * CP0 Register 15 825 */ 826 int32_t CP0_PRid; 827 target_ulong CP0_EBase; 828 target_ulong CP0_EBaseWG_rw_bitmask; 829 #define CP0EBase_WG 11 830 target_ulong CP0_CMGCRBase; 831 /* 832 * CP0 Register 16 (after Release 1) 833 */ 834 int32_t CP0_Config0; 835 #define CP0C0_M 31 836 #define CP0C0_K23 28 /* 30..28 */ 837 #define CP0C0_KU 25 /* 27..25 */ 838 #define CP0C0_MDU 20 839 #define CP0C0_MM 18 840 #define CP0C0_BM 16 841 #define CP0C0_Impl 16 /* 24..16 */ 842 #define CP0C0_BE 15 843 #define CP0C0_AT 13 /* 14..13 */ 844 #define CP0C0_AR 10 /* 12..10 */ 845 #define CP0C0_MT 7 /* 9..7 */ 846 #define CP0C0_VI 3 847 #define CP0C0_K0 0 /* 2..0 */ 848 #define CP0C0_AR_LENGTH 3 849 /* 850 * CP0 Register 16 (before Release 1) 851 */ 852 #define CP0C0_Impl 16 /* 24..16 */ 853 #define CP0C0_IC 9 /* 11..9 */ 854 #define CP0C0_DC 6 /* 8..6 */ 855 #define CP0C0_IB 5 856 #define CP0C0_DB 4 857 int32_t CP0_Config1; 858 #define CP0C1_M 31 859 #define CP0C1_MMU 25 /* 30..25 */ 860 #define CP0C1_IS 22 /* 24..22 */ 861 #define CP0C1_IL 19 /* 21..19 */ 862 #define CP0C1_IA 16 /* 18..16 */ 863 #define CP0C1_DS 13 /* 15..13 */ 864 #define CP0C1_DL 10 /* 12..10 */ 865 #define CP0C1_DA 7 /* 9..7 */ 866 #define CP0C1_C2 6 867 #define CP0C1_MD 5 868 #define CP0C1_PC 4 869 #define CP0C1_WR 3 870 #define CP0C1_CA 2 871 #define CP0C1_EP 1 872 #define CP0C1_FP 0 873 int32_t CP0_Config2; 874 #define CP0C2_M 31 875 #define CP0C2_TU 28 /* 30..28 */ 876 #define CP0C2_TS 24 /* 27..24 */ 877 #define CP0C2_TL 20 /* 23..20 */ 878 #define CP0C2_TA 16 /* 19..16 */ 879 #define CP0C2_SU 12 /* 15..12 */ 880 #define CP0C2_SS 8 /* 11..8 */ 881 #define CP0C2_SL 4 /* 7..4 */ 882 #define CP0C2_SA 0 /* 3..0 */ 883 int32_t CP0_Config3; 884 #define CP0C3_M 31 885 #define CP0C3_BPG 30 886 #define CP0C3_CMGCR 29 887 #define CP0C3_MSAP 28 888 #define CP0C3_BP 27 889 #define CP0C3_BI 26 890 #define CP0C3_SC 25 891 #define CP0C3_PW 24 892 #define CP0C3_VZ 23 893 #define CP0C3_IPLV 21 /* 22..21 */ 894 #define CP0C3_MMAR 18 /* 20..18 */ 895 #define CP0C3_MCU 17 896 #define CP0C3_ISA_ON_EXC 16 897 #define CP0C3_ISA 14 /* 15..14 */ 898 #define CP0C3_ULRI 13 899 #define CP0C3_RXI 12 900 #define CP0C3_DSP2P 11 901 #define CP0C3_DSPP 10 902 #define CP0C3_CTXTC 9 903 #define CP0C3_ITL 8 904 #define CP0C3_LPA 7 905 #define CP0C3_VEIC 6 906 #define CP0C3_VInt 5 907 #define CP0C3_SP 4 908 #define CP0C3_CDMM 3 909 #define CP0C3_MT 2 910 #define CP0C3_SM 1 911 #define CP0C3_TL 0 912 int32_t CP0_Config4; 913 int32_t CP0_Config4_rw_bitmask; 914 #define CP0C4_M 31 915 #define CP0C4_IE 29 /* 30..29 */ 916 #define CP0C4_AE 28 917 #define CP0C4_VTLBSizeExt 24 /* 27..24 */ 918 #define CP0C4_KScrExist 16 919 #define CP0C4_MMUExtDef 14 920 #define CP0C4_FTLBPageSize 8 /* 12..8 */ 921 /* bit layout if MMUExtDef=1 */ 922 #define CP0C4_MMUSizeExt 0 /* 7..0 */ 923 /* bit layout if MMUExtDef=2 */ 924 #define CP0C4_FTLBWays 4 /* 7..4 */ 925 #define CP0C4_FTLBSets 0 /* 3..0 */ 926 int32_t CP0_Config5; 927 int32_t CP0_Config5_rw_bitmask; 928 #define CP0C5_M 31 929 #define CP0C5_K 30 930 #define CP0C5_CV 29 931 #define CP0C5_EVA 28 932 #define CP0C5_MSAEn 27 933 #define CP0C5_PMJ 23 /* 25..23 */ 934 #define CP0C5_WR2 22 935 #define CP0C5_NMS 21 936 #define CP0C5_ULS 20 937 #define CP0C5_XPA 19 938 #define CP0C5_CRCP 18 939 #define CP0C5_MI 17 940 #define CP0C5_GI 15 /* 16..15 */ 941 #define CP0C5_CA2 14 942 #define CP0C5_XNP 13 943 #define CP0C5_DEC 11 944 #define CP0C5_L2C 10 945 #define CP0C5_UFE 9 946 #define CP0C5_FRE 8 947 #define CP0C5_VP 7 948 #define CP0C5_SBRI 6 949 #define CP0C5_MVH 5 950 #define CP0C5_LLB 4 951 #define CP0C5_MRP 3 952 #define CP0C5_UFR 2 953 #define CP0C5_NFExists 0 954 int32_t CP0_Config6; 955 int32_t CP0_Config6_rw_bitmask; 956 #define CP0C6_BPPASS 31 957 #define CP0C6_KPOS 24 958 #define CP0C6_KE 23 959 #define CP0C6_VTLBONLY 22 960 #define CP0C6_LASX 21 961 #define CP0C6_SSEN 20 962 #define CP0C6_DISDRTIME 19 963 #define CP0C6_PIXNUEN 18 964 #define CP0C6_SCRAND 17 965 #define CP0C6_LLEXCEN 16 966 #define CP0C6_DISVC 15 967 #define CP0C6_VCLRU 14 968 #define CP0C6_DCLRU 13 969 #define CP0C6_PIXUEN 12 970 #define CP0C6_DISBLKLYEN 11 971 #define CP0C6_UMEMUALEN 10 972 #define CP0C6_SFBEN 8 973 #define CP0C6_FLTINT 7 974 #define CP0C6_VLTINT 6 975 #define CP0C6_DISBTB 5 976 #define CP0C6_STPREFCTL 2 977 #define CP0C6_INSTPREF 1 978 #define CP0C6_DATAPREF 0 979 int32_t CP0_Config7; 980 int64_t CP0_Config7_rw_bitmask; 981 #define CP0C7_WII 31 982 #define CP0C7_NAPCGEN 2 983 #define CP0C7_UNIMUEN 1 984 #define CP0C7_VFPUCGEN 0 985 uint64_t CP0_LLAddr; 986 uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 987 int32_t CP0_MAARI; 988 /* XXX: Maybe make LLAddr per-TC? */ 989 /* 990 * CP0 Register 17 991 */ 992 target_ulong lladdr; /* LL virtual address compared against SC */ 993 target_ulong llval; 994 uint64_t llval_wp; 995 uint32_t llnewval_wp; 996 uint64_t CP0_LLAddr_rw_bitmask; 997 int CP0_LLAddr_shift; 998 /* 999 * CP0 Register 18 1000 */ 1001 target_ulong CP0_WatchLo[8]; 1002 /* 1003 * CP0 Register 19 1004 */ 1005 uint64_t CP0_WatchHi[8]; 1006 #define CP0WH_ASID 16 1007 #define CP0WH_M 31 1008 /* 1009 * CP0 Register 20 1010 */ 1011 target_ulong CP0_XContext; 1012 int32_t CP0_Framemask; 1013 /* 1014 * CP0 Register 23 1015 */ 1016 int32_t CP0_Debug; 1017 #define CP0DB_DBD 31 1018 #define CP0DB_DM 30 1019 #define CP0DB_LSNM 28 1020 #define CP0DB_Doze 27 1021 #define CP0DB_Halt 26 1022 #define CP0DB_CNT 25 1023 #define CP0DB_IBEP 24 1024 #define CP0DB_DBEP 21 1025 #define CP0DB_IEXI 20 1026 #define CP0DB_VER 15 1027 #define CP0DB_DEC 10 1028 #define CP0DB_SSt 8 1029 #define CP0DB_DINT 5 1030 #define CP0DB_DIB 4 1031 #define CP0DB_DDBS 3 1032 #define CP0DB_DDBL 2 1033 #define CP0DB_DBp 1 1034 #define CP0DB_DSS 0 1035 /* 1036 * CP0 Register 24 1037 */ 1038 target_ulong CP0_DEPC; 1039 /* 1040 * CP0 Register 25 1041 */ 1042 int32_t CP0_Performance0; 1043 /* 1044 * CP0 Register 26 1045 */ 1046 int32_t CP0_ErrCtl; 1047 #define CP0EC_WST 29 1048 #define CP0EC_SPR 28 1049 #define CP0EC_ITC 26 1050 /* 1051 * CP0 Register 28 1052 */ 1053 uint64_t CP0_TagLo; 1054 int32_t CP0_DataLo; 1055 /* 1056 * CP0 Register 29 1057 */ 1058 int32_t CP0_TagHi; 1059 int32_t CP0_DataHi; 1060 /* 1061 * CP0 Register 30 1062 */ 1063 target_ulong CP0_ErrorEPC; 1064 /* 1065 * CP0 Register 31 1066 */ 1067 int32_t CP0_DESAVE; 1068 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 1069 /* 1070 * Loongson CSR CPUCFG registers 1071 */ 1072 uint32_t lcsr_cpucfg1; 1073 #define CPUCFG1_FP 0 1074 #define CPUCFG1_FPREV 1 1075 #define CPUCFG1_MMI 4 1076 #define CPUCFG1_MSA1 5 1077 #define CPUCFG1_MSA2 6 1078 #define CPUCFG1_LSLDR0 16 1079 #define CPUCFG1_LSPERF 17 1080 #define CPUCFG1_LSPERFX 18 1081 #define CPUCFG1_LSSYNCI 19 1082 #define CPUCFG1_LLEXC 20 1083 #define CPUCFG1_SCRAND 21 1084 #define CPUCFG1_MUALP 25 1085 #define CPUCFG1_KMUALEN 26 1086 #define CPUCFG1_ITLBT 27 1087 #define CPUCFG1_SFBP 29 1088 #define CPUCFG1_CDMAP 30 1089 uint32_t lcsr_cpucfg2; 1090 #define CPUCFG2_LEXT1 0 1091 #define CPUCFG2_LEXT2 1 1092 #define CPUCFG2_LEXT3 2 1093 #define CPUCFG2_LSPW 3 1094 #define CPUCFG2_LCSRP 27 1095 #define CPUCFG2_LDISBLIKELY 28 1096 1097 /* We waste some space so we can handle shadow registers like TCs. */ 1098 TCState tcs[MIPS_SHADOW_SET_MAX]; 1099 CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 1100 /* QEMU */ 1101 int error_code; 1102 #define EXCP_TLB_NOMATCH 0x1 1103 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 1104 uint32_t hflags; /* CPU State */ 1105 /* TMASK defines different execution modes */ 1106 #define MIPS_HFLAG_TMASK 0x3F5807FF 1107 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 1108 /* 1109 * The KSU flags must be the lowest bits in hflags. The flag order 1110 * must be the same as defined for CP0 Status. This allows to use 1111 * the bits as the value of mmu_idx. 1112 */ 1113 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 1114 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 1115 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 1116 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 1117 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 1118 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 1119 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 1120 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 1121 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 1122 /* 1123 * True if the MIPS IV COP1X instructions can be used. This also 1124 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 1125 * and RSQRT.D. 1126 */ 1127 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 1128 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 1129 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 1130 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 1131 #define MIPS_HFLAG_M16_SHIFT 10 1132 /* 1133 * If translation is interrupted between the branch instruction and 1134 * the delay slot, record what type of branch it is so that we can 1135 * resume translation properly. It might be possible to reduce 1136 * this from three bits to two. 1137 */ 1138 #define MIPS_HFLAG_BMASK_BASE 0x803800 1139 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 1140 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 1141 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 1142 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 1143 /* Extra flags about the current pending branch. */ 1144 #define MIPS_HFLAG_BMASK_EXT 0x7C000 1145 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 1146 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 1147 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 1148 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 1149 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 1150 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 1151 /* MIPS DSP resources access. */ 1152 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ 1153 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ 1154 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ 1155 /* Extra flag about HWREna register. */ 1156 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 1157 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 1158 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 1159 #define MIPS_HFLAG_MSA 0x1000000 1160 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 1161 #define MIPS_HFLAG_ELPA 0x4000000 1162 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 1163 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ 1164 target_ulong btarget; /* Jump / branch target */ 1165 target_ulong bcond; /* Branch condition (if needed) */ 1166 1167 int SYNCI_Step; /* Address step size for SYNCI */ 1168 int CCRes; /* Cycle count resolution/divisor */ 1169 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 1170 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 1171 uint64_t insn_flags; /* Supported instruction set */ 1172 1173 /* Fields up to this point are cleared by a CPU reset */ 1174 struct {} end_reset_fields; 1175 1176 /* Fields from here on are preserved across CPU reset. */ 1177 CPUMIPSMVPContext *mvp; 1178 #if !defined(CONFIG_USER_ONLY) 1179 CPUMIPSTLBContext *tlb; 1180 qemu_irq irq[8]; 1181 MemoryRegion *itc_tag; /* ITC Configuration Tags */ 1182 1183 /* Loongson IOCSR memory */ 1184 struct { 1185 AddressSpace as; 1186 MemoryRegion mr; 1187 } iocsr; 1188 #endif 1189 1190 const mips_def_t *cpu_model; 1191 QEMUTimer *timer; /* Internal timer */ 1192 Clock *count_clock; /* CP0_Count clock */ 1193 target_ulong exception_base; /* ExceptionBase input to the core */ 1194 } CPUMIPSState; 1195 1196 /** 1197 * MIPSCPU: 1198 * @env: #CPUMIPSState 1199 * @clock: this CPU input clock (may be connected 1200 * to an output clock from another device). 1201 * 1202 * A MIPS CPU. 1203 */ 1204 struct ArchCPU { 1205 CPUState parent_obj; 1206 1207 CPUMIPSState env; 1208 1209 Clock *clock; 1210 Clock *count_div; /* Divider for CP0_Count clock */ 1211 1212 /* Properties */ 1213 bool is_big_endian; 1214 }; 1215 1216 /** 1217 * MIPSCPUClass: 1218 * @parent_realize: The parent class' realize handler. 1219 * @parent_phases: The parent class' reset phase handlers. 1220 * 1221 * A MIPS CPU model. 1222 */ 1223 struct MIPSCPUClass { 1224 CPUClass parent_class; 1225 1226 DeviceRealize parent_realize; 1227 ResettablePhases parent_phases; 1228 const struct mips_def_t *cpu_def; 1229 1230 /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ 1231 bool no_data_aborts; 1232 }; 1233 1234 void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 1235 uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 1236 1237 /* 1238 * MMU modes definitions. We carefully match the indices with our 1239 * hflags layout. 1240 */ 1241 #define MMU_KERNEL_IDX 0 1242 #define MMU_USER_IDX 2 1243 #define MMU_ERL_IDX 3 1244 hflags_mmu_index(uint32_t hflags)1245 static inline int hflags_mmu_index(uint32_t hflags) 1246 { 1247 if (hflags & MIPS_HFLAG_ERL) { 1248 return MMU_ERL_IDX; 1249 } else { 1250 return hflags & MIPS_HFLAG_KSU; 1251 } 1252 } 1253 mips_env_mmu_index(CPUMIPSState * env)1254 static inline int mips_env_mmu_index(CPUMIPSState *env) 1255 { 1256 return hflags_mmu_index(env->hflags); 1257 } 1258 1259 #include "exec/cpu-all.h" 1260 1261 /* Exceptions */ 1262 enum { 1263 EXCP_NONE = -1, 1264 EXCP_RESET = 0, 1265 EXCP_SRESET, 1266 EXCP_DSS, 1267 EXCP_DINT, 1268 EXCP_DDBL, 1269 EXCP_DDBS, 1270 EXCP_NMI, 1271 EXCP_MCHECK, 1272 EXCP_EXT_INTERRUPT, /* 8 */ 1273 EXCP_DFWATCH, 1274 EXCP_DIB, 1275 EXCP_IWATCH, 1276 EXCP_AdEL, 1277 EXCP_AdES, 1278 EXCP_TLBF, 1279 EXCP_IBE, 1280 EXCP_DBp, /* 16 */ 1281 EXCP_SYSCALL, 1282 EXCP_BREAK, 1283 EXCP_CpU, 1284 EXCP_RI, 1285 EXCP_OVERFLOW, 1286 EXCP_TRAP, 1287 EXCP_FPE, 1288 EXCP_DWATCH, /* 24 */ 1289 EXCP_LTLBL, 1290 EXCP_TLBL, 1291 EXCP_TLBS, 1292 EXCP_DBE, 1293 EXCP_THREAD, 1294 EXCP_MDMX, 1295 EXCP_C2E, 1296 EXCP_CACHE, /* 32 */ 1297 EXCP_DSPDIS, 1298 EXCP_MSADIS, 1299 EXCP_MSAFPE, 1300 EXCP_TLBXI, 1301 EXCP_TLBRI, 1302 EXCP_SEMIHOST, 1303 1304 EXCP_LAST = EXCP_SEMIHOST, 1305 }; 1306 1307 /* 1308 * This is an internally generated WAKE request line. 1309 * It is driven by the CPU itself. Raised when the MT 1310 * block wants to wake a VPE from an inactive state and 1311 * cleared when VPE goes from active to inactive. 1312 */ 1313 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 1314 1315 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 1316 1317 bool cpu_type_supports_cps_smp(const char *cpu_type); 1318 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); 1319 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); 1320 1321 /* Check presence of MIPS-3D ASE */ ase_3d_available(const CPUMIPSState * env)1322 static inline bool ase_3d_available(const CPUMIPSState *env) 1323 { 1324 return env->active_fpu.fcr0 & (1 << FCR0_3D); 1325 } 1326 1327 /* Check presence of MSA implementation */ ase_msa_available(CPUMIPSState * env)1328 static inline bool ase_msa_available(CPUMIPSState *env) 1329 { 1330 return env->CP0_Config3 & (1 << CP0C3_MSAP); 1331 } 1332 1333 /* Check presence of Loongson CSR instructions */ ase_lcsr_available(CPUMIPSState * env)1334 static inline bool ase_lcsr_available(CPUMIPSState *env) 1335 { 1336 return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP); 1337 } 1338 1339 /* Check presence of multi-threading ASE implementation */ ase_mt_available(CPUMIPSState * env)1340 static inline bool ase_mt_available(CPUMIPSState *env) 1341 { 1342 return env->CP0_Config3 & (1 << CP0C3_MT); 1343 } 1344 cpu_type_is_64bit(const char * cpu_type)1345 static inline bool cpu_type_is_64bit(const char *cpu_type) 1346 { 1347 return cpu_type_supports_isa(cpu_type, CPU_MIPS64); 1348 } 1349 1350 void cpu_set_exception_base(int vp_index, target_ulong address); 1351 1352 /* addr.c */ 1353 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); 1354 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); 1355 1356 uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr); 1357 uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); 1358 1359 #if !defined(CONFIG_USER_ONLY) 1360 1361 /* HW declaration specific to the MIPS target */ 1362 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 1363 void cpu_mips_irq_init_cpu(MIPSCPU *cpu); 1364 void cpu_mips_clock_init(MIPSCPU *cpu); 1365 1366 #endif /* !CONFIG_USER_ONLY */ 1367 1368 /* helper.c */ 1369 target_ulong exception_resume_pc(CPUMIPSState *env); 1370 cpu_get_tb_cpu_state(CPUMIPSState * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)1371 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, 1372 uint64_t *cs_base, uint32_t *flags) 1373 { 1374 *pc = env->active_tc.PC; 1375 *cs_base = 0; 1376 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 1377 MIPS_HFLAG_HWRENA_ULR); 1378 } 1379 1380 /** 1381 * mips_cpu_create_with_clock: 1382 * @typename: a MIPS CPU type. 1383 * @cpu_refclk: this cpu input clock (an output clock of another device) 1384 * @is_big_endian: whether this CPU is configured in big endianness 1385 * 1386 * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk, 1387 * then realizes the CPU. 1388 * 1389 * Returns: A #CPUState or %NULL if an error occurred. 1390 */ 1391 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, 1392 bool is_big_endian); 1393 1394 #endif /* MIPS_CPU_H */ 1395