1 /* 2 * QEMU MIPS CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internal.h" 27 #include "kvm_mips.h" 28 #include "qemu/module.h" 29 #include "sysemu/kvm.h" 30 #include "sysemu/qtest.h" 31 #include "exec/exec-all.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/qdev-clock.h" 34 #include "semihosting/semihost.h" 35 #include "qapi/qapi-commands-machine-target.h" 36 #include "fpu_helper.h" 37 38 const char regnames[32][3] = { 39 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 40 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 41 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 42 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 43 }; 44 45 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) 46 { 47 if (is_fpu64) { 48 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n", 49 fpr->w[FP_ENDIAN_IDX], fpr->d, 50 (double)fpr->fd, 51 (double)fpr->fs[FP_ENDIAN_IDX], 52 (double)fpr->fs[!FP_ENDIAN_IDX]); 53 } else { 54 fpr_t tmp; 55 56 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; 57 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; 58 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n", 59 tmp.w[FP_ENDIAN_IDX], tmp.d, 60 (double)tmp.fd, 61 (double)tmp.fs[FP_ENDIAN_IDX], 62 (double)tmp.fs[!FP_ENDIAN_IDX]); 63 } 64 } 65 66 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) 67 { 68 int i; 69 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); 70 71 qemu_fprintf(f, 72 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", 73 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, 74 get_float_exception_flags(&env->active_fpu.fp_status)); 75 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { 76 qemu_fprintf(f, "%3s: ", fregnames[i]); 77 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); 78 } 79 } 80 81 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) 82 { 83 MIPSCPU *cpu = MIPS_CPU(cs); 84 CPUMIPSState *env = &cpu->env; 85 int i; 86 87 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx 88 " LO=0x" TARGET_FMT_lx " ds %04x " 89 TARGET_FMT_lx " " TARGET_FMT_ld "\n", 90 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], 91 env->hflags, env->btarget, env->bcond); 92 for (i = 0; i < 32; i++) { 93 if ((i & 3) == 0) { 94 qemu_fprintf(f, "GPR%02d:", i); 95 } 96 qemu_fprintf(f, " %s " TARGET_FMT_lx, 97 regnames[i], env->active_tc.gpr[i]); 98 if ((i & 3) == 3) { 99 qemu_fprintf(f, "\n"); 100 } 101 } 102 103 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" 104 TARGET_FMT_lx "\n", 105 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); 106 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" 107 PRIx64 "\n", 108 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); 109 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", 110 env->CP0_Config2, env->CP0_Config3); 111 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", 112 env->CP0_Config4, env->CP0_Config5); 113 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { 114 fpu_dump_state(env, f, flags); 115 } 116 } 117 118 void cpu_set_exception_base(int vp_index, target_ulong address) 119 { 120 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); 121 vp->env.exception_base = address; 122 } 123 124 static void mips_cpu_set_pc(CPUState *cs, vaddr value) 125 { 126 MIPSCPU *cpu = MIPS_CPU(cs); 127 128 mips_env_set_pc(&cpu->env, value); 129 } 130 131 static vaddr mips_cpu_get_pc(CPUState *cs) 132 { 133 MIPSCPU *cpu = MIPS_CPU(cs); 134 135 return cpu->env.active_tc.PC; 136 } 137 138 static bool mips_cpu_has_work(CPUState *cs) 139 { 140 MIPSCPU *cpu = MIPS_CPU(cs); 141 CPUMIPSState *env = &cpu->env; 142 bool has_work = false; 143 144 /* 145 * Prior to MIPS Release 6 it is implementation dependent if non-enabled 146 * interrupts wake-up the CPU, however most of the implementations only 147 * check for interrupts that can be taken. 148 */ 149 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 150 cpu_mips_hw_interrupts_pending(env)) { 151 if (cpu_mips_hw_interrupts_enabled(env) || 152 (env->insn_flags & ISA_MIPS_R6)) { 153 has_work = true; 154 } 155 } 156 157 /* MIPS-MT has the ability to halt the CPU. */ 158 if (ase_mt_available(env)) { 159 /* 160 * The QEMU model will issue an _WAKE request whenever the CPUs 161 * should be woken up. 162 */ 163 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 164 has_work = true; 165 } 166 167 if (!mips_vpe_active(env)) { 168 has_work = false; 169 } 170 } 171 /* MIPS Release 6 has the ability to halt the CPU. */ 172 if (env->CP0_Config5 & (1 << CP0C5_VP)) { 173 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 174 has_work = true; 175 } 176 if (!mips_vp_active(env)) { 177 has_work = false; 178 } 179 } 180 return has_work; 181 } 182 183 #include "cpu-defs.c.inc" 184 185 static void mips_cpu_reset_hold(Object *obj) 186 { 187 CPUState *cs = CPU(obj); 188 MIPSCPU *cpu = MIPS_CPU(cs); 189 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); 190 CPUMIPSState *env = &cpu->env; 191 192 if (mcc->parent_phases.hold) { 193 mcc->parent_phases.hold(obj); 194 } 195 196 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); 197 198 /* Reset registers to their default values */ 199 env->CP0_PRid = env->cpu_model->CP0_PRid; 200 env->CP0_Config0 = env->cpu_model->CP0_Config0; 201 #if TARGET_BIG_ENDIAN 202 env->CP0_Config0 |= (1 << CP0C0_BE); 203 #endif 204 env->CP0_Config1 = env->cpu_model->CP0_Config1; 205 env->CP0_Config2 = env->cpu_model->CP0_Config2; 206 env->CP0_Config3 = env->cpu_model->CP0_Config3; 207 env->CP0_Config4 = env->cpu_model->CP0_Config4; 208 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; 209 env->CP0_Config5 = env->cpu_model->CP0_Config5; 210 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; 211 env->CP0_Config6 = env->cpu_model->CP0_Config6; 212 env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; 213 env->CP0_Config7 = env->cpu_model->CP0_Config7; 214 env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; 215 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask 216 << env->cpu_model->CP0_LLAddr_shift; 217 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; 218 env->SYNCI_Step = env->cpu_model->SYNCI_Step; 219 env->CCRes = env->cpu_model->CCRes; 220 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; 221 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; 222 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; 223 env->current_tc = 0; 224 env->SEGBITS = env->cpu_model->SEGBITS; 225 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); 226 #if defined(TARGET_MIPS64) 227 if (env->cpu_model->insn_flags & ISA_MIPS3) { 228 env->SEGMask |= 3ULL << 62; 229 } 230 #endif 231 env->PABITS = env->cpu_model->PABITS; 232 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; 233 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; 234 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; 235 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; 236 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; 237 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; 238 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; 239 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; 240 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; 241 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; 242 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; 243 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; 244 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; 245 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; 246 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; 247 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; 248 env->msair = env->cpu_model->MSAIR; 249 env->insn_flags = env->cpu_model->insn_flags; 250 251 #if defined(CONFIG_USER_ONLY) 252 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); 253 # ifdef TARGET_MIPS64 254 /* Enable 64-bit register mode. */ 255 env->CP0_Status |= (1 << CP0St_PX); 256 # endif 257 # ifdef TARGET_ABI_MIPSN64 258 /* Enable 64-bit address mode. */ 259 env->CP0_Status |= (1 << CP0St_UX); 260 # endif 261 /* 262 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR 263 * hardware registers. 264 */ 265 env->CP0_HWREna |= 0x0000000F; 266 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 267 env->CP0_Status |= (1 << CP0St_CU1); 268 } 269 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { 270 env->CP0_Status |= (1 << CP0St_MX); 271 } 272 # if defined(TARGET_MIPS64) 273 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ 274 if ((env->CP0_Config1 & (1 << CP0C1_FP)) && 275 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { 276 env->CP0_Status |= (1 << CP0St_FR); 277 } 278 # endif 279 #else /* !CONFIG_USER_ONLY */ 280 if (env->hflags & MIPS_HFLAG_BMASK) { 281 /* 282 * If the exception was raised from a delay slot, 283 * come back to the jump. 284 */ 285 env->CP0_ErrorEPC = (env->active_tc.PC 286 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); 287 } else { 288 env->CP0_ErrorEPC = env->active_tc.PC; 289 } 290 env->active_tc.PC = env->exception_base; 291 env->CP0_Random = env->tlb->nb_tlb - 1; 292 env->tlb->tlb_in_use = env->tlb->nb_tlb; 293 env->CP0_Wired = 0; 294 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; 295 env->CP0_EBase = (cs->cpu_index & 0x3FF); 296 if (mips_um_ksegs_enabled()) { 297 env->CP0_EBase |= 0x40000000; 298 } else { 299 env->CP0_EBase |= (int32_t)0x80000000; 300 } 301 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { 302 env->CP0_CMGCRBase = 0x1fbf8000 >> 4; 303 } 304 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 305 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; 306 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); 307 if (env->insn_flags & INSN_LOONGSON2F) { 308 /* Loongson-2F has those bits hardcoded to 1 */ 309 env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | 310 (1 << CP0St_UX); 311 } 312 313 /* 314 * Vectored interrupts not implemented, timer on int 7, 315 * no performance counters. 316 */ 317 env->CP0_IntCtl = 0xe0000000; 318 { 319 int i; 320 321 for (i = 0; i < 7; i++) { 322 env->CP0_WatchLo[i] = 0; 323 env->CP0_WatchHi[i] = 1 << CP0WH_M; 324 } 325 env->CP0_WatchLo[7] = 0; 326 env->CP0_WatchHi[7] = 0; 327 } 328 /* Count register increments in debug mode, EJTAG version 1 */ 329 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); 330 331 cpu_mips_store_count(env, 1); 332 333 if (ase_mt_available(env)) { 334 int i; 335 336 /* Only TC0 on VPE 0 starts as active. */ 337 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { 338 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; 339 env->tcs[i].CP0_TCHalt = 1; 340 } 341 env->active_tc.CP0_TCHalt = 1; 342 cs->halted = 1; 343 344 if (cs->cpu_index == 0) { 345 /* VPE0 starts up enabled. */ 346 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); 347 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); 348 349 /* TC0 starts up unhalted. */ 350 cs->halted = 0; 351 env->active_tc.CP0_TCHalt = 0; 352 env->tcs[0].CP0_TCHalt = 0; 353 /* With thread 0 active. */ 354 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); 355 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); 356 } 357 } 358 359 /* 360 * Configure default legacy segmentation control. We use this regardless of 361 * whether segmentation control is presented to the guest. 362 */ 363 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ 364 env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); 365 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ 366 env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; 367 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ 368 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 369 (2 << CP0SC_C); 370 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ 371 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 372 (3 << CP0SC_C)) << 16; 373 /* USeg (seg4 0x40000000..0x7FFFFFFF) */ 374 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 375 (1 << CP0SC_EU) | (2 << CP0SC_C); 376 /* USeg (seg5 0x00000000..0x3FFFFFFF) */ 377 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 378 (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; 379 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ 380 env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); 381 #endif /* !CONFIG_USER_ONLY */ 382 if ((env->insn_flags & ISA_MIPS_R6) && 383 (env->active_fpu.fcr0 & (1 << FCR0_F64))) { 384 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ 385 env->CP0_Status |= (1 << CP0St_FR); 386 } 387 388 if (env->insn_flags & ISA_MIPS_R6) { 389 /* PTW = 1 */ 390 env->CP0_PWSize = 0x40; 391 /* GDI = 12 */ 392 /* UDI = 12 */ 393 /* MDI = 12 */ 394 /* PRI = 12 */ 395 /* PTEI = 2 */ 396 env->CP0_PWField = 0x0C30C302; 397 } else { 398 /* GDI = 0 */ 399 /* UDI = 0 */ 400 /* MDI = 0 */ 401 /* PRI = 0 */ 402 /* PTEI = 2 */ 403 env->CP0_PWField = 0x02; 404 } 405 406 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { 407 /* microMIPS on reset when Config3.ISA is 3 */ 408 env->hflags |= MIPS_HFLAG_M16; 409 } 410 411 msa_reset(env); 412 413 compute_hflags(env); 414 restore_fp_status(env); 415 restore_pamask(env); 416 cs->exception_index = EXCP_NONE; 417 418 if (semihosting_get_argc()) { 419 /* UHI interface can be used to obtain argc and argv */ 420 env->active_tc.gpr[4] = -1; 421 } 422 423 #ifndef CONFIG_USER_ONLY 424 if (kvm_enabled()) { 425 kvm_mips_reset_vcpu(cpu); 426 } 427 #endif 428 } 429 430 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) 431 { 432 MIPSCPU *cpu = MIPS_CPU(s); 433 CPUMIPSState *env = &cpu->env; 434 435 if (!(env->insn_flags & ISA_NANOMIPS32)) { 436 #if TARGET_BIG_ENDIAN 437 info->print_insn = print_insn_big_mips; 438 #else 439 info->print_insn = print_insn_little_mips; 440 #endif 441 } else { 442 #if defined(CONFIG_NANOMIPS_DIS) 443 info->print_insn = print_insn_nanomips; 444 #endif 445 } 446 } 447 448 /* 449 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. 450 */ 451 #define CPU_FREQ_HZ_DEFAULT 200000000 452 453 static void mips_cp0_period_set(MIPSCPU *cpu) 454 { 455 CPUMIPSState *env = &cpu->env; 456 457 env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock, 458 env->cpu_model->CCRes); 459 assert(env->cp0_count_ns); 460 } 461 462 static void mips_cpu_realizefn(DeviceState *dev, Error **errp) 463 { 464 CPUState *cs = CPU(dev); 465 MIPSCPU *cpu = MIPS_CPU(dev); 466 CPUMIPSState *env = &cpu->env; 467 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); 468 Error *local_err = NULL; 469 470 if (!clock_get(cpu->clock)) { 471 #ifndef CONFIG_USER_ONLY 472 if (!qtest_enabled()) { 473 g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); 474 475 warn_report("CPU input clock is not connected to any output clock, " 476 "using default frequency of %s.", cpu_freq_str); 477 } 478 #endif 479 /* Initialize the frequency in case the clock remains unconnected. */ 480 clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); 481 } 482 mips_cp0_period_set(cpu); 483 484 cpu_exec_realizefn(cs, &local_err); 485 if (local_err != NULL) { 486 error_propagate(errp, local_err); 487 return; 488 } 489 490 env->exception_base = (int32_t)0xBFC00000; 491 492 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 493 mmu_init(env, env->cpu_model); 494 #endif 495 fpu_init(env, env->cpu_model); 496 mvp_init(env); 497 498 cpu_reset(cs); 499 qemu_init_vcpu(cs); 500 501 mcc->parent_realize(dev, errp); 502 } 503 504 static void mips_cpu_initfn(Object *obj) 505 { 506 MIPSCPU *cpu = MIPS_CPU(obj); 507 CPUMIPSState *env = &cpu->env; 508 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 509 510 cpu_set_cpustate_pointers(cpu); 511 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 512 env->cpu_model = mcc->cpu_def; 513 } 514 515 static char *mips_cpu_type_name(const char *cpu_model) 516 { 517 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); 518 } 519 520 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) 521 { 522 ObjectClass *oc; 523 char *typename; 524 525 typename = mips_cpu_type_name(cpu_model); 526 oc = object_class_by_name(typename); 527 g_free(typename); 528 return oc; 529 } 530 531 #ifndef CONFIG_USER_ONLY 532 #include "hw/core/sysemu-cpu-ops.h" 533 534 static const struct SysemuCPUOps mips_sysemu_ops = { 535 .get_phys_page_debug = mips_cpu_get_phys_page_debug, 536 .legacy_vmsd = &vmstate_mips_cpu, 537 }; 538 #endif 539 540 #ifdef CONFIG_TCG 541 #include "hw/core/tcg-cpu-ops.h" 542 /* 543 * NB: cannot be const, as some elements are changed for specific 544 * mips hardware (see hw/mips/jazz.c). 545 */ 546 static const struct TCGCPUOps mips_tcg_ops = { 547 .initialize = mips_tcg_init, 548 .synchronize_from_tb = mips_cpu_synchronize_from_tb, 549 .restore_state_to_opc = mips_restore_state_to_opc, 550 551 #if !defined(CONFIG_USER_ONLY) 552 .tlb_fill = mips_cpu_tlb_fill, 553 .cpu_exec_interrupt = mips_cpu_exec_interrupt, 554 .do_interrupt = mips_cpu_do_interrupt, 555 .do_transaction_failed = mips_cpu_do_transaction_failed, 556 .do_unaligned_access = mips_cpu_do_unaligned_access, 557 .io_recompile_replay_branch = mips_io_recompile_replay_branch, 558 #endif /* !CONFIG_USER_ONLY */ 559 }; 560 #endif /* CONFIG_TCG */ 561 562 static void mips_cpu_class_init(ObjectClass *c, void *data) 563 { 564 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); 565 CPUClass *cc = CPU_CLASS(c); 566 DeviceClass *dc = DEVICE_CLASS(c); 567 ResettableClass *rc = RESETTABLE_CLASS(c); 568 569 device_class_set_parent_realize(dc, mips_cpu_realizefn, 570 &mcc->parent_realize); 571 resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, 572 &mcc->parent_phases); 573 574 cc->class_by_name = mips_cpu_class_by_name; 575 cc->has_work = mips_cpu_has_work; 576 cc->dump_state = mips_cpu_dump_state; 577 cc->set_pc = mips_cpu_set_pc; 578 cc->get_pc = mips_cpu_get_pc; 579 cc->gdb_read_register = mips_cpu_gdb_read_register; 580 cc->gdb_write_register = mips_cpu_gdb_write_register; 581 #ifndef CONFIG_USER_ONLY 582 cc->sysemu_ops = &mips_sysemu_ops; 583 #endif 584 cc->disas_set_info = mips_cpu_disas_set_info; 585 cc->gdb_num_core_regs = 73; 586 cc->gdb_stop_before_watchpoint = true; 587 #ifdef CONFIG_TCG 588 cc->tcg_ops = &mips_tcg_ops; 589 #endif /* CONFIG_TCG */ 590 } 591 592 static const TypeInfo mips_cpu_type_info = { 593 .name = TYPE_MIPS_CPU, 594 .parent = TYPE_CPU, 595 .instance_size = sizeof(MIPSCPU), 596 .instance_init = mips_cpu_initfn, 597 .abstract = true, 598 .class_size = sizeof(MIPSCPUClass), 599 .class_init = mips_cpu_class_init, 600 }; 601 602 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) 603 { 604 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); 605 mcc->cpu_def = data; 606 } 607 608 static void mips_register_cpudef_type(const struct mips_def_t *def) 609 { 610 char *typename = mips_cpu_type_name(def->name); 611 TypeInfo ti = { 612 .name = typename, 613 .parent = TYPE_MIPS_CPU, 614 .class_init = mips_cpu_cpudef_class_init, 615 .class_data = (void *)def, 616 }; 617 618 type_register(&ti); 619 g_free(typename); 620 } 621 622 static void mips_cpu_register_types(void) 623 { 624 int i; 625 626 type_register_static(&mips_cpu_type_info); 627 for (i = 0; i < mips_defs_number; i++) { 628 mips_register_cpudef_type(&mips_defs[i]); 629 } 630 } 631 632 type_init(mips_cpu_register_types) 633 634 static void mips_cpu_add_definition(gpointer data, gpointer user_data) 635 { 636 ObjectClass *oc = data; 637 CpuDefinitionInfoList **cpu_list = user_data; 638 CpuDefinitionInfo *info; 639 const char *typename; 640 641 typename = object_class_get_name(oc); 642 info = g_malloc0(sizeof(*info)); 643 info->name = g_strndup(typename, 644 strlen(typename) - strlen("-" TYPE_MIPS_CPU)); 645 info->q_typename = g_strdup(typename); 646 647 QAPI_LIST_PREPEND(*cpu_list, info); 648 } 649 650 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 651 { 652 CpuDefinitionInfoList *cpu_list = NULL; 653 GSList *list; 654 655 list = object_class_get_list(TYPE_MIPS_CPU, false); 656 g_slist_foreach(list, mips_cpu_add_definition, &cpu_list); 657 g_slist_free(list); 658 659 return cpu_list; 660 } 661 662 /* Could be used by generic CPU object */ 663 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) 664 { 665 DeviceState *cpu; 666 667 cpu = DEVICE(object_new(cpu_type)); 668 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 669 qdev_realize(cpu, NULL, &error_abort); 670 671 return MIPS_CPU(cpu); 672 } 673 674 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) 675 { 676 return (env->cpu_model->insn_flags & isa_mask) != 0; 677 } 678 679 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) 680 { 681 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 682 return (mcc->cpu_def->insn_flags & isa) != 0; 683 } 684 685 bool cpu_type_supports_cps_smp(const char *cpu_type) 686 { 687 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 688 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; 689 } 690