xref: /openbmc/qemu/target/mips/cpu.c (revision 7f709ce7)
1 /*
2  * QEMU MIPS CPU
3  *
4  * Copyright (c) 2012 SUSE LINUX Products GmbH
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "cpu.h"
24 #include "internal.h"
25 #include "kvm_mips.h"
26 #include "qemu-common.h"
27 #include "sysemu/kvm.h"
28 #include "exec/exec-all.h"
29 
30 
31 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
32 {
33     MIPSCPU *cpu = MIPS_CPU(cs);
34     CPUMIPSState *env = &cpu->env;
35 
36     env->active_tc.PC = value & ~(target_ulong)1;
37     if (value & 1) {
38         env->hflags |= MIPS_HFLAG_M16;
39     } else {
40         env->hflags &= ~(MIPS_HFLAG_M16);
41     }
42 }
43 
44 static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
45 {
46     MIPSCPU *cpu = MIPS_CPU(cs);
47     CPUMIPSState *env = &cpu->env;
48 
49     env->active_tc.PC = tb->pc;
50     env->hflags &= ~MIPS_HFLAG_BMASK;
51     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
52 }
53 
54 static bool mips_cpu_has_work(CPUState *cs)
55 {
56     MIPSCPU *cpu = MIPS_CPU(cs);
57     CPUMIPSState *env = &cpu->env;
58     bool has_work = false;
59 
60     /* Prior to MIPS Release 6 it is implementation dependent if non-enabled
61        interrupts wake-up the CPU, however most of the implementations only
62        check for interrupts that can be taken. */
63     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
64         cpu_mips_hw_interrupts_pending(env)) {
65         if (cpu_mips_hw_interrupts_enabled(env) ||
66             (env->insn_flags & ISA_MIPS32R6)) {
67             has_work = true;
68         }
69     }
70 
71     /* MIPS-MT has the ability to halt the CPU.  */
72     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
73         /* The QEMU model will issue an _WAKE request whenever the CPUs
74            should be woken up.  */
75         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
76             has_work = true;
77         }
78 
79         if (!mips_vpe_active(env)) {
80             has_work = false;
81         }
82     }
83     /* MIPS Release 6 has the ability to halt the CPU.  */
84     if (env->CP0_Config5 & (1 << CP0C5_VP)) {
85         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
86             has_work = true;
87         }
88         if (!mips_vp_active(env)) {
89             has_work = false;
90         }
91     }
92     return has_work;
93 }
94 
95 /* CPUClass::reset() */
96 static void mips_cpu_reset(CPUState *s)
97 {
98     MIPSCPU *cpu = MIPS_CPU(s);
99     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
100     CPUMIPSState *env = &cpu->env;
101 
102     mcc->parent_reset(s);
103 
104     memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
105 
106     cpu_state_reset(env);
107 
108 #ifndef CONFIG_USER_ONLY
109     if (kvm_enabled()) {
110         kvm_mips_reset_vcpu(cpu);
111     }
112 #endif
113 }
114 
115 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
116 #ifdef TARGET_WORDS_BIGENDIAN
117     info->print_insn = print_insn_big_mips;
118 #else
119     info->print_insn = print_insn_little_mips;
120 #endif
121 }
122 
123 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
124 {
125     CPUState *cs = CPU(dev);
126     MIPSCPU *cpu = MIPS_CPU(dev);
127     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
128     Error *local_err = NULL;
129 
130     cpu_exec_realizefn(cs, &local_err);
131     if (local_err != NULL) {
132         error_propagate(errp, local_err);
133         return;
134     }
135 
136     cpu_mips_realize_env(&cpu->env);
137 
138     cpu_reset(cs);
139     qemu_init_vcpu(cs);
140 
141     mcc->parent_realize(dev, errp);
142 }
143 
144 static void mips_cpu_initfn(Object *obj)
145 {
146     CPUState *cs = CPU(obj);
147     MIPSCPU *cpu = MIPS_CPU(obj);
148     CPUMIPSState *env = &cpu->env;
149     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
150 
151     cs->env_ptr = env;
152     env->cpu_model = mcc->cpu_def;
153 }
154 
155 static char *mips_cpu_type_name(const char *cpu_model)
156 {
157     return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
158 }
159 
160 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
161 {
162     ObjectClass *oc;
163     char *typename;
164 
165     typename = mips_cpu_type_name(cpu_model);
166     oc = object_class_by_name(typename);
167     g_free(typename);
168     return oc;
169 }
170 
171 static void mips_cpu_class_init(ObjectClass *c, void *data)
172 {
173     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
174     CPUClass *cc = CPU_CLASS(c);
175     DeviceClass *dc = DEVICE_CLASS(c);
176 
177     mcc->parent_realize = dc->realize;
178     dc->realize = mips_cpu_realizefn;
179 
180     mcc->parent_reset = cc->reset;
181     cc->reset = mips_cpu_reset;
182 
183     cc->class_by_name = mips_cpu_class_by_name;
184     cc->has_work = mips_cpu_has_work;
185     cc->do_interrupt = mips_cpu_do_interrupt;
186     cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
187     cc->dump_state = mips_cpu_dump_state;
188     cc->set_pc = mips_cpu_set_pc;
189     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
190     cc->gdb_read_register = mips_cpu_gdb_read_register;
191     cc->gdb_write_register = mips_cpu_gdb_write_register;
192 #ifdef CONFIG_USER_ONLY
193     cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
194 #else
195     cc->do_unassigned_access = mips_cpu_unassigned_access;
196     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
197     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
198     cc->vmsd = &vmstate_mips_cpu;
199 #endif
200     cc->disas_set_info = mips_cpu_disas_set_info;
201 #ifdef CONFIG_TCG
202     cc->tcg_initialize = mips_tcg_init;
203 #endif
204 
205     cc->gdb_num_core_regs = 73;
206     cc->gdb_stop_before_watchpoint = true;
207 }
208 
209 static const TypeInfo mips_cpu_type_info = {
210     .name = TYPE_MIPS_CPU,
211     .parent = TYPE_CPU,
212     .instance_size = sizeof(MIPSCPU),
213     .instance_init = mips_cpu_initfn,
214     .abstract = true,
215     .class_size = sizeof(MIPSCPUClass),
216     .class_init = mips_cpu_class_init,
217 };
218 
219 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
220 {
221     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
222     mcc->cpu_def = data;
223 }
224 
225 static void mips_register_cpudef_type(const struct mips_def_t *def)
226 {
227     char *typename = mips_cpu_type_name(def->name);
228     TypeInfo ti = {
229         .name = typename,
230         .parent = TYPE_MIPS_CPU,
231         .class_init = mips_cpu_cpudef_class_init,
232         .class_data = (void *)def,
233     };
234 
235     type_register(&ti);
236     g_free(typename);
237 }
238 
239 static void mips_cpu_register_types(void)
240 {
241     int i;
242 
243     type_register_static(&mips_cpu_type_info);
244     for (i = 0; i < mips_defs_number; i++) {
245         mips_register_cpudef_type(&mips_defs[i]);
246     }
247 }
248 
249 type_init(mips_cpu_register_types)
250