1 /* 2 * QEMU MIPS CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "internal.h" 28 #include "kvm_mips.h" 29 #include "qemu/module.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/qtest.h" 32 #include "exec/exec-all.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-clock.h" 35 #include "semihosting/semihost.h" 36 #include "fpu_helper.h" 37 38 const char regnames[32][3] = { 39 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 40 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 41 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 42 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 43 }; 44 45 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) 46 { 47 if (is_fpu64) { 48 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n", 49 fpr->w[FP_ENDIAN_IDX], fpr->d, 50 (double)fpr->fd, 51 (double)fpr->fs[FP_ENDIAN_IDX], 52 (double)fpr->fs[!FP_ENDIAN_IDX]); 53 } else { 54 fpr_t tmp; 55 56 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; 57 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; 58 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n", 59 tmp.w[FP_ENDIAN_IDX], tmp.d, 60 (double)tmp.fd, 61 (double)tmp.fs[FP_ENDIAN_IDX], 62 (double)tmp.fs[!FP_ENDIAN_IDX]); 63 } 64 } 65 66 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) 67 { 68 int i; 69 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); 70 71 qemu_fprintf(f, 72 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", 73 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, 74 get_float_exception_flags(&env->active_fpu.fp_status)); 75 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { 76 qemu_fprintf(f, "%3s: ", fregnames[i]); 77 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); 78 } 79 } 80 81 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) 82 { 83 MIPSCPU *cpu = MIPS_CPU(cs); 84 CPUMIPSState *env = &cpu->env; 85 int i; 86 87 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx 88 " LO=0x" TARGET_FMT_lx " ds %04x " 89 TARGET_FMT_lx " " TARGET_FMT_ld "\n", 90 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], 91 env->hflags, env->btarget, env->bcond); 92 for (i = 0; i < 32; i++) { 93 if ((i & 3) == 0) { 94 qemu_fprintf(f, "GPR%02d:", i); 95 } 96 qemu_fprintf(f, " %s " TARGET_FMT_lx, 97 regnames[i], env->active_tc.gpr[i]); 98 if ((i & 3) == 3) { 99 qemu_fprintf(f, "\n"); 100 } 101 } 102 103 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" 104 TARGET_FMT_lx "\n", 105 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); 106 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" 107 PRIx64 "\n", 108 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); 109 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", 110 env->CP0_Config2, env->CP0_Config3); 111 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", 112 env->CP0_Config4, env->CP0_Config5); 113 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { 114 fpu_dump_state(env, f, flags); 115 } 116 } 117 118 void cpu_set_exception_base(int vp_index, target_ulong address) 119 { 120 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); 121 vp->env.exception_base = address; 122 } 123 124 static void mips_cpu_set_pc(CPUState *cs, vaddr value) 125 { 126 MIPSCPU *cpu = MIPS_CPU(cs); 127 128 mips_env_set_pc(&cpu->env, value); 129 } 130 131 static vaddr mips_cpu_get_pc(CPUState *cs) 132 { 133 MIPSCPU *cpu = MIPS_CPU(cs); 134 135 return cpu->env.active_tc.PC; 136 } 137 138 static bool mips_cpu_has_work(CPUState *cs) 139 { 140 MIPSCPU *cpu = MIPS_CPU(cs); 141 CPUMIPSState *env = &cpu->env; 142 bool has_work = false; 143 144 /* 145 * Prior to MIPS Release 6 it is implementation dependent if non-enabled 146 * interrupts wake-up the CPU, however most of the implementations only 147 * check for interrupts that can be taken. For pre-release 6 CPUs, 148 * check for CP0 Config7 'Wait IE ignore' bit. 149 */ 150 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 151 cpu_mips_hw_interrupts_pending(env)) { 152 if (cpu_mips_hw_interrupts_enabled(env) || 153 (env->CP0_Config7 & (1 << CP0C7_WII)) || 154 (env->insn_flags & ISA_MIPS_R6)) { 155 has_work = true; 156 } 157 } 158 159 /* MIPS-MT has the ability to halt the CPU. */ 160 if (ase_mt_available(env)) { 161 /* 162 * The QEMU model will issue an _WAKE request whenever the CPUs 163 * should be woken up. 164 */ 165 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 166 has_work = true; 167 } 168 169 if (!mips_vpe_active(env)) { 170 has_work = false; 171 } 172 } 173 /* MIPS Release 6 has the ability to halt the CPU. */ 174 if (env->CP0_Config5 & (1 << CP0C5_VP)) { 175 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 176 has_work = true; 177 } 178 if (!mips_vp_active(env)) { 179 has_work = false; 180 } 181 } 182 return has_work; 183 } 184 185 static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) 186 { 187 return mips_env_mmu_index(cpu_env(cs)); 188 } 189 190 #include "cpu-defs.c.inc" 191 192 static void mips_cpu_reset_hold(Object *obj) 193 { 194 CPUState *cs = CPU(obj); 195 MIPSCPU *cpu = MIPS_CPU(cs); 196 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); 197 CPUMIPSState *env = &cpu->env; 198 199 if (mcc->parent_phases.hold) { 200 mcc->parent_phases.hold(obj); 201 } 202 203 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); 204 205 /* Reset registers to their default values */ 206 env->CP0_PRid = env->cpu_model->CP0_PRid; 207 env->CP0_Config0 = env->cpu_model->CP0_Config0; 208 #if TARGET_BIG_ENDIAN 209 env->CP0_Config0 |= (1 << CP0C0_BE); 210 #endif 211 env->CP0_Config1 = env->cpu_model->CP0_Config1; 212 env->CP0_Config2 = env->cpu_model->CP0_Config2; 213 env->CP0_Config3 = env->cpu_model->CP0_Config3; 214 env->CP0_Config4 = env->cpu_model->CP0_Config4; 215 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; 216 env->CP0_Config5 = env->cpu_model->CP0_Config5; 217 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; 218 env->CP0_Config6 = env->cpu_model->CP0_Config6; 219 env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; 220 env->CP0_Config7 = env->cpu_model->CP0_Config7; 221 env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; 222 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask 223 << env->cpu_model->CP0_LLAddr_shift; 224 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; 225 env->SYNCI_Step = env->cpu_model->SYNCI_Step; 226 env->CCRes = env->cpu_model->CCRes; 227 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; 228 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; 229 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; 230 env->current_tc = 0; 231 env->SEGBITS = env->cpu_model->SEGBITS; 232 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); 233 #if defined(TARGET_MIPS64) 234 if (env->cpu_model->insn_flags & ISA_MIPS3) { 235 env->SEGMask |= 3ULL << 62; 236 } 237 #endif 238 env->PABITS = env->cpu_model->PABITS; 239 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; 240 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; 241 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; 242 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; 243 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; 244 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; 245 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; 246 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; 247 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; 248 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; 249 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; 250 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; 251 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; 252 env->lcsr_cpucfg1 = env->cpu_model->lcsr_cpucfg1; 253 env->lcsr_cpucfg2 = env->cpu_model->lcsr_cpucfg2; 254 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; 255 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; 256 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; 257 env->msair = env->cpu_model->MSAIR; 258 env->insn_flags = env->cpu_model->insn_flags; 259 260 #if defined(CONFIG_USER_ONLY) 261 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); 262 # ifdef TARGET_MIPS64 263 /* Enable 64-bit register mode. */ 264 env->CP0_Status |= (1 << CP0St_PX); 265 # endif 266 # ifdef TARGET_ABI_MIPSN64 267 /* Enable 64-bit address mode. */ 268 env->CP0_Status |= (1 << CP0St_UX); 269 # endif 270 /* 271 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR 272 * hardware registers. 273 */ 274 env->CP0_HWREna |= 0x0000000F; 275 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 276 env->CP0_Status |= (1 << CP0St_CU1); 277 } 278 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { 279 env->CP0_Status |= (1 << CP0St_MX); 280 } 281 # if defined(TARGET_MIPS64) 282 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ 283 if ((env->CP0_Config1 & (1 << CP0C1_FP)) && 284 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { 285 env->CP0_Status |= (1 << CP0St_FR); 286 } 287 # endif 288 #else /* !CONFIG_USER_ONLY */ 289 if (env->hflags & MIPS_HFLAG_BMASK) { 290 /* 291 * If the exception was raised from a delay slot, 292 * come back to the jump. 293 */ 294 env->CP0_ErrorEPC = (env->active_tc.PC 295 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); 296 } else { 297 env->CP0_ErrorEPC = env->active_tc.PC; 298 } 299 env->active_tc.PC = env->exception_base; 300 env->CP0_Random = env->tlb->nb_tlb - 1; 301 env->tlb->tlb_in_use = env->tlb->nb_tlb; 302 env->CP0_Wired = 0; 303 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; 304 env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF); 305 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { 306 env->CP0_CMGCRBase = 0x1fbf8000 >> 4; 307 } 308 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 309 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; 310 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); 311 if (env->insn_flags & INSN_LOONGSON2F) { 312 /* Loongson-2F has those bits hardcoded to 1 */ 313 env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | 314 (1 << CP0St_UX); 315 } 316 317 /* 318 * Vectored interrupts not implemented, timer on int 7, 319 * no performance counters. 320 */ 321 env->CP0_IntCtl = 0xe0000000; 322 { 323 int i; 324 325 for (i = 0; i < 7; i++) { 326 env->CP0_WatchLo[i] = 0; 327 env->CP0_WatchHi[i] = 1 << CP0WH_M; 328 } 329 env->CP0_WatchLo[7] = 0; 330 env->CP0_WatchHi[7] = 0; 331 } 332 /* Count register increments in debug mode, EJTAG version 1 */ 333 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); 334 335 cpu_mips_store_count(env, 1); 336 337 if (ase_mt_available(env)) { 338 int i; 339 340 /* Only TC0 on VPE 0 starts as active. */ 341 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { 342 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; 343 env->tcs[i].CP0_TCHalt = 1; 344 } 345 env->active_tc.CP0_TCHalt = 1; 346 cs->halted = 1; 347 348 if (cs->cpu_index == 0) { 349 /* VPE0 starts up enabled. */ 350 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); 351 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); 352 353 /* TC0 starts up unhalted. */ 354 cs->halted = 0; 355 env->active_tc.CP0_TCHalt = 0; 356 env->tcs[0].CP0_TCHalt = 0; 357 /* With thread 0 active. */ 358 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); 359 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); 360 } 361 } 362 363 /* 364 * Configure default legacy segmentation control. We use this regardless of 365 * whether segmentation control is presented to the guest. 366 */ 367 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ 368 env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); 369 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ 370 env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; 371 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ 372 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 373 (2 << CP0SC_C); 374 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ 375 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 376 (3 << CP0SC_C)) << 16; 377 /* USeg (seg4 0x40000000..0x7FFFFFFF) */ 378 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 379 (1 << CP0SC_EU) | (2 << CP0SC_C); 380 /* USeg (seg5 0x00000000..0x3FFFFFFF) */ 381 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 382 (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; 383 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ 384 env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); 385 #endif /* !CONFIG_USER_ONLY */ 386 if ((env->insn_flags & ISA_MIPS_R6) && 387 (env->active_fpu.fcr0 & (1 << FCR0_F64))) { 388 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ 389 env->CP0_Status |= (1 << CP0St_FR); 390 } 391 392 if (env->insn_flags & ISA_MIPS_R6) { 393 /* PTW = 1 */ 394 env->CP0_PWSize = 0x40; 395 /* GDI = 12 */ 396 /* UDI = 12 */ 397 /* MDI = 12 */ 398 /* PRI = 12 */ 399 /* PTEI = 2 */ 400 env->CP0_PWField = 0x0C30C302; 401 } else { 402 /* GDI = 0 */ 403 /* UDI = 0 */ 404 /* MDI = 0 */ 405 /* PRI = 0 */ 406 /* PTEI = 2 */ 407 env->CP0_PWField = 0x02; 408 } 409 410 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { 411 /* microMIPS on reset when Config3.ISA is 3 */ 412 env->hflags |= MIPS_HFLAG_M16; 413 } 414 415 msa_reset(env); 416 417 compute_hflags(env); 418 restore_fp_status(env); 419 restore_pamask(env); 420 cs->exception_index = EXCP_NONE; 421 422 if (semihosting_get_argc()) { 423 /* UHI interface can be used to obtain argc and argv */ 424 env->active_tc.gpr[4] = -1; 425 } 426 427 #ifndef CONFIG_USER_ONLY 428 if (kvm_enabled()) { 429 kvm_mips_reset_vcpu(cpu); 430 } 431 #endif 432 } 433 434 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) 435 { 436 MIPSCPU *cpu = MIPS_CPU(s); 437 CPUMIPSState *env = &cpu->env; 438 439 if (!(env->insn_flags & ISA_NANOMIPS32)) { 440 #if TARGET_BIG_ENDIAN 441 info->print_insn = print_insn_big_mips; 442 #else 443 info->print_insn = print_insn_little_mips; 444 #endif 445 } else { 446 info->print_insn = print_insn_nanomips; 447 } 448 } 449 450 /* 451 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. 452 */ 453 #define CPU_FREQ_HZ_DEFAULT 200000000 454 455 static void mips_cp0_period_set(MIPSCPU *cpu) 456 { 457 CPUMIPSState *env = &cpu->env; 458 459 clock_set_mul_div(cpu->count_div, env->cpu_model->CCRes, 1); 460 clock_set_source(cpu->count_div, cpu->clock); 461 clock_set_source(env->count_clock, cpu->count_div); 462 } 463 464 static void mips_cpu_realizefn(DeviceState *dev, Error **errp) 465 { 466 CPUState *cs = CPU(dev); 467 MIPSCPU *cpu = MIPS_CPU(dev); 468 CPUMIPSState *env = &cpu->env; 469 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); 470 Error *local_err = NULL; 471 472 if (!clock_get(cpu->clock)) { 473 #ifndef CONFIG_USER_ONLY 474 if (!qtest_enabled()) { 475 g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); 476 477 warn_report("CPU input clock is not connected to any output clock, " 478 "using default frequency of %s.", cpu_freq_str); 479 } 480 #endif 481 /* Initialize the frequency in case the clock remains unconnected. */ 482 clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); 483 } 484 mips_cp0_period_set(cpu); 485 486 cpu_exec_realizefn(cs, &local_err); 487 if (local_err != NULL) { 488 error_propagate(errp, local_err); 489 return; 490 } 491 492 env->exception_base = (int32_t)0xBFC00000; 493 494 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 495 mmu_init(env, env->cpu_model); 496 #endif 497 fpu_init(env, env->cpu_model); 498 mvp_init(env); 499 500 cpu_reset(cs); 501 qemu_init_vcpu(cs); 502 503 mcc->parent_realize(dev, errp); 504 } 505 506 static void mips_cpu_initfn(Object *obj) 507 { 508 MIPSCPU *cpu = MIPS_CPU(obj); 509 CPUMIPSState *env = &cpu->env; 510 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 511 512 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 513 cpu->count_div = clock_new(OBJECT(obj), "clk-div-count"); 514 env->count_clock = clock_new(OBJECT(obj), "clk-count"); 515 env->cpu_model = mcc->cpu_def; 516 #ifndef CONFIG_USER_ONLY 517 if (mcc->cpu_def->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP)) { 518 memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL, 519 env, "iocsr", UINT64_MAX); 520 address_space_init(&env->iocsr.as, 521 &env->iocsr.mr, "IOCSR"); 522 } 523 #endif 524 } 525 526 static char *mips_cpu_type_name(const char *cpu_model) 527 { 528 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); 529 } 530 531 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) 532 { 533 ObjectClass *oc; 534 char *typename; 535 536 typename = mips_cpu_type_name(cpu_model); 537 oc = object_class_by_name(typename); 538 g_free(typename); 539 return oc; 540 } 541 542 #ifndef CONFIG_USER_ONLY 543 #include "hw/core/sysemu-cpu-ops.h" 544 545 static const struct SysemuCPUOps mips_sysemu_ops = { 546 .get_phys_page_debug = mips_cpu_get_phys_page_debug, 547 .legacy_vmsd = &vmstate_mips_cpu, 548 }; 549 #endif 550 551 #ifdef CONFIG_TCG 552 #include "hw/core/tcg-cpu-ops.h" 553 /* 554 * NB: cannot be const, as some elements are changed for specific 555 * mips hardware (see hw/mips/jazz.c). 556 */ 557 static const TCGCPUOps mips_tcg_ops = { 558 .initialize = mips_tcg_init, 559 .synchronize_from_tb = mips_cpu_synchronize_from_tb, 560 .restore_state_to_opc = mips_restore_state_to_opc, 561 562 #if !defined(CONFIG_USER_ONLY) 563 .tlb_fill = mips_cpu_tlb_fill, 564 .cpu_exec_interrupt = mips_cpu_exec_interrupt, 565 .do_interrupt = mips_cpu_do_interrupt, 566 .do_transaction_failed = mips_cpu_do_transaction_failed, 567 .do_unaligned_access = mips_cpu_do_unaligned_access, 568 .io_recompile_replay_branch = mips_io_recompile_replay_branch, 569 #endif /* !CONFIG_USER_ONLY */ 570 }; 571 #endif /* CONFIG_TCG */ 572 573 static void mips_cpu_class_init(ObjectClass *c, void *data) 574 { 575 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); 576 CPUClass *cc = CPU_CLASS(c); 577 DeviceClass *dc = DEVICE_CLASS(c); 578 ResettableClass *rc = RESETTABLE_CLASS(c); 579 580 device_class_set_parent_realize(dc, mips_cpu_realizefn, 581 &mcc->parent_realize); 582 resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, 583 &mcc->parent_phases); 584 585 cc->class_by_name = mips_cpu_class_by_name; 586 cc->has_work = mips_cpu_has_work; 587 cc->mmu_index = mips_cpu_mmu_index; 588 cc->dump_state = mips_cpu_dump_state; 589 cc->set_pc = mips_cpu_set_pc; 590 cc->get_pc = mips_cpu_get_pc; 591 cc->gdb_read_register = mips_cpu_gdb_read_register; 592 cc->gdb_write_register = mips_cpu_gdb_write_register; 593 #ifndef CONFIG_USER_ONLY 594 cc->sysemu_ops = &mips_sysemu_ops; 595 #endif 596 cc->disas_set_info = mips_cpu_disas_set_info; 597 cc->gdb_num_core_regs = 73; 598 cc->gdb_stop_before_watchpoint = true; 599 #ifdef CONFIG_TCG 600 cc->tcg_ops = &mips_tcg_ops; 601 #endif /* CONFIG_TCG */ 602 } 603 604 static const TypeInfo mips_cpu_type_info = { 605 .name = TYPE_MIPS_CPU, 606 .parent = TYPE_CPU, 607 .instance_size = sizeof(MIPSCPU), 608 .instance_align = __alignof(MIPSCPU), 609 .instance_init = mips_cpu_initfn, 610 .abstract = true, 611 .class_size = sizeof(MIPSCPUClass), 612 .class_init = mips_cpu_class_init, 613 }; 614 615 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) 616 { 617 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); 618 mcc->cpu_def = data; 619 } 620 621 static void mips_register_cpudef_type(const struct mips_def_t *def) 622 { 623 char *typename = mips_cpu_type_name(def->name); 624 TypeInfo ti = { 625 .name = typename, 626 .parent = TYPE_MIPS_CPU, 627 .class_init = mips_cpu_cpudef_class_init, 628 .class_data = (void *)def, 629 }; 630 631 type_register(&ti); 632 g_free(typename); 633 } 634 635 static void mips_cpu_register_types(void) 636 { 637 int i; 638 639 type_register_static(&mips_cpu_type_info); 640 for (i = 0; i < mips_defs_number; i++) { 641 mips_register_cpudef_type(&mips_defs[i]); 642 } 643 } 644 645 type_init(mips_cpu_register_types) 646 647 /* Could be used by generic CPU object */ 648 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) 649 { 650 DeviceState *cpu; 651 652 cpu = DEVICE(object_new(cpu_type)); 653 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 654 qdev_realize(cpu, NULL, &error_abort); 655 656 return MIPS_CPU(cpu); 657 } 658 659 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) 660 { 661 return (env->cpu_model->insn_flags & isa_mask) != 0; 662 } 663 664 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) 665 { 666 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 667 return (mcc->cpu_def->insn_flags & isa) != 0; 668 } 669 670 bool cpu_type_supports_cps_smp(const char *cpu_type) 671 { 672 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 673 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; 674 } 675