1 /* 2 * QEMU MIPS CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internal.h" 27 #include "kvm_mips.h" 28 #include "qemu/module.h" 29 #include "sysemu/kvm.h" 30 #include "sysemu/qtest.h" 31 #include "exec/exec-all.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/qdev-clock.h" 34 #include "semihosting/semihost.h" 35 #include "fpu_helper.h" 36 37 const char regnames[32][3] = { 38 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 39 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 40 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 41 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 42 }; 43 44 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) 45 { 46 if (is_fpu64) { 47 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n", 48 fpr->w[FP_ENDIAN_IDX], fpr->d, 49 (double)fpr->fd, 50 (double)fpr->fs[FP_ENDIAN_IDX], 51 (double)fpr->fs[!FP_ENDIAN_IDX]); 52 } else { 53 fpr_t tmp; 54 55 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; 56 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; 57 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n", 58 tmp.w[FP_ENDIAN_IDX], tmp.d, 59 (double)tmp.fd, 60 (double)tmp.fs[FP_ENDIAN_IDX], 61 (double)tmp.fs[!FP_ENDIAN_IDX]); 62 } 63 } 64 65 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) 66 { 67 int i; 68 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); 69 70 qemu_fprintf(f, 71 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", 72 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, 73 get_float_exception_flags(&env->active_fpu.fp_status)); 74 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { 75 qemu_fprintf(f, "%3s: ", fregnames[i]); 76 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); 77 } 78 } 79 80 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) 81 { 82 MIPSCPU *cpu = MIPS_CPU(cs); 83 CPUMIPSState *env = &cpu->env; 84 int i; 85 86 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx 87 " LO=0x" TARGET_FMT_lx " ds %04x " 88 TARGET_FMT_lx " " TARGET_FMT_ld "\n", 89 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], 90 env->hflags, env->btarget, env->bcond); 91 for (i = 0; i < 32; i++) { 92 if ((i & 3) == 0) { 93 qemu_fprintf(f, "GPR%02d:", i); 94 } 95 qemu_fprintf(f, " %s " TARGET_FMT_lx, 96 regnames[i], env->active_tc.gpr[i]); 97 if ((i & 3) == 3) { 98 qemu_fprintf(f, "\n"); 99 } 100 } 101 102 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" 103 TARGET_FMT_lx "\n", 104 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); 105 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" 106 PRIx64 "\n", 107 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); 108 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", 109 env->CP0_Config2, env->CP0_Config3); 110 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", 111 env->CP0_Config4, env->CP0_Config5); 112 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { 113 fpu_dump_state(env, f, flags); 114 } 115 } 116 117 void cpu_set_exception_base(int vp_index, target_ulong address) 118 { 119 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); 120 vp->env.exception_base = address; 121 } 122 123 static void mips_cpu_set_pc(CPUState *cs, vaddr value) 124 { 125 MIPSCPU *cpu = MIPS_CPU(cs); 126 127 mips_env_set_pc(&cpu->env, value); 128 } 129 130 static vaddr mips_cpu_get_pc(CPUState *cs) 131 { 132 MIPSCPU *cpu = MIPS_CPU(cs); 133 134 return cpu->env.active_tc.PC; 135 } 136 137 static bool mips_cpu_has_work(CPUState *cs) 138 { 139 MIPSCPU *cpu = MIPS_CPU(cs); 140 CPUMIPSState *env = &cpu->env; 141 bool has_work = false; 142 143 /* 144 * Prior to MIPS Release 6 it is implementation dependent if non-enabled 145 * interrupts wake-up the CPU, however most of the implementations only 146 * check for interrupts that can be taken. For pre-release 6 CPUs, 147 * check for CP0 Config7 'Wait IE ignore' bit. 148 */ 149 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 150 cpu_mips_hw_interrupts_pending(env)) { 151 if (cpu_mips_hw_interrupts_enabled(env) || 152 (env->CP0_Config7 & (1 << CP0C7_WII)) || 153 (env->insn_flags & ISA_MIPS_R6)) { 154 has_work = true; 155 } 156 } 157 158 /* MIPS-MT has the ability to halt the CPU. */ 159 if (ase_mt_available(env)) { 160 /* 161 * The QEMU model will issue an _WAKE request whenever the CPUs 162 * should be woken up. 163 */ 164 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 165 has_work = true; 166 } 167 168 if (!mips_vpe_active(env)) { 169 has_work = false; 170 } 171 } 172 /* MIPS Release 6 has the ability to halt the CPU. */ 173 if (env->CP0_Config5 & (1 << CP0C5_VP)) { 174 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 175 has_work = true; 176 } 177 if (!mips_vp_active(env)) { 178 has_work = false; 179 } 180 } 181 return has_work; 182 } 183 184 #include "cpu-defs.c.inc" 185 186 static void mips_cpu_reset_hold(Object *obj) 187 { 188 CPUState *cs = CPU(obj); 189 MIPSCPU *cpu = MIPS_CPU(cs); 190 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); 191 CPUMIPSState *env = &cpu->env; 192 193 if (mcc->parent_phases.hold) { 194 mcc->parent_phases.hold(obj); 195 } 196 197 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); 198 199 /* Reset registers to their default values */ 200 env->CP0_PRid = env->cpu_model->CP0_PRid; 201 env->CP0_Config0 = env->cpu_model->CP0_Config0; 202 #if TARGET_BIG_ENDIAN 203 env->CP0_Config0 |= (1 << CP0C0_BE); 204 #endif 205 env->CP0_Config1 = env->cpu_model->CP0_Config1; 206 env->CP0_Config2 = env->cpu_model->CP0_Config2; 207 env->CP0_Config3 = env->cpu_model->CP0_Config3; 208 env->CP0_Config4 = env->cpu_model->CP0_Config4; 209 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; 210 env->CP0_Config5 = env->cpu_model->CP0_Config5; 211 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; 212 env->CP0_Config6 = env->cpu_model->CP0_Config6; 213 env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; 214 env->CP0_Config7 = env->cpu_model->CP0_Config7; 215 env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; 216 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask 217 << env->cpu_model->CP0_LLAddr_shift; 218 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; 219 env->SYNCI_Step = env->cpu_model->SYNCI_Step; 220 env->CCRes = env->cpu_model->CCRes; 221 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; 222 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; 223 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; 224 env->current_tc = 0; 225 env->SEGBITS = env->cpu_model->SEGBITS; 226 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); 227 #if defined(TARGET_MIPS64) 228 if (env->cpu_model->insn_flags & ISA_MIPS3) { 229 env->SEGMask |= 3ULL << 62; 230 } 231 #endif 232 env->PABITS = env->cpu_model->PABITS; 233 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; 234 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; 235 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; 236 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; 237 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; 238 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; 239 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; 240 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; 241 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; 242 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; 243 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; 244 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; 245 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; 246 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; 247 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; 248 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; 249 env->msair = env->cpu_model->MSAIR; 250 env->insn_flags = env->cpu_model->insn_flags; 251 252 #if defined(CONFIG_USER_ONLY) 253 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); 254 # ifdef TARGET_MIPS64 255 /* Enable 64-bit register mode. */ 256 env->CP0_Status |= (1 << CP0St_PX); 257 # endif 258 # ifdef TARGET_ABI_MIPSN64 259 /* Enable 64-bit address mode. */ 260 env->CP0_Status |= (1 << CP0St_UX); 261 # endif 262 /* 263 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR 264 * hardware registers. 265 */ 266 env->CP0_HWREna |= 0x0000000F; 267 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 268 env->CP0_Status |= (1 << CP0St_CU1); 269 } 270 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { 271 env->CP0_Status |= (1 << CP0St_MX); 272 } 273 # if defined(TARGET_MIPS64) 274 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ 275 if ((env->CP0_Config1 & (1 << CP0C1_FP)) && 276 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { 277 env->CP0_Status |= (1 << CP0St_FR); 278 } 279 # endif 280 #else /* !CONFIG_USER_ONLY */ 281 if (env->hflags & MIPS_HFLAG_BMASK) { 282 /* 283 * If the exception was raised from a delay slot, 284 * come back to the jump. 285 */ 286 env->CP0_ErrorEPC = (env->active_tc.PC 287 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); 288 } else { 289 env->CP0_ErrorEPC = env->active_tc.PC; 290 } 291 env->active_tc.PC = env->exception_base; 292 env->CP0_Random = env->tlb->nb_tlb - 1; 293 env->tlb->tlb_in_use = env->tlb->nb_tlb; 294 env->CP0_Wired = 0; 295 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; 296 env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF); 297 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { 298 env->CP0_CMGCRBase = 0x1fbf8000 >> 4; 299 } 300 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 301 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; 302 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); 303 if (env->insn_flags & INSN_LOONGSON2F) { 304 /* Loongson-2F has those bits hardcoded to 1 */ 305 env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | 306 (1 << CP0St_UX); 307 } 308 309 /* 310 * Vectored interrupts not implemented, timer on int 7, 311 * no performance counters. 312 */ 313 env->CP0_IntCtl = 0xe0000000; 314 { 315 int i; 316 317 for (i = 0; i < 7; i++) { 318 env->CP0_WatchLo[i] = 0; 319 env->CP0_WatchHi[i] = 1 << CP0WH_M; 320 } 321 env->CP0_WatchLo[7] = 0; 322 env->CP0_WatchHi[7] = 0; 323 } 324 /* Count register increments in debug mode, EJTAG version 1 */ 325 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); 326 327 cpu_mips_store_count(env, 1); 328 329 if (ase_mt_available(env)) { 330 int i; 331 332 /* Only TC0 on VPE 0 starts as active. */ 333 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { 334 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; 335 env->tcs[i].CP0_TCHalt = 1; 336 } 337 env->active_tc.CP0_TCHalt = 1; 338 cs->halted = 1; 339 340 if (cs->cpu_index == 0) { 341 /* VPE0 starts up enabled. */ 342 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); 343 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); 344 345 /* TC0 starts up unhalted. */ 346 cs->halted = 0; 347 env->active_tc.CP0_TCHalt = 0; 348 env->tcs[0].CP0_TCHalt = 0; 349 /* With thread 0 active. */ 350 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); 351 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); 352 } 353 } 354 355 /* 356 * Configure default legacy segmentation control. We use this regardless of 357 * whether segmentation control is presented to the guest. 358 */ 359 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ 360 env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); 361 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ 362 env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; 363 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ 364 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 365 (2 << CP0SC_C); 366 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ 367 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 368 (3 << CP0SC_C)) << 16; 369 /* USeg (seg4 0x40000000..0x7FFFFFFF) */ 370 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 371 (1 << CP0SC_EU) | (2 << CP0SC_C); 372 /* USeg (seg5 0x00000000..0x3FFFFFFF) */ 373 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 374 (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; 375 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ 376 env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); 377 #endif /* !CONFIG_USER_ONLY */ 378 if ((env->insn_flags & ISA_MIPS_R6) && 379 (env->active_fpu.fcr0 & (1 << FCR0_F64))) { 380 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ 381 env->CP0_Status |= (1 << CP0St_FR); 382 } 383 384 if (env->insn_flags & ISA_MIPS_R6) { 385 /* PTW = 1 */ 386 env->CP0_PWSize = 0x40; 387 /* GDI = 12 */ 388 /* UDI = 12 */ 389 /* MDI = 12 */ 390 /* PRI = 12 */ 391 /* PTEI = 2 */ 392 env->CP0_PWField = 0x0C30C302; 393 } else { 394 /* GDI = 0 */ 395 /* UDI = 0 */ 396 /* MDI = 0 */ 397 /* PRI = 0 */ 398 /* PTEI = 2 */ 399 env->CP0_PWField = 0x02; 400 } 401 402 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { 403 /* microMIPS on reset when Config3.ISA is 3 */ 404 env->hflags |= MIPS_HFLAG_M16; 405 } 406 407 msa_reset(env); 408 409 compute_hflags(env); 410 restore_fp_status(env); 411 restore_pamask(env); 412 cs->exception_index = EXCP_NONE; 413 414 if (semihosting_get_argc()) { 415 /* UHI interface can be used to obtain argc and argv */ 416 env->active_tc.gpr[4] = -1; 417 } 418 419 #ifndef CONFIG_USER_ONLY 420 if (kvm_enabled()) { 421 kvm_mips_reset_vcpu(cpu); 422 } 423 #endif 424 } 425 426 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) 427 { 428 MIPSCPU *cpu = MIPS_CPU(s); 429 CPUMIPSState *env = &cpu->env; 430 431 if (!(env->insn_flags & ISA_NANOMIPS32)) { 432 #if TARGET_BIG_ENDIAN 433 info->print_insn = print_insn_big_mips; 434 #else 435 info->print_insn = print_insn_little_mips; 436 #endif 437 } else { 438 info->print_insn = print_insn_nanomips; 439 } 440 } 441 442 /* 443 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. 444 */ 445 #define CPU_FREQ_HZ_DEFAULT 200000000 446 447 static void mips_cp0_period_set(MIPSCPU *cpu) 448 { 449 CPUMIPSState *env = &cpu->env; 450 451 env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock, 452 env->cpu_model->CCRes); 453 assert(env->cp0_count_ns); 454 } 455 456 static void mips_cpu_realizefn(DeviceState *dev, Error **errp) 457 { 458 CPUState *cs = CPU(dev); 459 MIPSCPU *cpu = MIPS_CPU(dev); 460 CPUMIPSState *env = &cpu->env; 461 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); 462 Error *local_err = NULL; 463 464 if (!clock_get(cpu->clock)) { 465 #ifndef CONFIG_USER_ONLY 466 if (!qtest_enabled()) { 467 g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); 468 469 warn_report("CPU input clock is not connected to any output clock, " 470 "using default frequency of %s.", cpu_freq_str); 471 } 472 #endif 473 /* Initialize the frequency in case the clock remains unconnected. */ 474 clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); 475 } 476 mips_cp0_period_set(cpu); 477 478 cpu_exec_realizefn(cs, &local_err); 479 if (local_err != NULL) { 480 error_propagate(errp, local_err); 481 return; 482 } 483 484 env->exception_base = (int32_t)0xBFC00000; 485 486 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 487 mmu_init(env, env->cpu_model); 488 #endif 489 fpu_init(env, env->cpu_model); 490 mvp_init(env); 491 492 cpu_reset(cs); 493 qemu_init_vcpu(cs); 494 495 mcc->parent_realize(dev, errp); 496 } 497 498 static void mips_cpu_initfn(Object *obj) 499 { 500 MIPSCPU *cpu = MIPS_CPU(obj); 501 CPUMIPSState *env = &cpu->env; 502 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 503 504 cpu_set_cpustate_pointers(cpu); 505 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 506 env->cpu_model = mcc->cpu_def; 507 } 508 509 static char *mips_cpu_type_name(const char *cpu_model) 510 { 511 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); 512 } 513 514 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) 515 { 516 ObjectClass *oc; 517 char *typename; 518 519 typename = mips_cpu_type_name(cpu_model); 520 oc = object_class_by_name(typename); 521 g_free(typename); 522 return oc; 523 } 524 525 #ifndef CONFIG_USER_ONLY 526 #include "hw/core/sysemu-cpu-ops.h" 527 528 static const struct SysemuCPUOps mips_sysemu_ops = { 529 .get_phys_page_debug = mips_cpu_get_phys_page_debug, 530 .legacy_vmsd = &vmstate_mips_cpu, 531 }; 532 #endif 533 534 #ifdef CONFIG_TCG 535 #include "hw/core/tcg-cpu-ops.h" 536 /* 537 * NB: cannot be const, as some elements are changed for specific 538 * mips hardware (see hw/mips/jazz.c). 539 */ 540 static const struct TCGCPUOps mips_tcg_ops = { 541 .initialize = mips_tcg_init, 542 .synchronize_from_tb = mips_cpu_synchronize_from_tb, 543 .restore_state_to_opc = mips_restore_state_to_opc, 544 545 #if !defined(CONFIG_USER_ONLY) 546 .tlb_fill = mips_cpu_tlb_fill, 547 .cpu_exec_interrupt = mips_cpu_exec_interrupt, 548 .do_interrupt = mips_cpu_do_interrupt, 549 .do_transaction_failed = mips_cpu_do_transaction_failed, 550 .do_unaligned_access = mips_cpu_do_unaligned_access, 551 .io_recompile_replay_branch = mips_io_recompile_replay_branch, 552 #endif /* !CONFIG_USER_ONLY */ 553 }; 554 #endif /* CONFIG_TCG */ 555 556 static void mips_cpu_class_init(ObjectClass *c, void *data) 557 { 558 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); 559 CPUClass *cc = CPU_CLASS(c); 560 DeviceClass *dc = DEVICE_CLASS(c); 561 ResettableClass *rc = RESETTABLE_CLASS(c); 562 563 device_class_set_parent_realize(dc, mips_cpu_realizefn, 564 &mcc->parent_realize); 565 resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, 566 &mcc->parent_phases); 567 568 cc->class_by_name = mips_cpu_class_by_name; 569 cc->has_work = mips_cpu_has_work; 570 cc->dump_state = mips_cpu_dump_state; 571 cc->set_pc = mips_cpu_set_pc; 572 cc->get_pc = mips_cpu_get_pc; 573 cc->gdb_read_register = mips_cpu_gdb_read_register; 574 cc->gdb_write_register = mips_cpu_gdb_write_register; 575 #ifndef CONFIG_USER_ONLY 576 cc->sysemu_ops = &mips_sysemu_ops; 577 #endif 578 cc->disas_set_info = mips_cpu_disas_set_info; 579 cc->gdb_num_core_regs = 73; 580 cc->gdb_stop_before_watchpoint = true; 581 #ifdef CONFIG_TCG 582 cc->tcg_ops = &mips_tcg_ops; 583 #endif /* CONFIG_TCG */ 584 } 585 586 static const TypeInfo mips_cpu_type_info = { 587 .name = TYPE_MIPS_CPU, 588 .parent = TYPE_CPU, 589 .instance_size = sizeof(MIPSCPU), 590 .instance_init = mips_cpu_initfn, 591 .abstract = true, 592 .class_size = sizeof(MIPSCPUClass), 593 .class_init = mips_cpu_class_init, 594 }; 595 596 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) 597 { 598 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); 599 mcc->cpu_def = data; 600 } 601 602 static void mips_register_cpudef_type(const struct mips_def_t *def) 603 { 604 char *typename = mips_cpu_type_name(def->name); 605 TypeInfo ti = { 606 .name = typename, 607 .parent = TYPE_MIPS_CPU, 608 .class_init = mips_cpu_cpudef_class_init, 609 .class_data = (void *)def, 610 }; 611 612 type_register(&ti); 613 g_free(typename); 614 } 615 616 static void mips_cpu_register_types(void) 617 { 618 int i; 619 620 type_register_static(&mips_cpu_type_info); 621 for (i = 0; i < mips_defs_number; i++) { 622 mips_register_cpudef_type(&mips_defs[i]); 623 } 624 } 625 626 type_init(mips_cpu_register_types) 627 628 /* Could be used by generic CPU object */ 629 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) 630 { 631 DeviceState *cpu; 632 633 cpu = DEVICE(object_new(cpu_type)); 634 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 635 qdev_realize(cpu, NULL, &error_abort); 636 637 return MIPS_CPU(cpu); 638 } 639 640 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) 641 { 642 return (env->cpu_model->insn_flags & isa_mask) != 0; 643 } 644 645 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) 646 { 647 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 648 return (mcc->cpu_def->insn_flags & isa) != 0; 649 } 650 651 bool cpu_type_supports_cps_smp(const char *cpu_type) 652 { 653 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 654 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; 655 } 656