1 /* 2 * QEMU MIPS CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "internal.h" 28 #include "kvm_mips.h" 29 #include "qemu/module.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/qtest.h" 32 #include "exec/exec-all.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-clock.h" 35 #include "semihosting/semihost.h" 36 #include "fpu_helper.h" 37 38 const char regnames[32][3] = { 39 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 40 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 41 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 42 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 43 }; 44 45 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) 46 { 47 if (is_fpu64) { 48 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n", 49 fpr->w[FP_ENDIAN_IDX], fpr->d, 50 (double)fpr->fd, 51 (double)fpr->fs[FP_ENDIAN_IDX], 52 (double)fpr->fs[!FP_ENDIAN_IDX]); 53 } else { 54 fpr_t tmp; 55 56 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; 57 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; 58 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n", 59 tmp.w[FP_ENDIAN_IDX], tmp.d, 60 (double)tmp.fd, 61 (double)tmp.fs[FP_ENDIAN_IDX], 62 (double)tmp.fs[!FP_ENDIAN_IDX]); 63 } 64 } 65 66 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) 67 { 68 int i; 69 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); 70 71 qemu_fprintf(f, 72 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", 73 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, 74 get_float_exception_flags(&env->active_fpu.fp_status)); 75 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { 76 qemu_fprintf(f, "%3s: ", fregnames[i]); 77 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); 78 } 79 } 80 81 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) 82 { 83 CPUMIPSState *env = cpu_env(cs); 84 int i; 85 86 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx 87 " LO=0x" TARGET_FMT_lx " ds %04x " 88 TARGET_FMT_lx " " TARGET_FMT_ld "\n", 89 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], 90 env->hflags, env->btarget, env->bcond); 91 for (i = 0; i < 32; i++) { 92 if ((i & 3) == 0) { 93 qemu_fprintf(f, "GPR%02d:", i); 94 } 95 qemu_fprintf(f, " %s " TARGET_FMT_lx, 96 regnames[i], env->active_tc.gpr[i]); 97 if ((i & 3) == 3) { 98 qemu_fprintf(f, "\n"); 99 } 100 } 101 102 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" 103 TARGET_FMT_lx "\n", 104 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); 105 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" 106 PRIx64 "\n", 107 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); 108 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", 109 env->CP0_Config2, env->CP0_Config3); 110 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", 111 env->CP0_Config4, env->CP0_Config5); 112 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { 113 fpu_dump_state(env, f, flags); 114 } 115 } 116 117 void cpu_set_exception_base(int vp_index, target_ulong address) 118 { 119 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); 120 vp->env.exception_base = address; 121 } 122 123 static void mips_cpu_set_pc(CPUState *cs, vaddr value) 124 { 125 mips_env_set_pc(cpu_env(cs), value); 126 } 127 128 static vaddr mips_cpu_get_pc(CPUState *cs) 129 { 130 MIPSCPU *cpu = MIPS_CPU(cs); 131 132 return cpu->env.active_tc.PC; 133 } 134 135 static bool mips_cpu_has_work(CPUState *cs) 136 { 137 CPUMIPSState *env = cpu_env(cs); 138 bool has_work = false; 139 140 /* 141 * Prior to MIPS Release 6 it is implementation dependent if non-enabled 142 * interrupts wake-up the CPU, however most of the implementations only 143 * check for interrupts that can be taken. For pre-release 6 CPUs, 144 * check for CP0 Config7 'Wait IE ignore' bit. 145 */ 146 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 147 cpu_mips_hw_interrupts_pending(env)) { 148 if (cpu_mips_hw_interrupts_enabled(env) || 149 (env->CP0_Config7 & (1 << CP0C7_WII)) || 150 (env->insn_flags & ISA_MIPS_R6)) { 151 has_work = true; 152 } 153 } 154 155 /* MIPS-MT has the ability to halt the CPU. */ 156 if (ase_mt_available(env)) { 157 /* 158 * The QEMU model will issue an _WAKE request whenever the CPUs 159 * should be woken up. 160 */ 161 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 162 has_work = true; 163 } 164 165 if (!mips_vpe_active(env)) { 166 has_work = false; 167 } 168 } 169 /* MIPS Release 6 has the ability to halt the CPU. */ 170 if (env->CP0_Config5 & (1 << CP0C5_VP)) { 171 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 172 has_work = true; 173 } 174 if (!mips_vp_active(env)) { 175 has_work = false; 176 } 177 } 178 return has_work; 179 } 180 181 static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) 182 { 183 return mips_env_mmu_index(cpu_env(cs)); 184 } 185 186 #include "cpu-defs.c.inc" 187 188 static void mips_cpu_reset_hold(Object *obj, ResetType type) 189 { 190 CPUState *cs = CPU(obj); 191 MIPSCPU *cpu = MIPS_CPU(cs); 192 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 193 CPUMIPSState *env = &cpu->env; 194 195 if (mcc->parent_phases.hold) { 196 mcc->parent_phases.hold(obj, type); 197 } 198 199 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); 200 201 /* Reset registers to their default values */ 202 env->CP0_PRid = env->cpu_model->CP0_PRid; 203 env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, 204 CP0C0_BE, 1, cpu->is_big_endian); 205 env->CP0_Config1 = env->cpu_model->CP0_Config1; 206 env->CP0_Config2 = env->cpu_model->CP0_Config2; 207 env->CP0_Config3 = env->cpu_model->CP0_Config3; 208 env->CP0_Config4 = env->cpu_model->CP0_Config4; 209 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; 210 env->CP0_Config5 = env->cpu_model->CP0_Config5; 211 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; 212 env->CP0_Config6 = env->cpu_model->CP0_Config6; 213 env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; 214 env->CP0_Config7 = env->cpu_model->CP0_Config7; 215 env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; 216 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask 217 << env->cpu_model->CP0_LLAddr_shift; 218 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; 219 env->SYNCI_Step = env->cpu_model->SYNCI_Step; 220 env->CCRes = env->cpu_model->CCRes; 221 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; 222 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; 223 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; 224 env->current_tc = 0; 225 env->SEGBITS = env->cpu_model->SEGBITS; 226 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); 227 #if defined(TARGET_MIPS64) 228 if (env->cpu_model->insn_flags & ISA_MIPS3) { 229 env->SEGMask |= 3ULL << 62; 230 } 231 #endif 232 env->PABITS = env->cpu_model->PABITS; 233 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; 234 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; 235 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; 236 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; 237 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; 238 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; 239 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; 240 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; 241 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; 242 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; 243 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; 244 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; 245 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; 246 env->lcsr_cpucfg1 = env->cpu_model->lcsr_cpucfg1; 247 env->lcsr_cpucfg2 = env->cpu_model->lcsr_cpucfg2; 248 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; 249 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; 250 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; 251 env->msair = env->cpu_model->MSAIR; 252 env->insn_flags = env->cpu_model->insn_flags; 253 254 #if defined(CONFIG_USER_ONLY) 255 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); 256 # ifdef TARGET_MIPS64 257 /* Enable 64-bit register mode. */ 258 env->CP0_Status |= (1 << CP0St_PX); 259 # endif 260 # ifdef TARGET_ABI_MIPSN64 261 /* Enable 64-bit address mode. */ 262 env->CP0_Status |= (1 << CP0St_UX); 263 # endif 264 /* 265 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR 266 * hardware registers. 267 */ 268 env->CP0_HWREna |= 0x0000000F; 269 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 270 env->CP0_Status |= (1 << CP0St_CU1); 271 } 272 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { 273 env->CP0_Status |= (1 << CP0St_MX); 274 } 275 # if defined(TARGET_MIPS64) 276 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ 277 if ((env->CP0_Config1 & (1 << CP0C1_FP)) && 278 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { 279 env->CP0_Status |= (1 << CP0St_FR); 280 } 281 # endif 282 #else /* !CONFIG_USER_ONLY */ 283 if (env->hflags & MIPS_HFLAG_BMASK) { 284 /* 285 * If the exception was raised from a delay slot, 286 * come back to the jump. 287 */ 288 env->CP0_ErrorEPC = (env->active_tc.PC 289 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); 290 } else { 291 env->CP0_ErrorEPC = env->active_tc.PC; 292 } 293 env->active_tc.PC = env->exception_base; 294 env->CP0_Random = env->tlb->nb_tlb - 1; 295 env->tlb->tlb_in_use = env->tlb->nb_tlb; 296 env->CP0_Wired = 0; 297 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; 298 env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF); 299 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { 300 env->CP0_CMGCRBase = 0x1fbf8000 >> 4; 301 } 302 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 303 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; 304 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); 305 if (env->insn_flags & INSN_LOONGSON2F) { 306 /* Loongson-2F has those bits hardcoded to 1 */ 307 env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | 308 (1 << CP0St_UX); 309 } 310 311 /* 312 * Vectored interrupts not implemented, timer on int 7, 313 * no performance counters. 314 */ 315 env->CP0_IntCtl = 0xe0000000; 316 { 317 int i; 318 319 for (i = 0; i < 7; i++) { 320 env->CP0_WatchLo[i] = 0; 321 env->CP0_WatchHi[i] = 1 << CP0WH_M; 322 } 323 env->CP0_WatchLo[7] = 0; 324 env->CP0_WatchHi[7] = 0; 325 } 326 /* Count register increments in debug mode, EJTAG version 1 */ 327 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); 328 329 cpu_mips_store_count(env, 1); 330 331 if (ase_mt_available(env)) { 332 int i; 333 334 /* Only TC0 on VPE 0 starts as active. */ 335 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { 336 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; 337 env->tcs[i].CP0_TCHalt = 1; 338 } 339 env->active_tc.CP0_TCHalt = 1; 340 cs->halted = 1; 341 342 if (cs->cpu_index == 0) { 343 /* VPE0 starts up enabled. */ 344 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); 345 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); 346 347 /* TC0 starts up unhalted. */ 348 cs->halted = 0; 349 env->active_tc.CP0_TCHalt = 0; 350 env->tcs[0].CP0_TCHalt = 0; 351 /* With thread 0 active. */ 352 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); 353 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); 354 } 355 } 356 357 /* 358 * Configure default legacy segmentation control. We use this regardless of 359 * whether segmentation control is presented to the guest. 360 */ 361 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ 362 env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); 363 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ 364 env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; 365 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ 366 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 367 (2 << CP0SC_C); 368 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ 369 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 370 (3 << CP0SC_C)) << 16; 371 /* USeg (seg4 0x40000000..0x7FFFFFFF) */ 372 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 373 (1 << CP0SC_EU) | (2 << CP0SC_C); 374 /* USeg (seg5 0x00000000..0x3FFFFFFF) */ 375 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 376 (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; 377 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ 378 env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); 379 #endif /* !CONFIG_USER_ONLY */ 380 if ((env->insn_flags & ISA_MIPS_R6) && 381 (env->active_fpu.fcr0 & (1 << FCR0_F64))) { 382 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ 383 env->CP0_Status |= (1 << CP0St_FR); 384 } 385 386 if (env->insn_flags & ISA_MIPS_R6) { 387 /* PTW = 1 */ 388 env->CP0_PWSize = 0x40; 389 /* GDI = 12 */ 390 /* UDI = 12 */ 391 /* MDI = 12 */ 392 /* PRI = 12 */ 393 /* PTEI = 2 */ 394 env->CP0_PWField = 0x0C30C302; 395 } else { 396 /* GDI = 0 */ 397 /* UDI = 0 */ 398 /* MDI = 0 */ 399 /* PRI = 0 */ 400 /* PTEI = 2 */ 401 env->CP0_PWField = 0x02; 402 } 403 404 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { 405 /* microMIPS on reset when Config3.ISA is 3 */ 406 env->hflags |= MIPS_HFLAG_M16; 407 } 408 409 msa_reset(env); 410 411 compute_hflags(env); 412 restore_fp_status(env); 413 restore_pamask(env); 414 cs->exception_index = EXCP_NONE; 415 416 if (semihosting_get_argc()) { 417 /* UHI interface can be used to obtain argc and argv */ 418 env->active_tc.gpr[4] = -1; 419 } 420 421 #ifndef CONFIG_USER_ONLY 422 if (kvm_enabled()) { 423 kvm_mips_reset_vcpu(cpu); 424 } 425 #endif 426 } 427 428 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) 429 { 430 if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { 431 #if TARGET_BIG_ENDIAN 432 info->print_insn = print_insn_big_mips; 433 #else 434 info->print_insn = print_insn_little_mips; 435 #endif 436 } else { 437 info->print_insn = print_insn_nanomips; 438 } 439 } 440 441 /* 442 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. 443 */ 444 #define CPU_FREQ_HZ_DEFAULT 200000000 445 446 static void mips_cp0_period_set(MIPSCPU *cpu) 447 { 448 CPUMIPSState *env = &cpu->env; 449 450 clock_set_mul_div(cpu->count_div, env->cpu_model->CCRes, 1); 451 clock_set_source(cpu->count_div, cpu->clock); 452 clock_set_source(env->count_clock, cpu->count_div); 453 } 454 455 static void mips_cpu_realizefn(DeviceState *dev, Error **errp) 456 { 457 CPUState *cs = CPU(dev); 458 MIPSCPU *cpu = MIPS_CPU(dev); 459 CPUMIPSState *env = &cpu->env; 460 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); 461 Error *local_err = NULL; 462 463 if (!clock_get(cpu->clock)) { 464 #ifndef CONFIG_USER_ONLY 465 if (!qtest_enabled()) { 466 g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); 467 468 warn_report("CPU input clock is not connected to any output clock, " 469 "using default frequency of %s.", cpu_freq_str); 470 } 471 #endif 472 /* Initialize the frequency in case the clock remains unconnected. */ 473 clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); 474 } 475 mips_cp0_period_set(cpu); 476 477 cpu_exec_realizefn(cs, &local_err); 478 if (local_err != NULL) { 479 error_propagate(errp, local_err); 480 return; 481 } 482 483 env->exception_base = (int32_t)0xBFC00000; 484 485 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 486 mmu_init(env, env->cpu_model); 487 #endif 488 fpu_init(env, env->cpu_model); 489 mvp_init(env); 490 491 cpu_reset(cs); 492 qemu_init_vcpu(cs); 493 494 mcc->parent_realize(dev, errp); 495 } 496 497 static void mips_cpu_initfn(Object *obj) 498 { 499 MIPSCPU *cpu = MIPS_CPU(obj); 500 CPUMIPSState *env = &cpu->env; 501 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 502 503 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 504 cpu->count_div = clock_new(OBJECT(obj), "clk-div-count"); 505 env->count_clock = clock_new(OBJECT(obj), "clk-count"); 506 env->cpu_model = mcc->cpu_def; 507 #ifndef CONFIG_USER_ONLY 508 if (mcc->cpu_def->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP)) { 509 memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL, 510 env, "iocsr", UINT64_MAX); 511 address_space_init(&env->iocsr.as, 512 &env->iocsr.mr, "IOCSR"); 513 } 514 #endif 515 } 516 517 static char *mips_cpu_type_name(const char *cpu_model) 518 { 519 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); 520 } 521 522 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) 523 { 524 ObjectClass *oc; 525 char *typename; 526 527 typename = mips_cpu_type_name(cpu_model); 528 oc = object_class_by_name(typename); 529 g_free(typename); 530 return oc; 531 } 532 533 #ifndef CONFIG_USER_ONLY 534 #include "hw/core/sysemu-cpu-ops.h" 535 536 static const struct SysemuCPUOps mips_sysemu_ops = { 537 .get_phys_page_debug = mips_cpu_get_phys_page_debug, 538 .legacy_vmsd = &vmstate_mips_cpu, 539 }; 540 #endif 541 542 static Property mips_cpu_properties[] = { 543 DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), 544 DEFINE_PROP_END_OF_LIST(), 545 }; 546 547 #ifdef CONFIG_TCG 548 #include "hw/core/tcg-cpu-ops.h" 549 /* 550 * NB: cannot be const, as some elements are changed for specific 551 * mips hardware (see hw/mips/jazz.c). 552 */ 553 static const TCGCPUOps mips_tcg_ops = { 554 .initialize = mips_tcg_init, 555 .synchronize_from_tb = mips_cpu_synchronize_from_tb, 556 .restore_state_to_opc = mips_restore_state_to_opc, 557 558 #if !defined(CONFIG_USER_ONLY) 559 .tlb_fill = mips_cpu_tlb_fill, 560 .cpu_exec_interrupt = mips_cpu_exec_interrupt, 561 .cpu_exec_halt = mips_cpu_has_work, 562 .do_interrupt = mips_cpu_do_interrupt, 563 .do_transaction_failed = mips_cpu_do_transaction_failed, 564 .do_unaligned_access = mips_cpu_do_unaligned_access, 565 .io_recompile_replay_branch = mips_io_recompile_replay_branch, 566 #endif /* !CONFIG_USER_ONLY */ 567 }; 568 #endif /* CONFIG_TCG */ 569 570 static void mips_cpu_class_init(ObjectClass *c, void *data) 571 { 572 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); 573 CPUClass *cc = CPU_CLASS(c); 574 DeviceClass *dc = DEVICE_CLASS(c); 575 ResettableClass *rc = RESETTABLE_CLASS(c); 576 577 device_class_set_props(dc, mips_cpu_properties); 578 device_class_set_parent_realize(dc, mips_cpu_realizefn, 579 &mcc->parent_realize); 580 resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, 581 &mcc->parent_phases); 582 583 cc->class_by_name = mips_cpu_class_by_name; 584 cc->has_work = mips_cpu_has_work; 585 cc->mmu_index = mips_cpu_mmu_index; 586 cc->dump_state = mips_cpu_dump_state; 587 cc->set_pc = mips_cpu_set_pc; 588 cc->get_pc = mips_cpu_get_pc; 589 cc->gdb_read_register = mips_cpu_gdb_read_register; 590 cc->gdb_write_register = mips_cpu_gdb_write_register; 591 #ifndef CONFIG_USER_ONLY 592 cc->sysemu_ops = &mips_sysemu_ops; 593 #endif 594 cc->disas_set_info = mips_cpu_disas_set_info; 595 cc->gdb_num_core_regs = 73; 596 cc->gdb_stop_before_watchpoint = true; 597 #ifdef CONFIG_TCG 598 cc->tcg_ops = &mips_tcg_ops; 599 #endif /* CONFIG_TCG */ 600 } 601 602 static const TypeInfo mips_cpu_type_info = { 603 .name = TYPE_MIPS_CPU, 604 .parent = TYPE_CPU, 605 .instance_size = sizeof(MIPSCPU), 606 .instance_align = __alignof(MIPSCPU), 607 .instance_init = mips_cpu_initfn, 608 .abstract = true, 609 .class_size = sizeof(MIPSCPUClass), 610 .class_init = mips_cpu_class_init, 611 }; 612 613 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) 614 { 615 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); 616 mcc->cpu_def = data; 617 } 618 619 static void mips_register_cpudef_type(const struct mips_def_t *def) 620 { 621 char *typename = mips_cpu_type_name(def->name); 622 TypeInfo ti = { 623 .name = typename, 624 .parent = TYPE_MIPS_CPU, 625 .class_init = mips_cpu_cpudef_class_init, 626 .class_data = (void *)def, 627 }; 628 629 type_register(&ti); 630 g_free(typename); 631 } 632 633 static void mips_cpu_register_types(void) 634 { 635 int i; 636 637 type_register_static(&mips_cpu_type_info); 638 for (i = 0; i < mips_defs_number; i++) { 639 mips_register_cpudef_type(&mips_defs[i]); 640 } 641 } 642 643 type_init(mips_cpu_register_types) 644 645 /* Could be used by generic CPU object */ 646 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, 647 bool is_big_endian) 648 { 649 DeviceState *cpu; 650 651 cpu = DEVICE(object_new(cpu_type)); 652 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 653 object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian, 654 &error_abort); 655 qdev_realize(cpu, NULL, &error_abort); 656 657 return MIPS_CPU(cpu); 658 } 659 660 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) 661 { 662 return (env->cpu_model->insn_flags & isa_mask) != 0; 663 } 664 665 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) 666 { 667 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 668 return (mcc->cpu_def->insn_flags & isa) != 0; 669 } 670 671 bool cpu_type_supports_cps_smp(const char *cpu_type) 672 { 673 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 674 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; 675 } 676