1*fcf5ef2aSThomas Huth /* 2*fcf5ef2aSThomas Huth * QEMU MIPS CPU 3*fcf5ef2aSThomas Huth * 4*fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 5*fcf5ef2aSThomas Huth * 6*fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7*fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8*fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9*fcf5ef2aSThomas Huth * version 2.1 of the License, or (at your option) any later version. 10*fcf5ef2aSThomas Huth * 11*fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12*fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14*fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15*fcf5ef2aSThomas Huth * 16*fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17*fcf5ef2aSThomas Huth * License along with this library; if not, see 18*fcf5ef2aSThomas Huth * <http://www.gnu.org/licenses/lgpl-2.1.html> 19*fcf5ef2aSThomas Huth */ 20*fcf5ef2aSThomas Huth #ifndef QEMU_MIPS_CPU_QOM_H 21*fcf5ef2aSThomas Huth #define QEMU_MIPS_CPU_QOM_H 22*fcf5ef2aSThomas Huth 23*fcf5ef2aSThomas Huth #include "qom/cpu.h" 24*fcf5ef2aSThomas Huth 25*fcf5ef2aSThomas Huth #ifdef TARGET_MIPS64 26*fcf5ef2aSThomas Huth #define TYPE_MIPS_CPU "mips64-cpu" 27*fcf5ef2aSThomas Huth #else 28*fcf5ef2aSThomas Huth #define TYPE_MIPS_CPU "mips-cpu" 29*fcf5ef2aSThomas Huth #endif 30*fcf5ef2aSThomas Huth 31*fcf5ef2aSThomas Huth #define MIPS_CPU_CLASS(klass) \ 32*fcf5ef2aSThomas Huth OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU) 33*fcf5ef2aSThomas Huth #define MIPS_CPU(obj) \ 34*fcf5ef2aSThomas Huth OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU) 35*fcf5ef2aSThomas Huth #define MIPS_CPU_GET_CLASS(obj) \ 36*fcf5ef2aSThomas Huth OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU) 37*fcf5ef2aSThomas Huth 38*fcf5ef2aSThomas Huth /** 39*fcf5ef2aSThomas Huth * MIPSCPUClass: 40*fcf5ef2aSThomas Huth * @parent_realize: The parent class' realize handler. 41*fcf5ef2aSThomas Huth * @parent_reset: The parent class' reset handler. 42*fcf5ef2aSThomas Huth * 43*fcf5ef2aSThomas Huth * A MIPS CPU model. 44*fcf5ef2aSThomas Huth */ 45*fcf5ef2aSThomas Huth typedef struct MIPSCPUClass { 46*fcf5ef2aSThomas Huth /*< private >*/ 47*fcf5ef2aSThomas Huth CPUClass parent_class; 48*fcf5ef2aSThomas Huth /*< public >*/ 49*fcf5ef2aSThomas Huth 50*fcf5ef2aSThomas Huth DeviceRealize parent_realize; 51*fcf5ef2aSThomas Huth void (*parent_reset)(CPUState *cpu); 52*fcf5ef2aSThomas Huth } MIPSCPUClass; 53*fcf5ef2aSThomas Huth 54*fcf5ef2aSThomas Huth typedef struct MIPSCPU MIPSCPU; 55*fcf5ef2aSThomas Huth 56*fcf5ef2aSThomas Huth #endif 57