1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * QEMU MIPS CPU 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9fcf5ef2aSThomas Huth * version 2.1 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see 18fcf5ef2aSThomas Huth * <http://www.gnu.org/licenses/lgpl-2.1.html> 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth #ifndef QEMU_MIPS_CPU_QOM_H 21fcf5ef2aSThomas Huth #define QEMU_MIPS_CPU_QOM_H 22fcf5ef2aSThomas Huth 232e5b09fdSMarkus Armbruster #include "hw/core/cpu.h" 24db1015e9SEduardo Habkost #include "qom/object.h" 25fcf5ef2aSThomas Huth 26fcf5ef2aSThomas Huth #ifdef TARGET_MIPS64 27fcf5ef2aSThomas Huth #define TYPE_MIPS_CPU "mips64-cpu" 28fcf5ef2aSThomas Huth #else 29fcf5ef2aSThomas Huth #define TYPE_MIPS_CPU "mips-cpu" 30fcf5ef2aSThomas Huth #endif 31fcf5ef2aSThomas Huth 32*9295b1aaSPhilippe Mathieu-Daudé OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) 33fcf5ef2aSThomas Huth 34fcf5ef2aSThomas Huth /** 35fcf5ef2aSThomas Huth * MIPSCPUClass: 36fcf5ef2aSThomas Huth * @parent_realize: The parent class' realize handler. 37fcf5ef2aSThomas Huth * @parent_reset: The parent class' reset handler. 38fcf5ef2aSThomas Huth * 39fcf5ef2aSThomas Huth * A MIPS CPU model. 40fcf5ef2aSThomas Huth */ 41db1015e9SEduardo Habkost struct MIPSCPUClass { 42fcf5ef2aSThomas Huth /*< private >*/ 43fcf5ef2aSThomas Huth CPUClass parent_class; 44fcf5ef2aSThomas Huth /*< public >*/ 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth DeviceRealize parent_realize; 47781c67caSPeter Maydell DeviceReset parent_reset; 4841da212cSIgor Mammedov const struct mips_def_t *cpu_def; 493803b6b4SRichard Henderson 503803b6b4SRichard Henderson /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ 513803b6b4SRichard Henderson bool no_data_aborts; 52db1015e9SEduardo Habkost }; 53fcf5ef2aSThomas Huth 54fcf5ef2aSThomas Huth 55fcf5ef2aSThomas Huth #endif 56