xref: /openbmc/qemu/target/microblaze/op_helper.c (revision dc5bd18f) 
1 /*
2  *  Microblaze helper routines.
3  *
4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/host-utils.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "fpu/softfloat.h"
28 
29 #define D(x)
30 
31 #if !defined(CONFIG_USER_ONLY)
32 
33 /* Try to fill the TLB and return an exception if error. If retaddr is
34  * NULL, it means that the function was called in C code (i.e. not
35  * from generated code or from helper.c)
36  */
37 void tlb_fill(CPUState *cs, target_ulong addr, int size,
38               MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
39 {
40     int ret;
41 
42     ret = mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
43     if (unlikely(ret)) {
44         /* now we have a real cpu fault */
45         cpu_loop_exit_restore(cs, retaddr);
46     }
47 }
48 #endif
49 
50 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
51 {
52     int test = ctrl & STREAM_TEST;
53     int atomic = ctrl & STREAM_ATOMIC;
54     int control = ctrl & STREAM_CONTROL;
55     int nonblock = ctrl & STREAM_NONBLOCK;
56     int exception = ctrl & STREAM_EXCEPTION;
57 
58     qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
59              id, data,
60              test ? "t" : "",
61              nonblock ? "n" : "",
62              exception ? "e" : "",
63              control ? "c" : "",
64              atomic ? "a" : "");
65 }
66 
67 uint32_t helper_get(uint32_t id, uint32_t ctrl)
68 {
69     int test = ctrl & STREAM_TEST;
70     int atomic = ctrl & STREAM_ATOMIC;
71     int control = ctrl & STREAM_CONTROL;
72     int nonblock = ctrl & STREAM_NONBLOCK;
73     int exception = ctrl & STREAM_EXCEPTION;
74 
75     qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
76              id,
77              test ? "t" : "",
78              nonblock ? "n" : "",
79              exception ? "e" : "",
80              control ? "c" : "",
81              atomic ? "a" : "");
82     return 0xdead0000 | id;
83 }
84 
85 void helper_raise_exception(CPUMBState *env, uint32_t index)
86 {
87     CPUState *cs = CPU(mb_env_get_cpu(env));
88 
89     cs->exception_index = index;
90     cpu_loop_exit(cs);
91 }
92 
93 void helper_debug(CPUMBState *env)
94 {
95     int i;
96 
97     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
98     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
99              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
100              env->debug, env->imm, env->iflags);
101     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
102              env->btaken, env->btarget,
103              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
104              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
105              (env->sregs[SR_MSR] & MSR_EIP),
106              (env->sregs[SR_MSR] & MSR_IE));
107     for (i = 0; i < 32; i++) {
108         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
109         if ((i + 1) % 4 == 0)
110             qemu_log("\n");
111     }
112     qemu_log("\n\n");
113 }
114 
115 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
116 {
117     uint32_t cout = 0;
118 
119     if ((b == ~0) && cin)
120         cout = 1;
121     else if ((~0 - a) < (b + cin))
122         cout = 1;
123     return cout;
124 }
125 
126 uint32_t helper_cmp(uint32_t a, uint32_t b)
127 {
128     uint32_t t;
129 
130     t = b + ~a + 1;
131     if ((b & 0x80000000) ^ (a & 0x80000000))
132         t = (t & 0x7fffffff) | (b & 0x80000000);
133     return t;
134 }
135 
136 uint32_t helper_cmpu(uint32_t a, uint32_t b)
137 {
138     uint32_t t;
139 
140     t = b + ~a + 1;
141     if ((b & 0x80000000) ^ (a & 0x80000000))
142         t = (t & 0x7fffffff) | (a & 0x80000000);
143     return t;
144 }
145 
146 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
147 {
148     return compute_carry(a, b, cf);
149 }
150 
151 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
152 {
153     if (b == 0) {
154         env->sregs[SR_MSR] |= MSR_DZ;
155 
156         if ((env->sregs[SR_MSR] & MSR_EE)
157             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
158             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
159             helper_raise_exception(env, EXCP_HW_EXCP);
160         }
161         return 0;
162     }
163     env->sregs[SR_MSR] &= ~MSR_DZ;
164     return 1;
165 }
166 
167 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
168 {
169     if (!div_prepare(env, a, b)) {
170         return 0;
171     }
172     return (int32_t)a / (int32_t)b;
173 }
174 
175 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
176 {
177     if (!div_prepare(env, a, b)) {
178         return 0;
179     }
180     return a / b;
181 }
182 
183 /* raise FPU exception.  */
184 static void raise_fpu_exception(CPUMBState *env)
185 {
186     env->sregs[SR_ESR] = ESR_EC_FPU;
187     helper_raise_exception(env, EXCP_HW_EXCP);
188 }
189 
190 static void update_fpu_flags(CPUMBState *env, int flags)
191 {
192     int raise = 0;
193 
194     if (flags & float_flag_invalid) {
195         env->sregs[SR_FSR] |= FSR_IO;
196         raise = 1;
197     }
198     if (flags & float_flag_divbyzero) {
199         env->sregs[SR_FSR] |= FSR_DZ;
200         raise = 1;
201     }
202     if (flags & float_flag_overflow) {
203         env->sregs[SR_FSR] |= FSR_OF;
204         raise = 1;
205     }
206     if (flags & float_flag_underflow) {
207         env->sregs[SR_FSR] |= FSR_UF;
208         raise = 1;
209     }
210     if (raise
211         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
212         && (env->sregs[SR_MSR] & MSR_EE)) {
213         raise_fpu_exception(env);
214     }
215 }
216 
217 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
218 {
219     CPU_FloatU fd, fa, fb;
220     int flags;
221 
222     set_float_exception_flags(0, &env->fp_status);
223     fa.l = a;
224     fb.l = b;
225     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
226 
227     flags = get_float_exception_flags(&env->fp_status);
228     update_fpu_flags(env, flags);
229     return fd.l;
230 }
231 
232 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
233 {
234     CPU_FloatU fd, fa, fb;
235     int flags;
236 
237     set_float_exception_flags(0, &env->fp_status);
238     fa.l = a;
239     fb.l = b;
240     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
241     flags = get_float_exception_flags(&env->fp_status);
242     update_fpu_flags(env, flags);
243     return fd.l;
244 }
245 
246 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
247 {
248     CPU_FloatU fd, fa, fb;
249     int flags;
250 
251     set_float_exception_flags(0, &env->fp_status);
252     fa.l = a;
253     fb.l = b;
254     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
255     flags = get_float_exception_flags(&env->fp_status);
256     update_fpu_flags(env, flags);
257 
258     return fd.l;
259 }
260 
261 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
262 {
263     CPU_FloatU fd, fa, fb;
264     int flags;
265 
266     set_float_exception_flags(0, &env->fp_status);
267     fa.l = a;
268     fb.l = b;
269     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
270     flags = get_float_exception_flags(&env->fp_status);
271     update_fpu_flags(env, flags);
272 
273     return fd.l;
274 }
275 
276 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
277 {
278     CPU_FloatU fa, fb;
279     uint32_t r = 0;
280 
281     fa.l = a;
282     fb.l = b;
283 
284     if (float32_is_signaling_nan(fa.f, &env->fp_status) ||
285         float32_is_signaling_nan(fb.f, &env->fp_status)) {
286         update_fpu_flags(env, float_flag_invalid);
287         r = 1;
288     }
289 
290     if (float32_is_quiet_nan(fa.f, &env->fp_status) ||
291         float32_is_quiet_nan(fb.f, &env->fp_status)) {
292         r = 1;
293     }
294 
295     return r;
296 }
297 
298 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
299 {
300     CPU_FloatU fa, fb;
301     int r;
302     int flags;
303 
304     set_float_exception_flags(0, &env->fp_status);
305     fa.l = a;
306     fb.l = b;
307     r = float32_lt(fb.f, fa.f, &env->fp_status);
308     flags = get_float_exception_flags(&env->fp_status);
309     update_fpu_flags(env, flags & float_flag_invalid);
310 
311     return r;
312 }
313 
314 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
315 {
316     CPU_FloatU fa, fb;
317     int flags;
318     int r;
319 
320     set_float_exception_flags(0, &env->fp_status);
321     fa.l = a;
322     fb.l = b;
323     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
324     flags = get_float_exception_flags(&env->fp_status);
325     update_fpu_flags(env, flags & float_flag_invalid);
326 
327     return r;
328 }
329 
330 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
331 {
332     CPU_FloatU fa, fb;
333     int flags;
334     int r;
335 
336     fa.l = a;
337     fb.l = b;
338     set_float_exception_flags(0, &env->fp_status);
339     r = float32_le(fa.f, fb.f, &env->fp_status);
340     flags = get_float_exception_flags(&env->fp_status);
341     update_fpu_flags(env, flags & float_flag_invalid);
342 
343 
344     return r;
345 }
346 
347 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
348 {
349     CPU_FloatU fa, fb;
350     int flags, r;
351 
352     fa.l = a;
353     fb.l = b;
354     set_float_exception_flags(0, &env->fp_status);
355     r = float32_lt(fa.f, fb.f, &env->fp_status);
356     flags = get_float_exception_flags(&env->fp_status);
357     update_fpu_flags(env, flags & float_flag_invalid);
358     return r;
359 }
360 
361 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
362 {
363     CPU_FloatU fa, fb;
364     int flags, r;
365 
366     fa.l = a;
367     fb.l = b;
368     set_float_exception_flags(0, &env->fp_status);
369     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
370     flags = get_float_exception_flags(&env->fp_status);
371     update_fpu_flags(env, flags & float_flag_invalid);
372 
373     return r;
374 }
375 
376 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
377 {
378     CPU_FloatU fa, fb;
379     int flags, r;
380 
381     fa.l = a;
382     fb.l = b;
383     set_float_exception_flags(0, &env->fp_status);
384     r = !float32_lt(fa.f, fb.f, &env->fp_status);
385     flags = get_float_exception_flags(&env->fp_status);
386     update_fpu_flags(env, flags & float_flag_invalid);
387 
388     return r;
389 }
390 
391 uint32_t helper_flt(CPUMBState *env, uint32_t a)
392 {
393     CPU_FloatU fd, fa;
394 
395     fa.l = a;
396     fd.f = int32_to_float32(fa.l, &env->fp_status);
397     return fd.l;
398 }
399 
400 uint32_t helper_fint(CPUMBState *env, uint32_t a)
401 {
402     CPU_FloatU fa;
403     uint32_t r;
404     int flags;
405 
406     set_float_exception_flags(0, &env->fp_status);
407     fa.l = a;
408     r = float32_to_int32(fa.f, &env->fp_status);
409     flags = get_float_exception_flags(&env->fp_status);
410     update_fpu_flags(env, flags);
411 
412     return r;
413 }
414 
415 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
416 {
417     CPU_FloatU fd, fa;
418     int flags;
419 
420     set_float_exception_flags(0, &env->fp_status);
421     fa.l = a;
422     fd.l = float32_sqrt(fa.f, &env->fp_status);
423     flags = get_float_exception_flags(&env->fp_status);
424     update_fpu_flags(env, flags);
425 
426     return fd.l;
427 }
428 
429 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
430 {
431     unsigned int i;
432     uint32_t mask = 0xff000000;
433 
434     for (i = 0; i < 4; i++) {
435         if ((a & mask) == (b & mask))
436             return i + 1;
437         mask >>= 8;
438     }
439     return 0;
440 }
441 
442 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
443                      uint32_t mask)
444 {
445     if (addr & mask) {
446             qemu_log_mask(CPU_LOG_INT,
447                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
448                           addr, mask, wr, dr);
449             env->sregs[SR_EAR] = addr;
450             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
451                                  | (dr & 31) << 5;
452             if (mask == 3) {
453                 env->sregs[SR_ESR] |= 1 << 11;
454             }
455             if (!(env->sregs[SR_MSR] & MSR_EE)) {
456                 return;
457             }
458             helper_raise_exception(env, EXCP_HW_EXCP);
459     }
460 }
461 
462 void helper_stackprot(CPUMBState *env, uint32_t addr)
463 {
464     if (addr < env->slr || addr > env->shr) {
465         qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
466                       addr, env->slr, env->shr);
467         env->sregs[SR_EAR] = addr;
468         env->sregs[SR_ESR] = ESR_EC_STACKPROT;
469         helper_raise_exception(env, EXCP_HW_EXCP);
470     }
471 }
472 
473 #if !defined(CONFIG_USER_ONLY)
474 /* Writes/reads to the MMU's special regs end up here.  */
475 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
476 {
477     return mmu_read(env, rn);
478 }
479 
480 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
481 {
482     mmu_write(env, rn, v);
483 }
484 
485 void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
486                               bool is_write, bool is_exec, int is_asi,
487                               unsigned size)
488 {
489     MicroBlazeCPU *cpu;
490     CPUMBState *env;
491 
492     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
493              addr, is_write ? 1 : 0, is_exec ? 1 : 0);
494     if (cs == NULL) {
495         return;
496     }
497     cpu = MICROBLAZE_CPU(cs);
498     env = &cpu->env;
499     if (!(env->sregs[SR_MSR] & MSR_EE)) {
500         return;
501     }
502 
503     env->sregs[SR_EAR] = addr;
504     if (is_exec) {
505         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
506             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
507             helper_raise_exception(env, EXCP_HW_EXCP);
508         }
509     } else {
510         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
511             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
512             helper_raise_exception(env, EXCP_HW_EXCP);
513         }
514     }
515 }
516 #endif
517