xref: /openbmc/qemu/target/microblaze/op_helper.c (revision 98670d47) 
1 /*
2  *  Microblaze helper routines.
3  *
4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/host-utils.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 
28 #define D(x)
29 
30 #if !defined(CONFIG_USER_ONLY)
31 
32 /* Try to fill the TLB and return an exception if error. If retaddr is
33  * NULL, it means that the function was called in C code (i.e. not
34  * from generated code or from helper.c)
35  */
36 void tlb_fill(CPUState *cs, target_ulong addr, int size,
37               MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
38 {
39     int ret;
40 
41     ret = mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
42     if (unlikely(ret)) {
43         /* now we have a real cpu fault */
44         cpu_loop_exit_restore(cs, retaddr);
45     }
46 }
47 #endif
48 
49 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
50 {
51     int test = ctrl & STREAM_TEST;
52     int atomic = ctrl & STREAM_ATOMIC;
53     int control = ctrl & STREAM_CONTROL;
54     int nonblock = ctrl & STREAM_NONBLOCK;
55     int exception = ctrl & STREAM_EXCEPTION;
56 
57     qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
58              id, data,
59              test ? "t" : "",
60              nonblock ? "n" : "",
61              exception ? "e" : "",
62              control ? "c" : "",
63              atomic ? "a" : "");
64 }
65 
66 uint32_t helper_get(uint32_t id, uint32_t ctrl)
67 {
68     int test = ctrl & STREAM_TEST;
69     int atomic = ctrl & STREAM_ATOMIC;
70     int control = ctrl & STREAM_CONTROL;
71     int nonblock = ctrl & STREAM_NONBLOCK;
72     int exception = ctrl & STREAM_EXCEPTION;
73 
74     qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
75              id,
76              test ? "t" : "",
77              nonblock ? "n" : "",
78              exception ? "e" : "",
79              control ? "c" : "",
80              atomic ? "a" : "");
81     return 0xdead0000 | id;
82 }
83 
84 void helper_raise_exception(CPUMBState *env, uint32_t index)
85 {
86     CPUState *cs = CPU(mb_env_get_cpu(env));
87 
88     cs->exception_index = index;
89     cpu_loop_exit(cs);
90 }
91 
92 void helper_debug(CPUMBState *env)
93 {
94     int i;
95 
96     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
97     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
98              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
99              env->debug, env->imm, env->iflags);
100     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
101              env->btaken, env->btarget,
102              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
103              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
104              (env->sregs[SR_MSR] & MSR_EIP),
105              (env->sregs[SR_MSR] & MSR_IE));
106     for (i = 0; i < 32; i++) {
107         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
108         if ((i + 1) % 4 == 0)
109             qemu_log("\n");
110     }
111     qemu_log("\n\n");
112 }
113 
114 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
115 {
116     uint32_t cout = 0;
117 
118     if ((b == ~0) && cin)
119         cout = 1;
120     else if ((~0 - a) < (b + cin))
121         cout = 1;
122     return cout;
123 }
124 
125 uint32_t helper_cmp(uint32_t a, uint32_t b)
126 {
127     uint32_t t;
128 
129     t = b + ~a + 1;
130     if ((b & 0x80000000) ^ (a & 0x80000000))
131         t = (t & 0x7fffffff) | (b & 0x80000000);
132     return t;
133 }
134 
135 uint32_t helper_cmpu(uint32_t a, uint32_t b)
136 {
137     uint32_t t;
138 
139     t = b + ~a + 1;
140     if ((b & 0x80000000) ^ (a & 0x80000000))
141         t = (t & 0x7fffffff) | (a & 0x80000000);
142     return t;
143 }
144 
145 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
146 {
147     return compute_carry(a, b, cf);
148 }
149 
150 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
151 {
152     if (b == 0) {
153         env->sregs[SR_MSR] |= MSR_DZ;
154 
155         if ((env->sregs[SR_MSR] & MSR_EE)
156             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
157             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
158             helper_raise_exception(env, EXCP_HW_EXCP);
159         }
160         return 0;
161     }
162     env->sregs[SR_MSR] &= ~MSR_DZ;
163     return 1;
164 }
165 
166 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
167 {
168     if (!div_prepare(env, a, b)) {
169         return 0;
170     }
171     return (int32_t)a / (int32_t)b;
172 }
173 
174 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
175 {
176     if (!div_prepare(env, a, b)) {
177         return 0;
178     }
179     return a / b;
180 }
181 
182 /* raise FPU exception.  */
183 static void raise_fpu_exception(CPUMBState *env)
184 {
185     env->sregs[SR_ESR] = ESR_EC_FPU;
186     helper_raise_exception(env, EXCP_HW_EXCP);
187 }
188 
189 static void update_fpu_flags(CPUMBState *env, int flags)
190 {
191     int raise = 0;
192 
193     if (flags & float_flag_invalid) {
194         env->sregs[SR_FSR] |= FSR_IO;
195         raise = 1;
196     }
197     if (flags & float_flag_divbyzero) {
198         env->sregs[SR_FSR] |= FSR_DZ;
199         raise = 1;
200     }
201     if (flags & float_flag_overflow) {
202         env->sregs[SR_FSR] |= FSR_OF;
203         raise = 1;
204     }
205     if (flags & float_flag_underflow) {
206         env->sregs[SR_FSR] |= FSR_UF;
207         raise = 1;
208     }
209     if (raise
210         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
211         && (env->sregs[SR_MSR] & MSR_EE)) {
212         raise_fpu_exception(env);
213     }
214 }
215 
216 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
217 {
218     CPU_FloatU fd, fa, fb;
219     int flags;
220 
221     set_float_exception_flags(0, &env->fp_status);
222     fa.l = a;
223     fb.l = b;
224     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
225 
226     flags = get_float_exception_flags(&env->fp_status);
227     update_fpu_flags(env, flags);
228     return fd.l;
229 }
230 
231 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
232 {
233     CPU_FloatU fd, fa, fb;
234     int flags;
235 
236     set_float_exception_flags(0, &env->fp_status);
237     fa.l = a;
238     fb.l = b;
239     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
240     flags = get_float_exception_flags(&env->fp_status);
241     update_fpu_flags(env, flags);
242     return fd.l;
243 }
244 
245 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
246 {
247     CPU_FloatU fd, fa, fb;
248     int flags;
249 
250     set_float_exception_flags(0, &env->fp_status);
251     fa.l = a;
252     fb.l = b;
253     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
254     flags = get_float_exception_flags(&env->fp_status);
255     update_fpu_flags(env, flags);
256 
257     return fd.l;
258 }
259 
260 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
261 {
262     CPU_FloatU fd, fa, fb;
263     int flags;
264 
265     set_float_exception_flags(0, &env->fp_status);
266     fa.l = a;
267     fb.l = b;
268     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
269     flags = get_float_exception_flags(&env->fp_status);
270     update_fpu_flags(env, flags);
271 
272     return fd.l;
273 }
274 
275 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
276 {
277     CPU_FloatU fa, fb;
278     uint32_t r = 0;
279 
280     fa.l = a;
281     fb.l = b;
282 
283     if (float32_is_signaling_nan(fa.f, &env->fp_status) ||
284         float32_is_signaling_nan(fb.f, &env->fp_status)) {
285         update_fpu_flags(env, float_flag_invalid);
286         r = 1;
287     }
288 
289     if (float32_is_quiet_nan(fa.f, &env->fp_status) ||
290         float32_is_quiet_nan(fb.f, &env->fp_status)) {
291         r = 1;
292     }
293 
294     return r;
295 }
296 
297 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
298 {
299     CPU_FloatU fa, fb;
300     int r;
301     int flags;
302 
303     set_float_exception_flags(0, &env->fp_status);
304     fa.l = a;
305     fb.l = b;
306     r = float32_lt(fb.f, fa.f, &env->fp_status);
307     flags = get_float_exception_flags(&env->fp_status);
308     update_fpu_flags(env, flags & float_flag_invalid);
309 
310     return r;
311 }
312 
313 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
314 {
315     CPU_FloatU fa, fb;
316     int flags;
317     int r;
318 
319     set_float_exception_flags(0, &env->fp_status);
320     fa.l = a;
321     fb.l = b;
322     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
323     flags = get_float_exception_flags(&env->fp_status);
324     update_fpu_flags(env, flags & float_flag_invalid);
325 
326     return r;
327 }
328 
329 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
330 {
331     CPU_FloatU fa, fb;
332     int flags;
333     int r;
334 
335     fa.l = a;
336     fb.l = b;
337     set_float_exception_flags(0, &env->fp_status);
338     r = float32_le(fa.f, fb.f, &env->fp_status);
339     flags = get_float_exception_flags(&env->fp_status);
340     update_fpu_flags(env, flags & float_flag_invalid);
341 
342 
343     return r;
344 }
345 
346 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
347 {
348     CPU_FloatU fa, fb;
349     int flags, r;
350 
351     fa.l = a;
352     fb.l = b;
353     set_float_exception_flags(0, &env->fp_status);
354     r = float32_lt(fa.f, fb.f, &env->fp_status);
355     flags = get_float_exception_flags(&env->fp_status);
356     update_fpu_flags(env, flags & float_flag_invalid);
357     return r;
358 }
359 
360 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
361 {
362     CPU_FloatU fa, fb;
363     int flags, r;
364 
365     fa.l = a;
366     fb.l = b;
367     set_float_exception_flags(0, &env->fp_status);
368     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
369     flags = get_float_exception_flags(&env->fp_status);
370     update_fpu_flags(env, flags & float_flag_invalid);
371 
372     return r;
373 }
374 
375 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
376 {
377     CPU_FloatU fa, fb;
378     int flags, r;
379 
380     fa.l = a;
381     fb.l = b;
382     set_float_exception_flags(0, &env->fp_status);
383     r = !float32_lt(fa.f, fb.f, &env->fp_status);
384     flags = get_float_exception_flags(&env->fp_status);
385     update_fpu_flags(env, flags & float_flag_invalid);
386 
387     return r;
388 }
389 
390 uint32_t helper_flt(CPUMBState *env, uint32_t a)
391 {
392     CPU_FloatU fd, fa;
393 
394     fa.l = a;
395     fd.f = int32_to_float32(fa.l, &env->fp_status);
396     return fd.l;
397 }
398 
399 uint32_t helper_fint(CPUMBState *env, uint32_t a)
400 {
401     CPU_FloatU fa;
402     uint32_t r;
403     int flags;
404 
405     set_float_exception_flags(0, &env->fp_status);
406     fa.l = a;
407     r = float32_to_int32(fa.f, &env->fp_status);
408     flags = get_float_exception_flags(&env->fp_status);
409     update_fpu_flags(env, flags);
410 
411     return r;
412 }
413 
414 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
415 {
416     CPU_FloatU fd, fa;
417     int flags;
418 
419     set_float_exception_flags(0, &env->fp_status);
420     fa.l = a;
421     fd.l = float32_sqrt(fa.f, &env->fp_status);
422     flags = get_float_exception_flags(&env->fp_status);
423     update_fpu_flags(env, flags);
424 
425     return fd.l;
426 }
427 
428 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
429 {
430     unsigned int i;
431     uint32_t mask = 0xff000000;
432 
433     for (i = 0; i < 4; i++) {
434         if ((a & mask) == (b & mask))
435             return i + 1;
436         mask >>= 8;
437     }
438     return 0;
439 }
440 
441 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
442                      uint32_t mask)
443 {
444     if (addr & mask) {
445             qemu_log_mask(CPU_LOG_INT,
446                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
447                           addr, mask, wr, dr);
448             env->sregs[SR_EAR] = addr;
449             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
450                                  | (dr & 31) << 5;
451             if (mask == 3) {
452                 env->sregs[SR_ESR] |= 1 << 11;
453             }
454             if (!(env->sregs[SR_MSR] & MSR_EE)) {
455                 return;
456             }
457             helper_raise_exception(env, EXCP_HW_EXCP);
458     }
459 }
460 
461 void helper_stackprot(CPUMBState *env, uint32_t addr)
462 {
463     if (addr < env->slr || addr > env->shr) {
464         qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
465                       addr, env->slr, env->shr);
466         env->sregs[SR_EAR] = addr;
467         env->sregs[SR_ESR] = ESR_EC_STACKPROT;
468         helper_raise_exception(env, EXCP_HW_EXCP);
469     }
470 }
471 
472 #if !defined(CONFIG_USER_ONLY)
473 /* Writes/reads to the MMU's special regs end up here.  */
474 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
475 {
476     return mmu_read(env, rn);
477 }
478 
479 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
480 {
481     mmu_write(env, rn, v);
482 }
483 
484 void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
485                               bool is_write, bool is_exec, int is_asi,
486                               unsigned size)
487 {
488     MicroBlazeCPU *cpu;
489     CPUMBState *env;
490 
491     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
492              addr, is_write ? 1 : 0, is_exec ? 1 : 0);
493     if (cs == NULL) {
494         return;
495     }
496     cpu = MICROBLAZE_CPU(cs);
497     env = &cpu->env;
498     if (!(env->sregs[SR_MSR] & MSR_EE)) {
499         return;
500     }
501 
502     env->sregs[SR_EAR] = addr;
503     if (is_exec) {
504         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
505             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
506             helper_raise_exception(env, EXCP_HW_EXCP);
507         }
508     } else {
509         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
510             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
511             helper_raise_exception(env, EXCP_HW_EXCP);
512         }
513     }
514 }
515 #endif
516