1 /* 2 * MicroBlaze gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/gdbstub.h" 23 24 int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) 25 { 26 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 27 CPUMBState *env = &cpu->env; 28 /* 29 * GDB expects SREGs in the following order: 30 * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. 31 * They aren't stored in this order, so make a map. 32 * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't 33 * map them to anything and return a value of 0 instead. 34 */ 35 static const uint8_t sreg_map[6] = { 36 SR_PC, 37 SR_MSR, 38 SR_EAR, 39 SR_ESR, 40 SR_FSR, 41 SR_BTR 42 }; 43 44 /* 45 * GDB expects registers to be reported in this order: 46 * R0-R31 47 * PC-BTR 48 * PVR0-PVR11 49 * EDR-TLBHI 50 * SLR-SHR 51 */ 52 if (n < 32) { 53 return gdb_get_reg32(mem_buf, env->regs[n]); 54 } else { 55 n -= 32; 56 switch (n) { 57 case 0 ... 5: 58 return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]); 59 /* PVR12 is intentionally skipped */ 60 case 6 ... 17: 61 n -= 6; 62 return gdb_get_reg32(mem_buf, env->pvr.regs[n]); 63 case 18: 64 return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]); 65 /* Other SRegs aren't modeled, so report a value of 0 */ 66 case 19 ... 24: 67 return gdb_get_reg32(mem_buf, 0); 68 case 25: 69 return gdb_get_reg32(mem_buf, env->slr); 70 case 26: 71 return gdb_get_reg32(mem_buf, env->shr); 72 default: 73 return 0; 74 } 75 } 76 } 77 78 int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 79 { 80 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 81 CPUClass *cc = CPU_GET_CLASS(cs); 82 CPUMBState *env = &cpu->env; 83 uint32_t tmp; 84 85 /* 86 * GDB expects SREGs in the following order: 87 * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. 88 * They aren't stored in this order, so make a map. 89 * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't 90 * map them to anything. 91 */ 92 static const uint8_t sreg_map[6] = { 93 SR_PC, 94 SR_MSR, 95 SR_EAR, 96 SR_ESR, 97 SR_FSR, 98 SR_BTR 99 }; 100 101 if (n > cc->gdb_num_core_regs) { 102 return 0; 103 } 104 105 tmp = ldl_p(mem_buf); 106 107 /* 108 * GDB expects registers to be reported in this order: 109 * R0-R31 110 * PC-BTR 111 * PVR0-PVR11 112 * EDR-TLBHI 113 * SLR-SHR 114 */ 115 if (n < 32) { 116 env->regs[n] = tmp; 117 } else { 118 n -= 32; 119 switch (n) { 120 case 0 ... 5: 121 env->sregs[sreg_map[n]] = tmp; 122 break; 123 /* PVR12 is intentionally skipped */ 124 case 6 ... 17: 125 n -= 6; 126 env->pvr.regs[n] = tmp; 127 break; 128 /* Only EDR is modeled in these indeces, so ignore the rest */ 129 case 18: 130 env->sregs[SR_EDR] = tmp; 131 break; 132 case 25: 133 env->slr = tmp; 134 break; 135 case 26: 136 env->shr = tmp; 137 break; 138 } 139 } 140 return 4; 141 } 142