1 /* 2 * MicroBlaze virtual CPU header 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef MICROBLAZE_CPU_H 21 #define MICROBLAZE_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 28 #define CPUArchState struct CPUMBState 29 30 struct CPUMBState; 31 typedef struct CPUMBState CPUMBState; 32 #if !defined(CONFIG_USER_ONLY) 33 #include "mmu.h" 34 #endif 35 36 #define EXCP_MMU 1 37 #define EXCP_IRQ 2 38 #define EXCP_BREAK 3 39 #define EXCP_HW_BREAK 4 40 #define EXCP_HW_EXCP 5 41 42 /* MicroBlaze-specific interrupt pending bits. */ 43 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 44 45 /* Meanings of the MBCPU object's two inbound GPIO lines */ 46 #define MB_CPU_IRQ 0 47 #define MB_CPU_FIR 1 48 49 /* Register aliases. R0 - R15 */ 50 #define R_SP 1 51 #define SR_PC 0 52 #define SR_MSR 1 53 #define SR_EAR 3 54 #define SR_ESR 5 55 #define SR_FSR 7 56 #define SR_BTR 0xb 57 #define SR_EDR 0xd 58 59 /* MSR flags. */ 60 #define MSR_BE (1<<0) /* 0x001 */ 61 #define MSR_IE (1<<1) /* 0x002 */ 62 #define MSR_C (1<<2) /* 0x004 */ 63 #define MSR_BIP (1<<3) /* 0x008 */ 64 #define MSR_FSL (1<<4) /* 0x010 */ 65 #define MSR_ICE (1<<5) /* 0x020 */ 66 #define MSR_DZ (1<<6) /* 0x040 */ 67 #define MSR_DCE (1<<7) /* 0x080 */ 68 #define MSR_EE (1<<8) /* 0x100 */ 69 #define MSR_EIP (1<<9) /* 0x200 */ 70 #define MSR_PVR (1<<10) /* 0x400 */ 71 #define MSR_CC (1<<31) 72 73 /* Machine State Register (MSR) Fields */ 74 #define MSR_UM (1<<11) /* User Mode */ 75 #define MSR_UMS (1<<12) /* User Mode Save */ 76 #define MSR_VM (1<<13) /* Virtual Mode */ 77 #define MSR_VMS (1<<14) /* Virtual Mode Save */ 78 79 #define MSR_KERNEL MSR_EE|MSR_VM 80 //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE 81 #define MSR_KERNEL_VMS MSR_EE|MSR_VMS 82 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE 83 84 /* Exception State Register (ESR) Fields */ 85 #define ESR_DIZ (1<<11) /* Zone Protection */ 86 #define ESR_S (1<<10) /* Store instruction */ 87 88 #define ESR_ESS_FSL_OFFSET 5 89 90 #define ESR_EC_FSL 0 91 #define ESR_EC_UNALIGNED_DATA 1 92 #define ESR_EC_ILLEGAL_OP 2 93 #define ESR_EC_INSN_BUS 3 94 #define ESR_EC_DATA_BUS 4 95 #define ESR_EC_DIVZERO 5 96 #define ESR_EC_FPU 6 97 #define ESR_EC_PRIVINSN 7 98 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ 99 #define ESR_EC_DATA_STORAGE 8 100 #define ESR_EC_INSN_STORAGE 9 101 #define ESR_EC_DATA_TLB 10 102 #define ESR_EC_INSN_TLB 11 103 #define ESR_EC_MASK 31 104 105 /* Floating Point Status Register (FSR) Bits */ 106 #define FSR_IO (1<<4) /* Invalid operation */ 107 #define FSR_DZ (1<<3) /* Divide-by-zero */ 108 #define FSR_OF (1<<2) /* Overflow */ 109 #define FSR_UF (1<<1) /* Underflow */ 110 #define FSR_DO (1<<0) /* Denormalized operand error */ 111 112 /* Version reg. */ 113 /* Basic PVR mask */ 114 #define PVR0_PVR_FULL_MASK 0x80000000 115 #define PVR0_USE_BARREL_MASK 0x40000000 116 #define PVR0_USE_DIV_MASK 0x20000000 117 #define PVR0_USE_HW_MUL_MASK 0x10000000 118 #define PVR0_USE_FPU_MASK 0x08000000 119 #define PVR0_USE_EXC_MASK 0x04000000 120 #define PVR0_USE_ICACHE_MASK 0x02000000 121 #define PVR0_USE_DCACHE_MASK 0x01000000 122 #define PVR0_USE_MMU_MASK 0x00800000 123 #define PVR0_USE_BTC 0x00400000 124 #define PVR0_ENDI_MASK 0x00200000 125 #define PVR0_FAULT 0x00100000 126 #define PVR0_VERSION_MASK 0x0000FF00 127 #define PVR0_USER1_MASK 0x000000FF 128 #define PVR0_SPROT_MASK 0x00000001 129 130 #define PVR0_VERSION_SHIFT 8 131 132 /* User 2 PVR mask */ 133 #define PVR1_USER2_MASK 0xFFFFFFFF 134 135 /* Configuration PVR masks */ 136 #define PVR2_D_OPB_MASK 0x80000000 137 #define PVR2_D_LMB_MASK 0x40000000 138 #define PVR2_I_OPB_MASK 0x20000000 139 #define PVR2_I_LMB_MASK 0x10000000 140 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 141 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 142 #define PVR2_D_PLB_MASK 0x02000000 /* new */ 143 #define PVR2_I_PLB_MASK 0x01000000 /* new */ 144 #define PVR2_INTERCONNECT 0x00800000 /* new */ 145 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 146 #define PVR2_USE_FSL_EXC 0x00040000 /* new */ 147 #define PVR2_USE_MSR_INSTR 0x00020000 148 #define PVR2_USE_PCMP_INSTR 0x00010000 149 #define PVR2_AREA_OPTIMISED 0x00008000 150 #define PVR2_USE_BARREL_MASK 0x00004000 151 #define PVR2_USE_DIV_MASK 0x00002000 152 #define PVR2_USE_HW_MUL_MASK 0x00001000 153 #define PVR2_USE_FPU_MASK 0x00000800 154 #define PVR2_USE_MUL64_MASK 0x00000400 155 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 156 #define PVR2_USE_IPLBEXC 0x00000100 157 #define PVR2_USE_DPLBEXC 0x00000080 158 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 159 #define PVR2_UNALIGNED_EXC_MASK 0x00000020 160 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 161 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 162 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 163 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 164 #define PVR2_FPU_EXC_MASK 0x00000001 165 166 /* Debug and exception PVR masks */ 167 #define PVR3_DEBUG_ENABLED_MASK 0x80000000 168 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 169 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 170 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 171 #define PVR3_FSL_LINKS_MASK 0x00000380 172 173 /* ICache config PVR masks */ 174 #define PVR4_USE_ICACHE_MASK 0x80000000 175 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 176 #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 177 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 178 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 179 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 180 181 /* DCache config PVR masks */ 182 #define PVR5_USE_DCACHE_MASK 0x80000000 183 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 184 #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 185 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 186 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 187 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 188 #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000 189 190 /* ICache base address PVR mask */ 191 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF 192 193 /* ICache high address PVR mask */ 194 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF 195 196 /* DCache base address PVR mask */ 197 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF 198 199 /* DCache high address PVR mask */ 200 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF 201 202 /* Target family PVR mask */ 203 #define PVR10_TARGET_FAMILY_MASK 0xFF000000 204 #define PVR10_ASIZE_SHIFT 18 205 206 /* MMU descrtiption */ 207 #define PVR11_USE_MMU 0xC0000000 208 #define PVR11_MMU_ITLB_SIZE 0x38000000 209 #define PVR11_MMU_DTLB_SIZE 0x07000000 210 #define PVR11_MMU_TLB_ACCESS 0x00C00000 211 #define PVR11_MMU_ZONES 0x003E0000 212 /* MSR Reset value PVR mask */ 213 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF 214 215 #define C_PVR_NONE 0 216 #define C_PVR_BASIC 1 217 #define C_PVR_FULL 2 218 219 /* CPU flags. */ 220 221 /* Condition codes. */ 222 #define CC_GE 5 223 #define CC_GT 4 224 #define CC_LE 3 225 #define CC_LT 2 226 #define CC_NE 1 227 #define CC_EQ 0 228 229 #define STREAM_EXCEPTION (1 << 0) 230 #define STREAM_ATOMIC (1 << 1) 231 #define STREAM_TEST (1 << 2) 232 #define STREAM_CONTROL (1 << 3) 233 #define STREAM_NONBLOCK (1 << 4) 234 235 struct CPUMBState { 236 uint32_t debug; 237 uint32_t btaken; 238 uint64_t btarget; 239 uint32_t bimm; 240 241 uint32_t imm; 242 uint32_t regs[32]; 243 uint64_t sregs[14]; 244 float_status fp_status; 245 /* Stack protectors. Yes, it's a hw feature. */ 246 uint32_t slr, shr; 247 248 /* lwx/swx reserved address */ 249 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ 250 target_ulong res_addr; 251 uint32_t res_val; 252 253 /* Internal flags. */ 254 #define IMM_FLAG 4 255 #define MSR_EE_FLAG (1 << 8) 256 #define DRTI_FLAG (1 << 16) 257 #define DRTE_FLAG (1 << 17) 258 #define DRTB_FLAG (1 << 18) 259 #define D_FLAG (1 << 19) /* Bit in ESR. */ 260 /* TB dependent CPUMBState. */ 261 #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) 262 uint32_t iflags; 263 264 #if !defined(CONFIG_USER_ONLY) 265 /* Unified MMU. */ 266 struct microblaze_mmu mmu; 267 #endif 268 269 /* Fields up to this point are cleared by a CPU reset */ 270 struct {} end_reset_fields; 271 272 CPU_COMMON 273 274 /* These fields are preserved on reset. */ 275 276 struct { 277 uint32_t regs[13]; 278 } pvr; 279 }; 280 281 /** 282 * MicroBlazeCPU: 283 * @env: #CPUMBState 284 * 285 * A MicroBlaze CPU. 286 */ 287 struct MicroBlazeCPU { 288 /*< private >*/ 289 CPUState parent_obj; 290 291 /*< public >*/ 292 293 /* Microblaze Configuration Settings */ 294 struct { 295 bool stackprot; 296 uint32_t base_vectors; 297 uint8_t addr_size; 298 uint8_t use_fpu; 299 uint8_t use_hw_mul; 300 bool use_barrel; 301 bool use_div; 302 bool use_msr_instr; 303 bool use_pcmp_instr; 304 bool use_mmu; 305 bool dcache_writeback; 306 bool endi; 307 bool dopb_bus_exception; 308 bool iopb_bus_exception; 309 char *version; 310 uint8_t pvr; 311 } cfg; 312 313 CPUMBState env; 314 }; 315 316 static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) 317 { 318 return container_of(env, MicroBlazeCPU, env); 319 } 320 321 #define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) 322 323 #define ENV_OFFSET offsetof(MicroBlazeCPU, env) 324 325 void mb_cpu_do_interrupt(CPUState *cs); 326 bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); 327 void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 328 hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 329 int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 330 int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 331 332 void mb_tcg_init(void); 333 /* you can call this signal handler from your SIGBUS and SIGSEGV 334 signal handlers to inform the virtual CPU of exceptions. non zero 335 is returned if the signal was handled by the virtual CPU. */ 336 int cpu_mb_signal_handler(int host_signum, void *pinfo, 337 void *puc); 338 339 #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU 340 341 #define cpu_signal_handler cpu_mb_signal_handler 342 343 /* MMU modes definitions */ 344 #define MMU_MODE0_SUFFIX _nommu 345 #define MMU_MODE1_SUFFIX _kernel 346 #define MMU_MODE2_SUFFIX _user 347 #define MMU_NOMMU_IDX 0 348 #define MMU_KERNEL_IDX 1 349 #define MMU_USER_IDX 2 350 /* See NB_MMU_MODES further up the file. */ 351 352 static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) 353 { 354 MicroBlazeCPU *cpu = mb_env_get_cpu(env); 355 356 /* Are we in nommu mode?. */ 357 if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { 358 return MMU_NOMMU_IDX; 359 } 360 361 if (env->sregs[SR_MSR] & MSR_UM) { 362 return MMU_USER_IDX; 363 } 364 return MMU_KERNEL_IDX; 365 } 366 367 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 368 MMUAccessType access_type, int mmu_idx, 369 bool probe, uintptr_t retaddr); 370 371 #include "exec/cpu-all.h" 372 373 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, 374 target_ulong *cs_base, uint32_t *flags) 375 { 376 *pc = env->sregs[SR_PC]; 377 *cs_base = 0; 378 *flags = (env->iflags & IFLAGS_TB_MASK) | 379 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); 380 } 381 382 #if !defined(CONFIG_USER_ONLY) 383 void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 384 unsigned size, MMUAccessType access_type, 385 int mmu_idx, MemTxAttrs attrs, 386 MemTxResult response, uintptr_t retaddr); 387 #endif 388 389 #endif 390