1 /* 2 * QEMU MicroBlaze CPU 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * Copyright (c) 2012 SUSE LINUX Products GmbH 7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "qemu-common.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "exec/exec-all.h" 31 32 static const struct { 33 const char *name; 34 uint8_t version_id; 35 } mb_cpu_lookup[] = { 36 /* These key value are as per MBV field in PVR0 */ 37 {"5.00.a", 0x01}, 38 {"5.00.b", 0x02}, 39 {"5.00.c", 0x03}, 40 {"6.00.a", 0x04}, 41 {"6.00.b", 0x06}, 42 {"7.00.a", 0x05}, 43 {"7.00.b", 0x07}, 44 {"7.10.a", 0x08}, 45 {"7.10.b", 0x09}, 46 {"7.10.c", 0x0a}, 47 {"7.10.d", 0x0b}, 48 {"7.20.a", 0x0c}, 49 {"7.20.b", 0x0d}, 50 {"7.20.c", 0x0e}, 51 {"7.20.d", 0x0f}, 52 {"7.30.a", 0x10}, 53 {"7.30.b", 0x11}, 54 {"8.00.a", 0x12}, 55 {"8.00.b", 0x13}, 56 {"8.10.a", 0x14}, 57 {"8.20.a", 0x15}, 58 {"8.20.b", 0x16}, 59 {"8.30.a", 0x17}, 60 {"8.40.a", 0x18}, 61 {"8.40.b", 0x19}, 62 {"8.50.a", 0x1A}, 63 {"9.0", 0x1B}, 64 {"9.1", 0x1D}, 65 {"9.2", 0x1F}, 66 {"9.3", 0x20}, 67 {"9.4", 0x21}, 68 {"9.5", 0x22}, 69 {"9.6", 0x23}, 70 {"10.0", 0x24}, 71 {NULL, 0}, 72 }; 73 74 static void mb_cpu_set_pc(CPUState *cs, vaddr value) 75 { 76 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 77 78 cpu->env.sregs[SR_PC] = value; 79 } 80 81 static bool mb_cpu_has_work(CPUState *cs) 82 { 83 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 84 } 85 86 #ifndef CONFIG_USER_ONLY 87 static void microblaze_cpu_set_irq(void *opaque, int irq, int level) 88 { 89 MicroBlazeCPU *cpu = opaque; 90 CPUState *cs = CPU(cpu); 91 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; 92 93 if (level) { 94 cpu_interrupt(cs, type); 95 } else { 96 cpu_reset_interrupt(cs, type); 97 } 98 } 99 #endif 100 101 /* CPUClass::reset() */ 102 static void mb_cpu_reset(CPUState *s) 103 { 104 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); 105 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); 106 CPUMBState *env = &cpu->env; 107 108 mcc->parent_reset(s); 109 110 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); 111 env->res_addr = RES_ADDR_NONE; 112 113 /* Disable stack protector. */ 114 env->shr = ~0; 115 116 env->sregs[SR_PC] = cpu->cfg.base_vectors; 117 118 #if defined(CONFIG_USER_ONLY) 119 /* start in user mode with interrupts enabled. */ 120 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; 121 #else 122 env->sregs[SR_MSR] = 0; 123 mmu_init(&env->mmu); 124 env->mmu.c_mmu = 3; 125 env->mmu.c_mmu_tlb_access = 3; 126 env->mmu.c_mmu_zones = 16; 127 #endif 128 } 129 130 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) 131 { 132 info->mach = bfd_arch_microblaze; 133 info->print_insn = print_insn_microblaze; 134 } 135 136 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 137 { 138 CPUState *cs = CPU(dev); 139 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); 140 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 141 CPUMBState *env = &cpu->env; 142 uint8_t version_code = 0; 143 int i = 0; 144 Error *local_err = NULL; 145 146 cpu_exec_realizefn(cs, &local_err); 147 if (local_err != NULL) { 148 error_propagate(errp, local_err); 149 return; 150 } 151 152 qemu_init_vcpu(cs); 153 154 env->pvr.regs[0] = PVR0_USE_EXC_MASK \ 155 | PVR0_USE_ICACHE_MASK \ 156 | PVR0_USE_DCACHE_MASK; 157 env->pvr.regs[2] = PVR2_D_OPB_MASK \ 158 | PVR2_D_LMB_MASK \ 159 | PVR2_I_OPB_MASK \ 160 | PVR2_I_LMB_MASK \ 161 | PVR2_FPU_EXC_MASK \ 162 | 0; 163 164 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) { 165 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) { 166 version_code = mb_cpu_lookup[i].version_id; 167 break; 168 } 169 } 170 171 if (!version_code) { 172 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); 173 } 174 175 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | 176 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | 177 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | 178 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | 179 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | 180 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | 181 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | 182 (version_code << PVR0_VERSION_SHIFT) | 183 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); 184 185 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | 186 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | 187 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | 188 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | 189 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | 190 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | 191 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | 192 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); 193 194 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? 195 PVR5_DCACHE_WRITEBACK_MASK : 0; 196 197 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ 198 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); 199 200 mcc->parent_realize(dev, errp); 201 } 202 203 static void mb_cpu_initfn(Object *obj) 204 { 205 CPUState *cs = CPU(obj); 206 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); 207 CPUMBState *env = &cpu->env; 208 209 cs->env_ptr = env; 210 211 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 212 213 #ifndef CONFIG_USER_ONLY 214 /* Inbound IRQ and FIR lines */ 215 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); 216 #endif 217 } 218 219 static const VMStateDescription vmstate_mb_cpu = { 220 .name = "cpu", 221 .unmigratable = 1, 222 }; 223 224 static Property mb_properties[] = { 225 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), 226 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, 227 false), 228 /* If use-fpu > 0 - FPU is enabled 229 * If use-fpu = 2 - Floating point conversion and square root instructions 230 * are enabled 231 */ 232 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), 233 /* If use-hw-mul > 0 - Multiplier is enabled 234 * If use-hw-mul = 2 - 64-bit multiplier is enabled 235 */ 236 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), 237 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), 238 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), 239 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), 240 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), 241 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), 242 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, 243 false), 244 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), 245 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), 246 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), 247 DEFINE_PROP_END_OF_LIST(), 248 }; 249 250 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) 251 { 252 return object_class_by_name(TYPE_MICROBLAZE_CPU); 253 } 254 255 static void mb_cpu_class_init(ObjectClass *oc, void *data) 256 { 257 DeviceClass *dc = DEVICE_CLASS(oc); 258 CPUClass *cc = CPU_CLASS(oc); 259 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); 260 261 device_class_set_parent_realize(dc, mb_cpu_realizefn, 262 &mcc->parent_realize); 263 mcc->parent_reset = cc->reset; 264 cc->reset = mb_cpu_reset; 265 266 cc->class_by_name = mb_cpu_class_by_name; 267 cc->has_work = mb_cpu_has_work; 268 cc->do_interrupt = mb_cpu_do_interrupt; 269 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; 270 cc->dump_state = mb_cpu_dump_state; 271 cc->set_pc = mb_cpu_set_pc; 272 cc->gdb_read_register = mb_cpu_gdb_read_register; 273 cc->gdb_write_register = mb_cpu_gdb_write_register; 274 #ifdef CONFIG_USER_ONLY 275 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; 276 #else 277 cc->do_unassigned_access = mb_cpu_unassigned_access; 278 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; 279 #endif 280 dc->vmsd = &vmstate_mb_cpu; 281 dc->props = mb_properties; 282 cc->gdb_num_core_regs = 32 + 5; 283 284 cc->disas_set_info = mb_disas_set_info; 285 cc->tcg_initialize = mb_tcg_init; 286 } 287 288 static const TypeInfo mb_cpu_type_info = { 289 .name = TYPE_MICROBLAZE_CPU, 290 .parent = TYPE_CPU, 291 .instance_size = sizeof(MicroBlazeCPU), 292 .instance_init = mb_cpu_initfn, 293 .class_size = sizeof(MicroBlazeCPUClass), 294 .class_init = mb_cpu_class_init, 295 }; 296 297 static void mb_cpu_register_types(void) 298 { 299 type_register_static(&mb_cpu_type_info); 300 } 301 302 type_init(mb_cpu_register_types) 303