1 /* 2 * QEMU MicroBlaze CPU 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * Copyright (c) 2012 SUSE LINUX Products GmbH 7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "qemu-common.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "exec/exec-all.h" 31 #include "fpu/softfloat.h" 32 33 static const struct { 34 const char *name; 35 uint8_t version_id; 36 } mb_cpu_lookup[] = { 37 /* These key value are as per MBV field in PVR0 */ 38 {"5.00.a", 0x01}, 39 {"5.00.b", 0x02}, 40 {"5.00.c", 0x03}, 41 {"6.00.a", 0x04}, 42 {"6.00.b", 0x06}, 43 {"7.00.a", 0x05}, 44 {"7.00.b", 0x07}, 45 {"7.10.a", 0x08}, 46 {"7.10.b", 0x09}, 47 {"7.10.c", 0x0a}, 48 {"7.10.d", 0x0b}, 49 {"7.20.a", 0x0c}, 50 {"7.20.b", 0x0d}, 51 {"7.20.c", 0x0e}, 52 {"7.20.d", 0x0f}, 53 {"7.30.a", 0x10}, 54 {"7.30.b", 0x11}, 55 {"8.00.a", 0x12}, 56 {"8.00.b", 0x13}, 57 {"8.10.a", 0x14}, 58 {"8.20.a", 0x15}, 59 {"8.20.b", 0x16}, 60 {"8.30.a", 0x17}, 61 {"8.40.a", 0x18}, 62 {"8.40.b", 0x19}, 63 {"8.50.a", 0x1A}, 64 {"9.0", 0x1B}, 65 {"9.1", 0x1D}, 66 {"9.2", 0x1F}, 67 {"9.3", 0x20}, 68 {"9.4", 0x21}, 69 {"9.5", 0x22}, 70 {"9.6", 0x23}, 71 {"10.0", 0x24}, 72 {NULL, 0}, 73 }; 74 75 static void mb_cpu_set_pc(CPUState *cs, vaddr value) 76 { 77 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 78 79 cpu->env.sregs[SR_PC] = value; 80 } 81 82 static bool mb_cpu_has_work(CPUState *cs) 83 { 84 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 85 } 86 87 #ifndef CONFIG_USER_ONLY 88 static void microblaze_cpu_set_irq(void *opaque, int irq, int level) 89 { 90 MicroBlazeCPU *cpu = opaque; 91 CPUState *cs = CPU(cpu); 92 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; 93 94 if (level) { 95 cpu_interrupt(cs, type); 96 } else { 97 cpu_reset_interrupt(cs, type); 98 } 99 } 100 #endif 101 102 /* CPUClass::reset() */ 103 static void mb_cpu_reset(CPUState *s) 104 { 105 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); 106 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); 107 CPUMBState *env = &cpu->env; 108 109 mcc->parent_reset(s); 110 111 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); 112 env->res_addr = RES_ADDR_NONE; 113 114 /* Disable stack protector. */ 115 env->shr = ~0; 116 117 env->sregs[SR_PC] = cpu->cfg.base_vectors; 118 119 #if defined(CONFIG_USER_ONLY) 120 /* start in user mode with interrupts enabled. */ 121 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; 122 #else 123 env->sregs[SR_MSR] = 0; 124 mmu_init(&env->mmu); 125 env->mmu.c_mmu = 3; 126 env->mmu.c_mmu_tlb_access = 3; 127 env->mmu.c_mmu_zones = 16; 128 #endif 129 } 130 131 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) 132 { 133 info->mach = bfd_arch_microblaze; 134 info->print_insn = print_insn_microblaze; 135 } 136 137 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 138 { 139 CPUState *cs = CPU(dev); 140 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); 141 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 142 CPUMBState *env = &cpu->env; 143 uint8_t version_code = 0; 144 int i = 0; 145 Error *local_err = NULL; 146 147 cpu_exec_realizefn(cs, &local_err); 148 if (local_err != NULL) { 149 error_propagate(errp, local_err); 150 return; 151 } 152 153 qemu_init_vcpu(cs); 154 155 env->pvr.regs[0] = PVR0_USE_EXC_MASK \ 156 | PVR0_USE_ICACHE_MASK \ 157 | PVR0_USE_DCACHE_MASK; 158 env->pvr.regs[2] = PVR2_D_OPB_MASK \ 159 | PVR2_D_LMB_MASK \ 160 | PVR2_I_OPB_MASK \ 161 | PVR2_I_LMB_MASK \ 162 | PVR2_FPU_EXC_MASK \ 163 | 0; 164 165 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) { 166 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) { 167 version_code = mb_cpu_lookup[i].version_id; 168 break; 169 } 170 } 171 172 if (!version_code) { 173 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); 174 } 175 176 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | 177 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | 178 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | 179 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | 180 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | 181 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | 182 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | 183 (version_code << PVR0_VERSION_SHIFT) | 184 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); 185 186 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | 187 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | 188 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | 189 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | 190 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | 191 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | 192 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | 193 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); 194 195 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? 196 PVR5_DCACHE_WRITEBACK_MASK : 0; 197 198 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ 199 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); 200 201 mcc->parent_realize(dev, errp); 202 } 203 204 static void mb_cpu_initfn(Object *obj) 205 { 206 CPUState *cs = CPU(obj); 207 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); 208 CPUMBState *env = &cpu->env; 209 210 cs->env_ptr = env; 211 212 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 213 214 #ifndef CONFIG_USER_ONLY 215 /* Inbound IRQ and FIR lines */ 216 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); 217 #endif 218 } 219 220 static const VMStateDescription vmstate_mb_cpu = { 221 .name = "cpu", 222 .unmigratable = 1, 223 }; 224 225 static Property mb_properties[] = { 226 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), 227 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, 228 false), 229 /* If use-fpu > 0 - FPU is enabled 230 * If use-fpu = 2 - Floating point conversion and square root instructions 231 * are enabled 232 */ 233 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), 234 /* If use-hw-mul > 0 - Multiplier is enabled 235 * If use-hw-mul = 2 - 64-bit multiplier is enabled 236 */ 237 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), 238 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), 239 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), 240 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), 241 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), 242 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), 243 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, 244 false), 245 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), 246 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), 247 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), 248 DEFINE_PROP_END_OF_LIST(), 249 }; 250 251 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) 252 { 253 return object_class_by_name(TYPE_MICROBLAZE_CPU); 254 } 255 256 static void mb_cpu_class_init(ObjectClass *oc, void *data) 257 { 258 DeviceClass *dc = DEVICE_CLASS(oc); 259 CPUClass *cc = CPU_CLASS(oc); 260 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); 261 262 device_class_set_parent_realize(dc, mb_cpu_realizefn, 263 &mcc->parent_realize); 264 mcc->parent_reset = cc->reset; 265 cc->reset = mb_cpu_reset; 266 267 cc->class_by_name = mb_cpu_class_by_name; 268 cc->has_work = mb_cpu_has_work; 269 cc->do_interrupt = mb_cpu_do_interrupt; 270 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; 271 cc->dump_state = mb_cpu_dump_state; 272 cc->set_pc = mb_cpu_set_pc; 273 cc->gdb_read_register = mb_cpu_gdb_read_register; 274 cc->gdb_write_register = mb_cpu_gdb_write_register; 275 #ifdef CONFIG_USER_ONLY 276 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; 277 #else 278 cc->do_unassigned_access = mb_cpu_unassigned_access; 279 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; 280 #endif 281 dc->vmsd = &vmstate_mb_cpu; 282 dc->props = mb_properties; 283 cc->gdb_num_core_regs = 32 + 5; 284 285 cc->disas_set_info = mb_disas_set_info; 286 cc->tcg_initialize = mb_tcg_init; 287 } 288 289 static const TypeInfo mb_cpu_type_info = { 290 .name = TYPE_MICROBLAZE_CPU, 291 .parent = TYPE_CPU, 292 .instance_size = sizeof(MicroBlazeCPU), 293 .instance_init = mb_cpu_initfn, 294 .class_size = sizeof(MicroBlazeCPUClass), 295 .class_init = mb_cpu_class_init, 296 }; 297 298 static void mb_cpu_register_types(void) 299 { 300 type_register_static(&mb_cpu_type_info); 301 } 302 303 type_init(mb_cpu_register_types) 304