1 /* 2 * QEMU MicroBlaze CPU 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * Copyright (c) 2012 SUSE LINUX Products GmbH 7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "qapi/error.h" 27 #include "cpu.h" 28 #include "qemu/module.h" 29 #include "hw/qdev-properties.h" 30 #include "exec/exec-all.h" 31 #include "exec/gdbstub.h" 32 #include "fpu/softfloat-helpers.h" 33 #include "tcg/tcg.h" 34 35 static const struct { 36 const char *name; 37 uint8_t version_id; 38 } mb_cpu_lookup[] = { 39 /* These key value are as per MBV field in PVR0 */ 40 {"5.00.a", 0x01}, 41 {"5.00.b", 0x02}, 42 {"5.00.c", 0x03}, 43 {"6.00.a", 0x04}, 44 {"6.00.b", 0x06}, 45 {"7.00.a", 0x05}, 46 {"7.00.b", 0x07}, 47 {"7.10.a", 0x08}, 48 {"7.10.b", 0x09}, 49 {"7.10.c", 0x0a}, 50 {"7.10.d", 0x0b}, 51 {"7.20.a", 0x0c}, 52 {"7.20.b", 0x0d}, 53 {"7.20.c", 0x0e}, 54 {"7.20.d", 0x0f}, 55 {"7.30.a", 0x10}, 56 {"7.30.b", 0x11}, 57 {"8.00.a", 0x12}, 58 {"8.00.b", 0x13}, 59 {"8.10.a", 0x14}, 60 {"8.20.a", 0x15}, 61 {"8.20.b", 0x16}, 62 {"8.30.a", 0x17}, 63 {"8.40.a", 0x18}, 64 {"8.40.b", 0x19}, 65 {"8.50.a", 0x1A}, 66 {"9.0", 0x1B}, 67 {"9.1", 0x1D}, 68 {"9.2", 0x1F}, 69 {"9.3", 0x20}, 70 {"9.4", 0x21}, 71 {"9.5", 0x22}, 72 {"9.6", 0x23}, 73 {"10.0", 0x24}, 74 {NULL, 0}, 75 }; 76 77 /* If no specific version gets selected, default to the following. */ 78 #define DEFAULT_CPU_VERSION "10.0" 79 80 static void mb_cpu_set_pc(CPUState *cs, vaddr value) 81 { 82 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 83 84 cpu->env.pc = value; 85 /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */ 86 cpu->env.iflags = 0; 87 } 88 89 static vaddr mb_cpu_get_pc(CPUState *cs) 90 { 91 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 92 93 return cpu->env.pc; 94 } 95 96 static void mb_cpu_synchronize_from_tb(CPUState *cs, 97 const TranslationBlock *tb) 98 { 99 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 100 101 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 102 cpu->env.pc = tb->pc; 103 cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; 104 } 105 106 static void mb_restore_state_to_opc(CPUState *cs, 107 const TranslationBlock *tb, 108 const uint64_t *data) 109 { 110 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 111 112 cpu->env.pc = data[0]; 113 cpu->env.iflags = data[1]; 114 } 115 116 static bool mb_cpu_has_work(CPUState *cs) 117 { 118 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 119 } 120 121 static int mb_cpu_mmu_index(CPUState *cs, bool ifetch) 122 { 123 CPUMBState *env = cpu_env(cs); 124 MicroBlazeCPU *cpu = env_archcpu(env); 125 126 /* Are we in nommu mode?. */ 127 if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { 128 return MMU_NOMMU_IDX; 129 } 130 131 if (env->msr & MSR_UM) { 132 return MMU_USER_IDX; 133 } 134 return MMU_KERNEL_IDX; 135 } 136 137 #ifndef CONFIG_USER_ONLY 138 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) 139 { 140 MicroBlazeCPU *cpu = opaque; 141 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; 142 143 cpu->ns_axi_dp = level & en; 144 } 145 146 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) 147 { 148 MicroBlazeCPU *cpu = opaque; 149 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; 150 151 cpu->ns_axi_ip = level & en; 152 } 153 154 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) 155 { 156 MicroBlazeCPU *cpu = opaque; 157 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; 158 159 cpu->ns_axi_dc = level & en; 160 } 161 162 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) 163 { 164 MicroBlazeCPU *cpu = opaque; 165 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; 166 167 cpu->ns_axi_ic = level & en; 168 } 169 170 static void microblaze_cpu_set_irq(void *opaque, int irq, int level) 171 { 172 MicroBlazeCPU *cpu = opaque; 173 CPUState *cs = CPU(cpu); 174 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; 175 176 if (level) { 177 cpu_interrupt(cs, type); 178 } else { 179 cpu_reset_interrupt(cs, type); 180 } 181 } 182 #endif 183 184 static void mb_cpu_reset_hold(Object *obj) 185 { 186 CPUState *cs = CPU(obj); 187 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 188 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj); 189 CPUMBState *env = &cpu->env; 190 191 if (mcc->parent_phases.hold) { 192 mcc->parent_phases.hold(obj); 193 } 194 195 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); 196 env->res_addr = RES_ADDR_NONE; 197 198 /* Disable stack protector. */ 199 env->shr = ~0; 200 201 env->pc = cpu->cfg.base_vectors; 202 203 #if defined(CONFIG_USER_ONLY) 204 /* start in user mode with interrupts enabled. */ 205 mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); 206 #else 207 mb_cpu_write_msr(env, 0); 208 mmu_init(&env->mmu); 209 #endif 210 } 211 212 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) 213 { 214 info->mach = bfd_arch_microblaze; 215 info->print_insn = print_insn_microblaze; 216 } 217 218 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 219 { 220 CPUState *cs = CPU(dev); 221 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); 222 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 223 uint8_t version_code = 0; 224 const char *version; 225 int i = 0; 226 Error *local_err = NULL; 227 228 cpu_exec_realizefn(cs, &local_err); 229 if (local_err != NULL) { 230 error_propagate(errp, local_err); 231 return; 232 } 233 234 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) { 235 error_setg(errp, "addr-size %d is out of range (32 - 64)", 236 cpu->cfg.addr_size); 237 return; 238 } 239 240 qemu_init_vcpu(cs); 241 242 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; 243 for (i = 0; mb_cpu_lookup[i].name && version; i++) { 244 if (strcmp(mb_cpu_lookup[i].name, version) == 0) { 245 version_code = mb_cpu_lookup[i].version_id; 246 break; 247 } 248 } 249 250 if (!version_code) { 251 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); 252 } 253 254 cpu->cfg.pvr_regs[0] = 255 (PVR0_USE_EXC_MASK | 256 PVR0_USE_ICACHE_MASK | 257 PVR0_USE_DCACHE_MASK | 258 (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | 259 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | 260 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | 261 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | 262 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | 263 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | 264 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | 265 (version_code << PVR0_VERSION_SHIFT) | 266 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | 267 cpu->cfg.pvr_user1); 268 269 cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2; 270 271 cpu->cfg.pvr_regs[2] = 272 (PVR2_D_OPB_MASK | 273 PVR2_D_LMB_MASK | 274 PVR2_I_OPB_MASK | 275 PVR2_I_LMB_MASK | 276 PVR2_FPU_EXC_MASK | 277 (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | 278 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | 279 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | 280 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | 281 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | 282 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | 283 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | 284 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | 285 (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | 286 (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | 287 (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) | 288 (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) | 289 (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) | 290 (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0)); 291 292 cpu->cfg.pvr_regs[5] |= 293 cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; 294 295 cpu->cfg.pvr_regs[10] = 296 (0x0c000000 | /* Default to spartan 3a dsp family. */ 297 (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT); 298 299 cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | 300 16 << 17); 301 302 cpu->cfg.mmu = 3; 303 cpu->cfg.mmu_tlb_access = 3; 304 cpu->cfg.mmu_zones = 16; 305 cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size); 306 307 mcc->parent_realize(dev, errp); 308 } 309 310 static void mb_cpu_initfn(Object *obj) 311 { 312 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); 313 CPUMBState *env = &cpu->env; 314 315 gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, 316 mb_cpu_gdb_write_stack_protect, 317 gdb_find_static_feature("microblaze-stack-protect.xml"), 318 0); 319 320 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 321 322 #ifndef CONFIG_USER_ONLY 323 /* Inbound IRQ and FIR lines */ 324 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); 325 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); 326 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); 327 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); 328 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); 329 #endif 330 } 331 332 static Property mb_properties[] = { 333 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), 334 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, 335 false), 336 /* 337 * This is the C_ADDR_SIZE synth-time configuration option of the 338 * MicroBlaze cores. Supported values range between 32 and 64. 339 * 340 * When set to > 32, 32bit MicroBlaze can emit load/stores 341 * with extended addressing. 342 */ 343 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32), 344 /* If use-fpu > 0 - FPU is enabled 345 * If use-fpu = 2 - Floating point conversion and square root instructions 346 * are enabled 347 */ 348 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), 349 /* If use-hw-mul > 0 - Multiplier is enabled 350 * If use-hw-mul = 2 - 64-bit multiplier is enabled 351 */ 352 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), 353 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), 354 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), 355 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), 356 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), 357 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), 358 /* 359 * use-non-secure enables/disables the use of the non_secure[3:0] signals. 360 * It is a bitfield where 1 = non-secure for the following bits and their 361 * corresponding interfaces: 362 * 0x1 - M_AXI_DP 363 * 0x2 - M_AXI_IP 364 * 0x4 - M_AXI_DC 365 * 0x8 - M_AXI_IC 366 */ 367 DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0), 368 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, 369 false), 370 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), 371 /* Enables bus exceptions on failed data accesses (load/stores). */ 372 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU, 373 cfg.dopb_bus_exception, false), 374 /* Enables bus exceptions on failed instruction fetches. */ 375 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, 376 cfg.iopb_bus_exception, false), 377 DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU, 378 cfg.illegal_opcode_exception, false), 379 DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU, 380 cfg.div_zero_exception, false), 381 DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU, 382 cfg.unaligned_exceptions, false), 383 DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, 384 cfg.opcode_0_illegal, false), 385 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), 386 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), 387 DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0), 388 DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0), 389 DEFINE_PROP_END_OF_LIST(), 390 }; 391 392 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) 393 { 394 return object_class_by_name(TYPE_MICROBLAZE_CPU); 395 } 396 397 #ifndef CONFIG_USER_ONLY 398 #include "hw/core/sysemu-cpu-ops.h" 399 400 static const struct SysemuCPUOps mb_sysemu_ops = { 401 .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug, 402 }; 403 #endif 404 405 #include "hw/core/tcg-cpu-ops.h" 406 407 static const TCGCPUOps mb_tcg_ops = { 408 .initialize = mb_tcg_init, 409 .synchronize_from_tb = mb_cpu_synchronize_from_tb, 410 .restore_state_to_opc = mb_restore_state_to_opc, 411 412 #ifndef CONFIG_USER_ONLY 413 .tlb_fill = mb_cpu_tlb_fill, 414 .cpu_exec_interrupt = mb_cpu_exec_interrupt, 415 .do_interrupt = mb_cpu_do_interrupt, 416 .do_transaction_failed = mb_cpu_transaction_failed, 417 .do_unaligned_access = mb_cpu_do_unaligned_access, 418 #endif /* !CONFIG_USER_ONLY */ 419 }; 420 421 static void mb_cpu_class_init(ObjectClass *oc, void *data) 422 { 423 DeviceClass *dc = DEVICE_CLASS(oc); 424 CPUClass *cc = CPU_CLASS(oc); 425 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); 426 ResettableClass *rc = RESETTABLE_CLASS(oc); 427 428 device_class_set_parent_realize(dc, mb_cpu_realizefn, 429 &mcc->parent_realize); 430 resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL, 431 &mcc->parent_phases); 432 433 cc->class_by_name = mb_cpu_class_by_name; 434 cc->has_work = mb_cpu_has_work; 435 cc->mmu_index = mb_cpu_mmu_index; 436 cc->dump_state = mb_cpu_dump_state; 437 cc->set_pc = mb_cpu_set_pc; 438 cc->get_pc = mb_cpu_get_pc; 439 cc->gdb_read_register = mb_cpu_gdb_read_register; 440 cc->gdb_write_register = mb_cpu_gdb_write_register; 441 442 #ifndef CONFIG_USER_ONLY 443 dc->vmsd = &vmstate_mb_cpu; 444 cc->sysemu_ops = &mb_sysemu_ops; 445 #endif 446 device_class_set_props(dc, mb_properties); 447 cc->gdb_core_xml_file = "microblaze-core.xml"; 448 449 cc->disas_set_info = mb_disas_set_info; 450 cc->tcg_ops = &mb_tcg_ops; 451 } 452 453 static const TypeInfo mb_cpu_type_info = { 454 .name = TYPE_MICROBLAZE_CPU, 455 .parent = TYPE_CPU, 456 .instance_size = sizeof(MicroBlazeCPU), 457 .instance_align = __alignof(MicroBlazeCPU), 458 .instance_init = mb_cpu_initfn, 459 .class_size = sizeof(MicroBlazeCPUClass), 460 .class_init = mb_cpu_class_init, 461 }; 462 463 static void mb_cpu_register_types(void) 464 { 465 type_register_static(&mb_cpu_type_info); 466 } 467 468 type_init(mb_cpu_register_types) 469