xref: /openbmc/qemu/target/microblaze/cpu.c (revision 84307cd6027c4602913177ff09aeefa4743b7234) 
1 /*
2  * QEMU MicroBlaze CPU
3  *
4  * Copyright (c) 2009 Edgar E. Iglesias
5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6  * Copyright (c) 2012 SUSE LINUX Products GmbH
7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8  *
9  * This library is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU Lesser General Public
11  * License as published by the Free Software Foundation; either
12  * version 2.1 of the License, or (at your option) any later version.
13  *
14  * This library is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17  * Lesser General Public License for more details.
18  *
19  * You should have received a copy of the GNU Lesser General Public
20  * License along with this library; if not, see
21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
22  */
23 
24 #include "qemu/osdep.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "cpu.h"
28 #include "qemu/module.h"
29 #include "hw/qdev-properties.h"
30 #include "accel/tcg/cpu-ldst.h"
31 #include "exec/gdbstub.h"
32 #include "exec/translation-block.h"
33 #include "fpu/softfloat-helpers.h"
34 #include "tcg/tcg.h"
35 
36 static const struct {
37     const char *name;
38     uint8_t version_id;
39 } mb_cpu_lookup[] = {
40     /* These key value are as per MBV field in PVR0 */
41     {"5.00.a", 0x01},
42     {"5.00.b", 0x02},
43     {"5.00.c", 0x03},
44     {"6.00.a", 0x04},
45     {"6.00.b", 0x06},
46     {"7.00.a", 0x05},
47     {"7.00.b", 0x07},
48     {"7.10.a", 0x08},
49     {"7.10.b", 0x09},
50     {"7.10.c", 0x0a},
51     {"7.10.d", 0x0b},
52     {"7.20.a", 0x0c},
53     {"7.20.b", 0x0d},
54     {"7.20.c", 0x0e},
55     {"7.20.d", 0x0f},
56     {"7.30.a", 0x10},
57     {"7.30.b", 0x11},
58     {"8.00.a", 0x12},
59     {"8.00.b", 0x13},
60     {"8.10.a", 0x14},
61     {"8.20.a", 0x15},
62     {"8.20.b", 0x16},
63     {"8.30.a", 0x17},
64     {"8.40.a", 0x18},
65     {"8.40.b", 0x19},
66     {"8.50.a", 0x1A},
67     {"9.0", 0x1B},
68     {"9.1", 0x1D},
69     {"9.2", 0x1F},
70     {"9.3", 0x20},
71     {"9.4", 0x21},
72     {"9.5", 0x22},
73     {"9.6", 0x23},
74     {"10.0", 0x24},
75     {NULL, 0},
76 };
77 
78 /* If no specific version gets selected, default to the following.  */
79 #define DEFAULT_CPU_VERSION "10.0"
80 
81 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
82 {
83     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
84 
85     cpu->env.pc = value;
86     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
87     cpu->env.iflags = 0;
88 }
89 
90 static vaddr mb_cpu_get_pc(CPUState *cs)
91 {
92     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
93 
94     return cpu->env.pc;
95 }
96 
97 static void mb_cpu_synchronize_from_tb(CPUState *cs,
98                                        const TranslationBlock *tb)
99 {
100     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
101 
102     tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
103     cpu->env.pc = tb->pc;
104     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
105 }
106 
107 static void mb_restore_state_to_opc(CPUState *cs,
108                                     const TranslationBlock *tb,
109                                     const uint64_t *data)
110 {
111     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
112 
113     cpu->env.pc = data[0];
114     cpu->env.iflags = data[1];
115 }
116 
117 #ifndef CONFIG_USER_ONLY
118 static bool mb_cpu_has_work(CPUState *cs)
119 {
120     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
121 }
122 #endif /* !CONFIG_USER_ONLY */
123 
124 static int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
125 {
126     CPUMBState *env = cpu_env(cs);
127     MicroBlazeCPU *cpu = env_archcpu(env);
128 
129     /* Are we in nommu mode?.  */
130     if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
131         return MMU_NOMMU_IDX;
132     }
133 
134     if (env->msr & MSR_UM) {
135         return MMU_USER_IDX;
136     }
137     return MMU_KERNEL_IDX;
138 }
139 
140 #ifndef CONFIG_USER_ONLY
141 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
142 {
143     MicroBlazeCPU *cpu = opaque;
144     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
145 
146     cpu->ns_axi_dp = level & en;
147 }
148 
149 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
150 {
151     MicroBlazeCPU *cpu = opaque;
152     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
153 
154     cpu->ns_axi_ip = level & en;
155 }
156 
157 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
158 {
159     MicroBlazeCPU *cpu = opaque;
160     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
161 
162     cpu->ns_axi_dc = level & en;
163 }
164 
165 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
166 {
167     MicroBlazeCPU *cpu = opaque;
168     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
169 
170     cpu->ns_axi_ic = level & en;
171 }
172 
173 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
174 {
175     MicroBlazeCPU *cpu = opaque;
176     CPUState *cs = CPU(cpu);
177     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
178 
179     if (level) {
180         cpu_interrupt(cs, type);
181     } else {
182         cpu_reset_interrupt(cs, type);
183     }
184 }
185 #endif
186 
187 static void mb_cpu_reset_hold(Object *obj, ResetType type)
188 {
189     CPUState *cs = CPU(obj);
190     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
191     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj);
192     CPUMBState *env = &cpu->env;
193 
194     if (mcc->parent_phases.hold) {
195         mcc->parent_phases.hold(obj, type);
196     }
197 
198     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
199     env->res_addr = RES_ADDR_NONE;
200 
201     /* Disable stack protector.  */
202     env->shr = ~0;
203 
204     env->pc = cpu->cfg.base_vectors;
205 
206     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
207     /*
208      * TODO: this is probably not the correct NaN propagation rule for
209      * this architecture.
210      */
211     set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
212     /* Default NaN: sign bit set, most significant frac bit set */
213     set_float_default_nan_pattern(0b11000000, &env->fp_status);
214 
215 #if defined(CONFIG_USER_ONLY)
216     /* start in user mode with interrupts enabled.  */
217     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
218 #else
219     mb_cpu_write_msr(env, 0);
220     mmu_init(&env->mmu);
221 #endif
222 }
223 
224 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
225 {
226     info->mach = bfd_arch_microblaze;
227     info->print_insn = print_insn_microblaze;
228     info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
229                                      : BFD_ENDIAN_LITTLE;
230 }
231 
232 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
233 {
234     CPUState *cs = CPU(dev);
235     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
236     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
237     uint8_t version_code = 0;
238     const char *version;
239     int i = 0;
240     Error *local_err = NULL;
241 
242     cpu_exec_realizefn(cs, &local_err);
243     if (local_err != NULL) {
244         error_propagate(errp, local_err);
245         return;
246     }
247 
248     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
249         error_setg(errp, "addr-size %d is out of range (32 - 64)",
250                    cpu->cfg.addr_size);
251         return;
252     }
253 
254     qemu_init_vcpu(cs);
255 
256     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
257     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
258         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
259             version_code = mb_cpu_lookup[i].version_id;
260             break;
261         }
262     }
263 
264     if (!version_code) {
265         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
266     }
267 
268     cpu->cfg.pvr_regs[0] =
269         (PVR0_USE_EXC_MASK |
270          PVR0_USE_ICACHE_MASK |
271          PVR0_USE_DCACHE_MASK |
272          (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
273          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
274          (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
275          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
276          (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
277          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
278          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
279          (version_code << PVR0_VERSION_SHIFT) |
280          (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
281          cpu->cfg.pvr_user1);
282 
283     cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
284 
285     cpu->cfg.pvr_regs[2] =
286         (PVR2_D_OPB_MASK |
287          PVR2_D_LMB_MASK |
288          PVR2_I_OPB_MASK |
289          PVR2_I_LMB_MASK |
290          PVR2_FPU_EXC_MASK |
291          (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
292          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
293          (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
294          (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
295          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
296          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
297          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
298          (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
299          (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
300          (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
301          (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
302          (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
303          (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
304          (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
305 
306     cpu->cfg.pvr_regs[5] |=
307         cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
308 
309     cpu->cfg.pvr_regs[10] =
310         (0x0c000000 | /* Default to spartan 3a dsp family.  */
311          (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
312 
313     cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
314                              16 << 17);
315 
316     cpu->cfg.mmu = 3;
317     cpu->cfg.mmu_tlb_access = 3;
318     cpu->cfg.mmu_zones = 16;
319     cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
320 
321     mcc->parent_realize(dev, errp);
322 }
323 
324 static void mb_cpu_initfn(Object *obj)
325 {
326     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
327 
328     gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
329                              mb_cpu_gdb_write_stack_protect,
330                              gdb_find_static_feature("microblaze-stack-protect.xml"),
331                              0);
332 
333 #ifndef CONFIG_USER_ONLY
334     /* Inbound IRQ and FIR lines */
335     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
336     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
337     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
338     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
339     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
340 #endif
341 
342     /* Restricted 'endianness' property is equivalent of 'little-endian' */
343     object_property_add_alias(obj, "little-endian", obj, "endianness");
344 }
345 
346 static const Property mb_properties[] = {
347     /*
348      * Following properties are used by Xilinx DTS conversion tool
349      * do not rename them.
350      */
351     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
352     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
353                      false),
354     /*
355      * This is the C_ADDR_SIZE synth-time configuration option of the
356      * MicroBlaze cores. Supported values range between 32 and 64.
357      *
358      * When set to > 32, 32bit MicroBlaze can emit load/stores
359      * with extended addressing.
360      */
361     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
362     /* If use-fpu > 0 - FPU is enabled
363      * If use-fpu = 2 - Floating point conversion and square root instructions
364      *                  are enabled
365      */
366     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
367     /* If use-hw-mul > 0 - Multiplier is enabled
368      * If use-hw-mul = 2 - 64-bit multiplier is enabled
369      */
370     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
371     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
372     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
373     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
374     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
375     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
376     /*
377      * use-non-secure enables/disables the use of the non_secure[3:0] signals.
378      * It is a bitfield where 1 = non-secure for the following bits and their
379      * corresponding interfaces:
380      * 0x1 - M_AXI_DP
381      * 0x2 - M_AXI_IP
382      * 0x4 - M_AXI_DC
383      * 0x8 - M_AXI_IC
384      */
385     DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
386     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
387                      false),
388     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
389     /* Enables bus exceptions on failed data accesses (load/stores).  */
390     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
391                      cfg.dopb_bus_exception, false),
392     /* Enables bus exceptions on failed instruction fetches.  */
393     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
394                      cfg.iopb_bus_exception, false),
395     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
396                      cfg.illegal_opcode_exception, false),
397     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
398                      cfg.div_zero_exception, false),
399     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
400                      cfg.unaligned_exceptions, false),
401     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
402                      cfg.opcode_0_illegal, false),
403     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
404     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
405     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
406     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
407     /*
408      * End of properties reserved by Xilinx DTS conversion tool.
409      */
410 };
411 
412 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
413 {
414     return object_class_by_name(TYPE_MICROBLAZE_CPU);
415 }
416 
417 #ifndef CONFIG_USER_ONLY
418 #include "hw/core/sysemu-cpu-ops.h"
419 
420 static const struct SysemuCPUOps mb_sysemu_ops = {
421     .has_work = mb_cpu_has_work,
422     .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
423 };
424 #endif
425 
426 #include "accel/tcg/cpu-ops.h"
427 
428 static const TCGCPUOps mb_tcg_ops = {
429     /* MicroBlaze is always in-order. */
430     .guest_default_memory_order = TCG_MO_ALL,
431     .mttcg_supported = true,
432 
433     .initialize = mb_tcg_init,
434     .translate_code = mb_translate_code,
435     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
436     .restore_state_to_opc = mb_restore_state_to_opc,
437     .mmu_index = mb_cpu_mmu_index,
438 
439 #ifndef CONFIG_USER_ONLY
440     .tlb_fill = mb_cpu_tlb_fill,
441     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
442     .cpu_exec_halt = mb_cpu_has_work,
443     .do_interrupt = mb_cpu_do_interrupt,
444     .do_transaction_failed = mb_cpu_transaction_failed,
445     .do_unaligned_access = mb_cpu_do_unaligned_access,
446 #endif /* !CONFIG_USER_ONLY */
447 };
448 
449 static void mb_cpu_class_init(ObjectClass *oc, const void *data)
450 {
451     DeviceClass *dc = DEVICE_CLASS(oc);
452     CPUClass *cc = CPU_CLASS(oc);
453     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
454     ResettableClass *rc = RESETTABLE_CLASS(oc);
455 
456     device_class_set_parent_realize(dc, mb_cpu_realizefn,
457                                     &mcc->parent_realize);
458     resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
459                                        &mcc->parent_phases);
460 
461     cc->class_by_name = mb_cpu_class_by_name;
462     cc->dump_state = mb_cpu_dump_state;
463     cc->set_pc = mb_cpu_set_pc;
464     cc->get_pc = mb_cpu_get_pc;
465     cc->gdb_read_register = mb_cpu_gdb_read_register;
466     cc->gdb_write_register = mb_cpu_gdb_write_register;
467 
468 #ifndef CONFIG_USER_ONLY
469     dc->vmsd = &vmstate_mb_cpu;
470     cc->sysemu_ops = &mb_sysemu_ops;
471 #endif
472     device_class_set_props(dc, mb_properties);
473     cc->gdb_core_xml_file = "microblaze-core.xml";
474 
475     cc->disas_set_info = mb_disas_set_info;
476     cc->tcg_ops = &mb_tcg_ops;
477 }
478 
479 static const TypeInfo mb_cpu_type_info = {
480     .name = TYPE_MICROBLAZE_CPU,
481     .parent = TYPE_CPU,
482     .instance_size = sizeof(MicroBlazeCPU),
483     .instance_align = __alignof(MicroBlazeCPU),
484     .instance_init = mb_cpu_initfn,
485     .class_size = sizeof(MicroBlazeCPUClass),
486     .class_init = mb_cpu_class_init,
487 };
488 
489 static void mb_cpu_register_types(void)
490 {
491     type_register_static(&mb_cpu_type_info);
492 }
493 
494 type_init(mb_cpu_register_types)
495