1 /* 2 * QEMU MicroBlaze CPU 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * Copyright (c) 2012 SUSE LINUX Products GmbH 7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "qapi/error.h" 27 #include "cpu.h" 28 #include "qemu/module.h" 29 #include "hw/qdev-properties.h" 30 #include "exec/exec-all.h" 31 #include "exec/gdbstub.h" 32 #include "fpu/softfloat-helpers.h" 33 34 static const struct { 35 const char *name; 36 uint8_t version_id; 37 } mb_cpu_lookup[] = { 38 /* These key value are as per MBV field in PVR0 */ 39 {"5.00.a", 0x01}, 40 {"5.00.b", 0x02}, 41 {"5.00.c", 0x03}, 42 {"6.00.a", 0x04}, 43 {"6.00.b", 0x06}, 44 {"7.00.a", 0x05}, 45 {"7.00.b", 0x07}, 46 {"7.10.a", 0x08}, 47 {"7.10.b", 0x09}, 48 {"7.10.c", 0x0a}, 49 {"7.10.d", 0x0b}, 50 {"7.20.a", 0x0c}, 51 {"7.20.b", 0x0d}, 52 {"7.20.c", 0x0e}, 53 {"7.20.d", 0x0f}, 54 {"7.30.a", 0x10}, 55 {"7.30.b", 0x11}, 56 {"8.00.a", 0x12}, 57 {"8.00.b", 0x13}, 58 {"8.10.a", 0x14}, 59 {"8.20.a", 0x15}, 60 {"8.20.b", 0x16}, 61 {"8.30.a", 0x17}, 62 {"8.40.a", 0x18}, 63 {"8.40.b", 0x19}, 64 {"8.50.a", 0x1A}, 65 {"9.0", 0x1B}, 66 {"9.1", 0x1D}, 67 {"9.2", 0x1F}, 68 {"9.3", 0x20}, 69 {"9.4", 0x21}, 70 {"9.5", 0x22}, 71 {"9.6", 0x23}, 72 {"10.0", 0x24}, 73 {NULL, 0}, 74 }; 75 76 /* If no specific version gets selected, default to the following. */ 77 #define DEFAULT_CPU_VERSION "10.0" 78 79 static void mb_cpu_set_pc(CPUState *cs, vaddr value) 80 { 81 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 82 83 cpu->env.pc = value; 84 /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */ 85 cpu->env.iflags = 0; 86 } 87 88 static vaddr mb_cpu_get_pc(CPUState *cs) 89 { 90 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 91 92 return cpu->env.pc; 93 } 94 95 static void mb_cpu_synchronize_from_tb(CPUState *cs, 96 const TranslationBlock *tb) 97 { 98 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 99 100 cpu->env.pc = tb_pc(tb); 101 cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; 102 } 103 104 static void mb_restore_state_to_opc(CPUState *cs, 105 const TranslationBlock *tb, 106 const uint64_t *data) 107 { 108 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 109 110 cpu->env.pc = data[0]; 111 cpu->env.iflags = data[1]; 112 } 113 114 static bool mb_cpu_has_work(CPUState *cs) 115 { 116 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 117 } 118 119 #ifndef CONFIG_USER_ONLY 120 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) 121 { 122 MicroBlazeCPU *cpu = opaque; 123 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; 124 125 cpu->ns_axi_dp = level & en; 126 } 127 128 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) 129 { 130 MicroBlazeCPU *cpu = opaque; 131 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; 132 133 cpu->ns_axi_ip = level & en; 134 } 135 136 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) 137 { 138 MicroBlazeCPU *cpu = opaque; 139 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; 140 141 cpu->ns_axi_dc = level & en; 142 } 143 144 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) 145 { 146 MicroBlazeCPU *cpu = opaque; 147 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; 148 149 cpu->ns_axi_ic = level & en; 150 } 151 152 static void microblaze_cpu_set_irq(void *opaque, int irq, int level) 153 { 154 MicroBlazeCPU *cpu = opaque; 155 CPUState *cs = CPU(cpu); 156 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; 157 158 if (level) { 159 cpu_interrupt(cs, type); 160 } else { 161 cpu_reset_interrupt(cs, type); 162 } 163 } 164 #endif 165 166 static void mb_cpu_reset_hold(Object *obj) 167 { 168 CPUState *s = CPU(obj); 169 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); 170 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); 171 CPUMBState *env = &cpu->env; 172 173 if (mcc->parent_phases.hold) { 174 mcc->parent_phases.hold(obj); 175 } 176 177 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); 178 env->res_addr = RES_ADDR_NONE; 179 180 /* Disable stack protector. */ 181 env->shr = ~0; 182 183 env->pc = cpu->cfg.base_vectors; 184 185 #if defined(CONFIG_USER_ONLY) 186 /* start in user mode with interrupts enabled. */ 187 mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); 188 #else 189 mb_cpu_write_msr(env, 0); 190 mmu_init(&env->mmu); 191 #endif 192 } 193 194 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) 195 { 196 info->mach = bfd_arch_microblaze; 197 info->print_insn = print_insn_microblaze; 198 } 199 200 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 201 { 202 CPUState *cs = CPU(dev); 203 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); 204 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 205 uint8_t version_code = 0; 206 const char *version; 207 int i = 0; 208 Error *local_err = NULL; 209 210 cpu_exec_realizefn(cs, &local_err); 211 if (local_err != NULL) { 212 error_propagate(errp, local_err); 213 return; 214 } 215 216 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) { 217 error_setg(errp, "addr-size %d is out of range (32 - 64)", 218 cpu->cfg.addr_size); 219 return; 220 } 221 222 qemu_init_vcpu(cs); 223 224 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; 225 for (i = 0; mb_cpu_lookup[i].name && version; i++) { 226 if (strcmp(mb_cpu_lookup[i].name, version) == 0) { 227 version_code = mb_cpu_lookup[i].version_id; 228 break; 229 } 230 } 231 232 if (!version_code) { 233 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); 234 } 235 236 cpu->cfg.pvr_regs[0] = 237 (PVR0_USE_EXC_MASK | 238 PVR0_USE_ICACHE_MASK | 239 PVR0_USE_DCACHE_MASK | 240 (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | 241 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | 242 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | 243 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | 244 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | 245 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | 246 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | 247 (version_code << PVR0_VERSION_SHIFT) | 248 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | 249 cpu->cfg.pvr_user1); 250 251 cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2; 252 253 cpu->cfg.pvr_regs[2] = 254 (PVR2_D_OPB_MASK | 255 PVR2_D_LMB_MASK | 256 PVR2_I_OPB_MASK | 257 PVR2_I_LMB_MASK | 258 PVR2_FPU_EXC_MASK | 259 (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | 260 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | 261 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | 262 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | 263 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | 264 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | 265 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | 266 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | 267 (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | 268 (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | 269 (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) | 270 (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) | 271 (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) | 272 (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0)); 273 274 cpu->cfg.pvr_regs[5] |= 275 cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; 276 277 cpu->cfg.pvr_regs[10] = 278 (0x0c000000 | /* Default to spartan 3a dsp family. */ 279 (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT); 280 281 cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | 282 16 << 17); 283 284 cpu->cfg.mmu = 3; 285 cpu->cfg.mmu_tlb_access = 3; 286 cpu->cfg.mmu_zones = 16; 287 cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size); 288 289 mcc->parent_realize(dev, errp); 290 } 291 292 static void mb_cpu_initfn(Object *obj) 293 { 294 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); 295 CPUMBState *env = &cpu->env; 296 297 cpu_set_cpustate_pointers(cpu); 298 gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, 299 mb_cpu_gdb_write_stack_protect, 2, 300 "microblaze-stack-protect.xml", 0); 301 302 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 303 304 #ifndef CONFIG_USER_ONLY 305 /* Inbound IRQ and FIR lines */ 306 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); 307 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); 308 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); 309 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); 310 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); 311 #endif 312 } 313 314 static Property mb_properties[] = { 315 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), 316 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, 317 false), 318 /* 319 * This is the C_ADDR_SIZE synth-time configuration option of the 320 * MicroBlaze cores. Supported values range between 32 and 64. 321 * 322 * When set to > 32, 32bit MicroBlaze can emit load/stores 323 * with extended addressing. 324 */ 325 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32), 326 /* If use-fpu > 0 - FPU is enabled 327 * If use-fpu = 2 - Floating point conversion and square root instructions 328 * are enabled 329 */ 330 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), 331 /* If use-hw-mul > 0 - Multiplier is enabled 332 * If use-hw-mul = 2 - 64-bit multiplier is enabled 333 */ 334 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), 335 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), 336 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), 337 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), 338 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), 339 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), 340 /* 341 * use-non-secure enables/disables the use of the non_secure[3:0] signals. 342 * It is a bitfield where 1 = non-secure for the following bits and their 343 * corresponding interfaces: 344 * 0x1 - M_AXI_DP 345 * 0x2 - M_AXI_IP 346 * 0x4 - M_AXI_DC 347 * 0x8 - M_AXI_IC 348 */ 349 DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0), 350 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, 351 false), 352 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), 353 /* Enables bus exceptions on failed data accesses (load/stores). */ 354 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU, 355 cfg.dopb_bus_exception, false), 356 /* Enables bus exceptions on failed instruction fetches. */ 357 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, 358 cfg.iopb_bus_exception, false), 359 DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU, 360 cfg.illegal_opcode_exception, false), 361 DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU, 362 cfg.div_zero_exception, false), 363 DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU, 364 cfg.unaligned_exceptions, false), 365 DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, 366 cfg.opcode_0_illegal, false), 367 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), 368 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), 369 DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0), 370 DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0), 371 DEFINE_PROP_END_OF_LIST(), 372 }; 373 374 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) 375 { 376 return object_class_by_name(TYPE_MICROBLAZE_CPU); 377 } 378 379 #ifndef CONFIG_USER_ONLY 380 #include "hw/core/sysemu-cpu-ops.h" 381 382 static const struct SysemuCPUOps mb_sysemu_ops = { 383 .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug, 384 }; 385 #endif 386 387 #include "hw/core/tcg-cpu-ops.h" 388 389 static const struct TCGCPUOps mb_tcg_ops = { 390 .initialize = mb_tcg_init, 391 .synchronize_from_tb = mb_cpu_synchronize_from_tb, 392 .restore_state_to_opc = mb_restore_state_to_opc, 393 394 #ifndef CONFIG_USER_ONLY 395 .tlb_fill = mb_cpu_tlb_fill, 396 .cpu_exec_interrupt = mb_cpu_exec_interrupt, 397 .do_interrupt = mb_cpu_do_interrupt, 398 .do_transaction_failed = mb_cpu_transaction_failed, 399 .do_unaligned_access = mb_cpu_do_unaligned_access, 400 #endif /* !CONFIG_USER_ONLY */ 401 }; 402 403 static void mb_cpu_class_init(ObjectClass *oc, void *data) 404 { 405 DeviceClass *dc = DEVICE_CLASS(oc); 406 CPUClass *cc = CPU_CLASS(oc); 407 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); 408 ResettableClass *rc = RESETTABLE_CLASS(oc); 409 410 device_class_set_parent_realize(dc, mb_cpu_realizefn, 411 &mcc->parent_realize); 412 resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL, 413 &mcc->parent_phases); 414 415 cc->class_by_name = mb_cpu_class_by_name; 416 cc->has_work = mb_cpu_has_work; 417 418 cc->dump_state = mb_cpu_dump_state; 419 cc->set_pc = mb_cpu_set_pc; 420 cc->get_pc = mb_cpu_get_pc; 421 cc->gdb_read_register = mb_cpu_gdb_read_register; 422 cc->gdb_write_register = mb_cpu_gdb_write_register; 423 424 #ifndef CONFIG_USER_ONLY 425 dc->vmsd = &vmstate_mb_cpu; 426 cc->sysemu_ops = &mb_sysemu_ops; 427 #endif 428 device_class_set_props(dc, mb_properties); 429 cc->gdb_num_core_regs = 32 + 25; 430 cc->gdb_core_xml_file = "microblaze-core.xml"; 431 432 cc->disas_set_info = mb_disas_set_info; 433 cc->tcg_ops = &mb_tcg_ops; 434 } 435 436 static const TypeInfo mb_cpu_type_info = { 437 .name = TYPE_MICROBLAZE_CPU, 438 .parent = TYPE_CPU, 439 .instance_size = sizeof(MicroBlazeCPU), 440 .instance_init = mb_cpu_initfn, 441 .class_size = sizeof(MicroBlazeCPUClass), 442 .class_init = mb_cpu_class_init, 443 }; 444 445 static void mb_cpu_register_types(void) 446 { 447 type_register_static(&mb_cpu_type_info); 448 } 449 450 type_init(mb_cpu_register_types) 451