1 /* 2 * QEMU MicroBlaze CPU 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * Copyright (c) 2012 SUSE LINUX Products GmbH 7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "qemu-common.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "exec/exec-all.h" 31 32 static const struct { 33 const char *name; 34 uint8_t version_id; 35 } mb_cpu_lookup[] = { 36 /* These key value are as per MBV field in PVR0 */ 37 {"5.00.a", 0x01}, 38 {"5.00.b", 0x02}, 39 {"5.00.c", 0x03}, 40 {"6.00.a", 0x04}, 41 {"6.00.b", 0x06}, 42 {"7.00.a", 0x05}, 43 {"7.00.b", 0x07}, 44 {"7.10.a", 0x08}, 45 {"7.10.b", 0x09}, 46 {"7.10.c", 0x0a}, 47 {"7.10.d", 0x0b}, 48 {"7.20.a", 0x0c}, 49 {"7.20.b", 0x0d}, 50 {"7.20.c", 0x0e}, 51 {"7.20.d", 0x0f}, 52 {"7.30.a", 0x10}, 53 {"7.30.b", 0x11}, 54 {"8.00.a", 0x12}, 55 {"8.00.b", 0x13}, 56 {"8.10.a", 0x14}, 57 {"8.20.a", 0x15}, 58 {"8.20.b", 0x16}, 59 {"8.30.a", 0x17}, 60 {"8.40.a", 0x18}, 61 {"8.40.b", 0x19}, 62 {"8.50.a", 0x1A}, 63 {"9.0", 0x1B}, 64 {"9.1", 0x1D}, 65 {"9.2", 0x1F}, 66 {"9.3", 0x20}, 67 {NULL, 0}, 68 }; 69 70 static void mb_cpu_set_pc(CPUState *cs, vaddr value) 71 { 72 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 73 74 cpu->env.sregs[SR_PC] = value; 75 } 76 77 static bool mb_cpu_has_work(CPUState *cs) 78 { 79 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 80 } 81 82 #ifndef CONFIG_USER_ONLY 83 static void microblaze_cpu_set_irq(void *opaque, int irq, int level) 84 { 85 MicroBlazeCPU *cpu = opaque; 86 CPUState *cs = CPU(cpu); 87 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; 88 89 if (level) { 90 cpu_interrupt(cs, type); 91 } else { 92 cpu_reset_interrupt(cs, type); 93 } 94 } 95 #endif 96 97 /* CPUClass::reset() */ 98 static void mb_cpu_reset(CPUState *s) 99 { 100 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); 101 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); 102 CPUMBState *env = &cpu->env; 103 104 mcc->parent_reset(s); 105 106 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); 107 env->res_addr = RES_ADDR_NONE; 108 109 /* Disable stack protector. */ 110 env->shr = ~0; 111 112 env->sregs[SR_PC] = cpu->cfg.base_vectors; 113 114 #if defined(CONFIG_USER_ONLY) 115 /* start in user mode with interrupts enabled. */ 116 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; 117 #else 118 env->sregs[SR_MSR] = 0; 119 mmu_init(&env->mmu); 120 env->mmu.c_mmu = 3; 121 env->mmu.c_mmu_tlb_access = 3; 122 env->mmu.c_mmu_zones = 16; 123 #endif 124 } 125 126 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) 127 { 128 info->mach = bfd_arch_microblaze; 129 info->print_insn = print_insn_microblaze; 130 } 131 132 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 133 { 134 CPUState *cs = CPU(dev); 135 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); 136 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 137 CPUMBState *env = &cpu->env; 138 uint8_t version_code = 0; 139 int i = 0; 140 Error *local_err = NULL; 141 142 cpu_exec_realizefn(cs, &local_err); 143 if (local_err != NULL) { 144 error_propagate(errp, local_err); 145 return; 146 } 147 148 qemu_init_vcpu(cs); 149 150 env->pvr.regs[0] = PVR0_USE_BARREL_MASK \ 151 | PVR0_USE_DIV_MASK \ 152 | PVR0_USE_HW_MUL_MASK \ 153 | PVR0_USE_EXC_MASK \ 154 | PVR0_USE_ICACHE_MASK \ 155 | PVR0_USE_DCACHE_MASK \ 156 | (0xb << 8); 157 env->pvr.regs[2] = PVR2_D_OPB_MASK \ 158 | PVR2_D_LMB_MASK \ 159 | PVR2_I_OPB_MASK \ 160 | PVR2_I_LMB_MASK \ 161 | PVR2_USE_MSR_INSTR \ 162 | PVR2_USE_PCMP_INSTR \ 163 | PVR2_USE_BARREL_MASK \ 164 | PVR2_USE_DIV_MASK \ 165 | PVR2_USE_HW_MUL_MASK \ 166 | PVR2_USE_MUL64_MASK \ 167 | PVR2_FPU_EXC_MASK \ 168 | 0; 169 170 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) { 171 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) { 172 version_code = mb_cpu_lookup[i].version_id; 173 break; 174 } 175 } 176 177 if (!version_code) { 178 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); 179 } 180 181 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | 182 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | 183 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | 184 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | 185 (version_code << 16) | 186 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); 187 188 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | 189 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); 190 191 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? 192 PVR5_DCACHE_WRITEBACK_MASK : 0; 193 194 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ 195 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); 196 197 mcc->parent_realize(dev, errp); 198 } 199 200 static void mb_cpu_initfn(Object *obj) 201 { 202 CPUState *cs = CPU(obj); 203 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); 204 CPUMBState *env = &cpu->env; 205 static bool tcg_initialized; 206 207 cs->env_ptr = env; 208 209 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 210 211 #ifndef CONFIG_USER_ONLY 212 /* Inbound IRQ and FIR lines */ 213 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); 214 #endif 215 216 if (tcg_enabled() && !tcg_initialized) { 217 tcg_initialized = true; 218 mb_tcg_init(); 219 } 220 } 221 222 static const VMStateDescription vmstate_mb_cpu = { 223 .name = "cpu", 224 .unmigratable = 1, 225 }; 226 227 static Property mb_properties[] = { 228 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), 229 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, 230 false), 231 /* If use-fpu > 0 - FPU is enabled 232 * If use-fpu = 2 - Floating point conversion and square root instructions 233 * are enabled 234 */ 235 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), 236 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), 237 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, 238 false), 239 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), 240 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), 241 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), 242 DEFINE_PROP_END_OF_LIST(), 243 }; 244 245 static void mb_cpu_class_init(ObjectClass *oc, void *data) 246 { 247 DeviceClass *dc = DEVICE_CLASS(oc); 248 CPUClass *cc = CPU_CLASS(oc); 249 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); 250 251 mcc->parent_realize = dc->realize; 252 dc->realize = mb_cpu_realizefn; 253 254 mcc->parent_reset = cc->reset; 255 cc->reset = mb_cpu_reset; 256 257 cc->has_work = mb_cpu_has_work; 258 cc->do_interrupt = mb_cpu_do_interrupt; 259 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; 260 cc->dump_state = mb_cpu_dump_state; 261 cc->set_pc = mb_cpu_set_pc; 262 cc->gdb_read_register = mb_cpu_gdb_read_register; 263 cc->gdb_write_register = mb_cpu_gdb_write_register; 264 #ifdef CONFIG_USER_ONLY 265 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; 266 #else 267 cc->do_unassigned_access = mb_cpu_unassigned_access; 268 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; 269 #endif 270 dc->vmsd = &vmstate_mb_cpu; 271 dc->props = mb_properties; 272 cc->gdb_num_core_regs = 32 + 5; 273 274 cc->disas_set_info = mb_disas_set_info; 275 } 276 277 static const TypeInfo mb_cpu_type_info = { 278 .name = TYPE_MICROBLAZE_CPU, 279 .parent = TYPE_CPU, 280 .instance_size = sizeof(MicroBlazeCPU), 281 .instance_init = mb_cpu_initfn, 282 .class_size = sizeof(MicroBlazeCPUClass), 283 .class_init = mb_cpu_class_init, 284 }; 285 286 static void mb_cpu_register_types(void) 287 { 288 type_register_static(&mb_cpu_type_info); 289 } 290 291 type_init(mb_cpu_register_types) 292