1 /* 2 * m68k translation 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "disas/disas.h" 24 #include "exec/exec-all.h" 25 #include "tcg-op.h" 26 #include "qemu/log.h" 27 #include "exec/cpu_ldst.h" 28 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 #include "trace-tcg.h" 33 #include "exec/log.h" 34 35 36 //#define DEBUG_DISPATCH 1 37 38 /* Fake floating point. */ 39 #define tcg_gen_mov_f64 tcg_gen_mov_i64 40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 42 43 #define DEFO32(name, offset) static TCGv QREG_##name; 44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name; 45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name; 46 #include "qregs.def" 47 #undef DEFO32 48 #undef DEFO64 49 #undef DEFF64 50 51 static TCGv_i32 cpu_halted; 52 static TCGv_i32 cpu_exception_index; 53 54 static TCGv_env cpu_env; 55 56 static char cpu_reg_names[3*8*3 + 5*4]; 57 static TCGv cpu_dregs[8]; 58 static TCGv cpu_aregs[8]; 59 static TCGv_i64 cpu_fregs[8]; 60 static TCGv_i64 cpu_macc[4]; 61 62 #define REG(insn, pos) (((insn) >> (pos)) & 7) 63 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)] 64 #define AREG(insn, pos) get_areg(s, REG(insn, pos)) 65 #define FREG(insn, pos) cpu_fregs[REG(insn, pos)] 66 #define MACREG(acc) cpu_macc[acc] 67 #define QREG_SP get_areg(s, 7) 68 69 static TCGv NULL_QREG; 70 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) 71 /* Used to distinguish stores from bad addressing modes. */ 72 static TCGv store_dummy; 73 74 #include "exec/gen-icount.h" 75 76 void m68k_tcg_init(void) 77 { 78 char *p; 79 int i; 80 81 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 82 tcg_ctx.tcg_env = cpu_env; 83 84 #define DEFO32(name, offset) \ 85 QREG_##name = tcg_global_mem_new_i32(cpu_env, \ 86 offsetof(CPUM68KState, offset), #name); 87 #define DEFO64(name, offset) \ 88 QREG_##name = tcg_global_mem_new_i64(cpu_env, \ 89 offsetof(CPUM68KState, offset), #name); 90 #define DEFF64(name, offset) DEFO64(name, offset) 91 #include "qregs.def" 92 #undef DEFO32 93 #undef DEFO64 94 #undef DEFF64 95 96 cpu_halted = tcg_global_mem_new_i32(cpu_env, 97 -offsetof(M68kCPU, env) + 98 offsetof(CPUState, halted), "HALTED"); 99 cpu_exception_index = tcg_global_mem_new_i32(cpu_env, 100 -offsetof(M68kCPU, env) + 101 offsetof(CPUState, exception_index), 102 "EXCEPTION"); 103 104 p = cpu_reg_names; 105 for (i = 0; i < 8; i++) { 106 sprintf(p, "D%d", i); 107 cpu_dregs[i] = tcg_global_mem_new(cpu_env, 108 offsetof(CPUM68KState, dregs[i]), p); 109 p += 3; 110 sprintf(p, "A%d", i); 111 cpu_aregs[i] = tcg_global_mem_new(cpu_env, 112 offsetof(CPUM68KState, aregs[i]), p); 113 p += 3; 114 sprintf(p, "F%d", i); 115 cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env, 116 offsetof(CPUM68KState, fregs[i]), p); 117 p += 3; 118 } 119 for (i = 0; i < 4; i++) { 120 sprintf(p, "ACC%d", i); 121 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, 122 offsetof(CPUM68KState, macc[i]), p); 123 p += 5; 124 } 125 126 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); 127 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); 128 } 129 130 /* internal defines */ 131 typedef struct DisasContext { 132 CPUM68KState *env; 133 target_ulong insn_pc; /* Start of the current instruction. */ 134 target_ulong pc; 135 int is_jmp; 136 CCOp cc_op; /* Current CC operation */ 137 int cc_op_synced; 138 int user; 139 uint32_t fpcr; 140 struct TranslationBlock *tb; 141 int singlestep_enabled; 142 TCGv_i64 mactmp; 143 int done_mac; 144 int writeback_mask; 145 TCGv writeback[8]; 146 } DisasContext; 147 148 static TCGv get_areg(DisasContext *s, unsigned regno) 149 { 150 if (s->writeback_mask & (1 << regno)) { 151 return s->writeback[regno]; 152 } else { 153 return cpu_aregs[regno]; 154 } 155 } 156 157 static void delay_set_areg(DisasContext *s, unsigned regno, 158 TCGv val, bool give_temp) 159 { 160 if (s->writeback_mask & (1 << regno)) { 161 if (give_temp) { 162 tcg_temp_free(s->writeback[regno]); 163 s->writeback[regno] = val; 164 } else { 165 tcg_gen_mov_i32(s->writeback[regno], val); 166 } 167 } else { 168 s->writeback_mask |= 1 << regno; 169 if (give_temp) { 170 s->writeback[regno] = val; 171 } else { 172 TCGv tmp = tcg_temp_new(); 173 s->writeback[regno] = tmp; 174 tcg_gen_mov_i32(tmp, val); 175 } 176 } 177 } 178 179 static void do_writebacks(DisasContext *s) 180 { 181 unsigned mask = s->writeback_mask; 182 if (mask) { 183 s->writeback_mask = 0; 184 do { 185 unsigned regno = ctz32(mask); 186 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]); 187 tcg_temp_free(s->writeback[regno]); 188 mask &= mask - 1; 189 } while (mask); 190 } 191 } 192 193 #define DISAS_JUMP_NEXT 4 194 195 #if defined(CONFIG_USER_ONLY) 196 #define IS_USER(s) 1 197 #else 198 #define IS_USER(s) s->user 199 #endif 200 201 /* XXX: move that elsewhere */ 202 /* ??? Fix exceptions. */ 203 static void *gen_throws_exception; 204 #define gen_last_qop NULL 205 206 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); 207 208 #ifdef DEBUG_DISPATCH 209 #define DISAS_INSN(name) \ 210 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ 211 uint16_t insn); \ 212 static void disas_##name(CPUM68KState *env, DisasContext *s, \ 213 uint16_t insn) \ 214 { \ 215 qemu_log("Dispatch " #name "\n"); \ 216 real_disas_##name(env, s, insn); \ 217 } \ 218 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ 219 uint16_t insn) 220 #else 221 #define DISAS_INSN(name) \ 222 static void disas_##name(CPUM68KState *env, DisasContext *s, \ 223 uint16_t insn) 224 #endif 225 226 static const uint8_t cc_op_live[CC_OP_NB] = { 227 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X, 228 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V, 229 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V, 230 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V, 231 [CC_OP_LOGIC] = CCF_X | CCF_N 232 }; 233 234 static void set_cc_op(DisasContext *s, CCOp op) 235 { 236 CCOp old_op = s->cc_op; 237 int dead; 238 239 if (old_op == op) { 240 return; 241 } 242 s->cc_op = op; 243 s->cc_op_synced = 0; 244 245 /* Discard CC computation that will no longer be used. 246 Note that X and N are never dead. */ 247 dead = cc_op_live[old_op] & ~cc_op_live[op]; 248 if (dead & CCF_C) { 249 tcg_gen_discard_i32(QREG_CC_C); 250 } 251 if (dead & CCF_Z) { 252 tcg_gen_discard_i32(QREG_CC_Z); 253 } 254 if (dead & CCF_V) { 255 tcg_gen_discard_i32(QREG_CC_V); 256 } 257 } 258 259 /* Update the CPU env CC_OP state. */ 260 static void update_cc_op(DisasContext *s) 261 { 262 if (!s->cc_op_synced) { 263 s->cc_op_synced = 1; 264 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); 265 } 266 } 267 268 /* Generate a load from the specified address. Narrow values are 269 sign extended to full register width. */ 270 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) 271 { 272 TCGv tmp; 273 int index = IS_USER(s); 274 tmp = tcg_temp_new_i32(); 275 switch(opsize) { 276 case OS_BYTE: 277 if (sign) 278 tcg_gen_qemu_ld8s(tmp, addr, index); 279 else 280 tcg_gen_qemu_ld8u(tmp, addr, index); 281 break; 282 case OS_WORD: 283 if (sign) 284 tcg_gen_qemu_ld16s(tmp, addr, index); 285 else 286 tcg_gen_qemu_ld16u(tmp, addr, index); 287 break; 288 case OS_LONG: 289 case OS_SINGLE: 290 tcg_gen_qemu_ld32u(tmp, addr, index); 291 break; 292 default: 293 g_assert_not_reached(); 294 } 295 gen_throws_exception = gen_last_qop; 296 return tmp; 297 } 298 299 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) 300 { 301 TCGv_i64 tmp; 302 int index = IS_USER(s); 303 tmp = tcg_temp_new_i64(); 304 tcg_gen_qemu_ldf64(tmp, addr, index); 305 gen_throws_exception = gen_last_qop; 306 return tmp; 307 } 308 309 /* Generate a store. */ 310 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) 311 { 312 int index = IS_USER(s); 313 switch(opsize) { 314 case OS_BYTE: 315 tcg_gen_qemu_st8(val, addr, index); 316 break; 317 case OS_WORD: 318 tcg_gen_qemu_st16(val, addr, index); 319 break; 320 case OS_LONG: 321 case OS_SINGLE: 322 tcg_gen_qemu_st32(val, addr, index); 323 break; 324 default: 325 g_assert_not_reached(); 326 } 327 gen_throws_exception = gen_last_qop; 328 } 329 330 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) 331 { 332 int index = IS_USER(s); 333 tcg_gen_qemu_stf64(val, addr, index); 334 gen_throws_exception = gen_last_qop; 335 } 336 337 typedef enum { 338 EA_STORE, 339 EA_LOADU, 340 EA_LOADS 341 } ea_what; 342 343 /* Generate an unsigned load if VAL is 0 a signed load if val is -1, 344 otherwise generate a store. */ 345 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, 346 ea_what what) 347 { 348 if (what == EA_STORE) { 349 gen_store(s, opsize, addr, val); 350 return store_dummy; 351 } else { 352 return gen_load(s, opsize, addr, what == EA_LOADS); 353 } 354 } 355 356 /* Read a 16-bit immediate constant */ 357 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) 358 { 359 uint16_t im; 360 im = cpu_lduw_code(env, s->pc); 361 s->pc += 2; 362 return im; 363 } 364 365 /* Read an 8-bit immediate constant */ 366 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s) 367 { 368 return read_im16(env, s); 369 } 370 371 /* Read a 32-bit immediate constant. */ 372 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) 373 { 374 uint32_t im; 375 im = read_im16(env, s) << 16; 376 im |= 0xffff & read_im16(env, s); 377 return im; 378 } 379 380 /* Calculate and address index. */ 381 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp) 382 { 383 TCGv add; 384 int scale; 385 386 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); 387 if ((ext & 0x800) == 0) { 388 tcg_gen_ext16s_i32(tmp, add); 389 add = tmp; 390 } 391 scale = (ext >> 9) & 3; 392 if (scale != 0) { 393 tcg_gen_shli_i32(tmp, add, scale); 394 add = tmp; 395 } 396 return add; 397 } 398 399 /* Handle a base + index + displacement effective addresss. 400 A NULL_QREG base means pc-relative. */ 401 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) 402 { 403 uint32_t offset; 404 uint16_t ext; 405 TCGv add; 406 TCGv tmp; 407 uint32_t bd, od; 408 409 offset = s->pc; 410 ext = read_im16(env, s); 411 412 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) 413 return NULL_QREG; 414 415 if (m68k_feature(s->env, M68K_FEATURE_M68000) && 416 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) { 417 ext &= ~(3 << 9); 418 } 419 420 if (ext & 0x100) { 421 /* full extension word format */ 422 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) 423 return NULL_QREG; 424 425 if ((ext & 0x30) > 0x10) { 426 /* base displacement */ 427 if ((ext & 0x30) == 0x20) { 428 bd = (int16_t)read_im16(env, s); 429 } else { 430 bd = read_im32(env, s); 431 } 432 } else { 433 bd = 0; 434 } 435 tmp = tcg_temp_new(); 436 if ((ext & 0x44) == 0) { 437 /* pre-index */ 438 add = gen_addr_index(s, ext, tmp); 439 } else { 440 add = NULL_QREG; 441 } 442 if ((ext & 0x80) == 0) { 443 /* base not suppressed */ 444 if (IS_NULL_QREG(base)) { 445 base = tcg_const_i32(offset + bd); 446 bd = 0; 447 } 448 if (!IS_NULL_QREG(add)) { 449 tcg_gen_add_i32(tmp, add, base); 450 add = tmp; 451 } else { 452 add = base; 453 } 454 } 455 if (!IS_NULL_QREG(add)) { 456 if (bd != 0) { 457 tcg_gen_addi_i32(tmp, add, bd); 458 add = tmp; 459 } 460 } else { 461 add = tcg_const_i32(bd); 462 } 463 if ((ext & 3) != 0) { 464 /* memory indirect */ 465 base = gen_load(s, OS_LONG, add, 0); 466 if ((ext & 0x44) == 4) { 467 add = gen_addr_index(s, ext, tmp); 468 tcg_gen_add_i32(tmp, add, base); 469 add = tmp; 470 } else { 471 add = base; 472 } 473 if ((ext & 3) > 1) { 474 /* outer displacement */ 475 if ((ext & 3) == 2) { 476 od = (int16_t)read_im16(env, s); 477 } else { 478 od = read_im32(env, s); 479 } 480 } else { 481 od = 0; 482 } 483 if (od != 0) { 484 tcg_gen_addi_i32(tmp, add, od); 485 add = tmp; 486 } 487 } 488 } else { 489 /* brief extension word format */ 490 tmp = tcg_temp_new(); 491 add = gen_addr_index(s, ext, tmp); 492 if (!IS_NULL_QREG(base)) { 493 tcg_gen_add_i32(tmp, add, base); 494 if ((int8_t)ext) 495 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); 496 } else { 497 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); 498 } 499 add = tmp; 500 } 501 return add; 502 } 503 504 /* Sign or zero extend a value. */ 505 506 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign) 507 { 508 switch (opsize) { 509 case OS_BYTE: 510 if (sign) { 511 tcg_gen_ext8s_i32(res, val); 512 } else { 513 tcg_gen_ext8u_i32(res, val); 514 } 515 break; 516 case OS_WORD: 517 if (sign) { 518 tcg_gen_ext16s_i32(res, val); 519 } else { 520 tcg_gen_ext16u_i32(res, val); 521 } 522 break; 523 case OS_LONG: 524 tcg_gen_mov_i32(res, val); 525 break; 526 default: 527 g_assert_not_reached(); 528 } 529 } 530 531 /* Evaluate all the CC flags. */ 532 533 static void gen_flush_flags(DisasContext *s) 534 { 535 TCGv t0, t1; 536 537 switch (s->cc_op) { 538 case CC_OP_FLAGS: 539 return; 540 541 case CC_OP_ADDB: 542 case CC_OP_ADDW: 543 case CC_OP_ADDL: 544 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); 545 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); 546 /* Compute signed overflow for addition. */ 547 t0 = tcg_temp_new(); 548 t1 = tcg_temp_new(); 549 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V); 550 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1); 551 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); 552 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); 553 tcg_temp_free(t0); 554 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V); 555 tcg_temp_free(t1); 556 break; 557 558 case CC_OP_SUBB: 559 case CC_OP_SUBW: 560 case CC_OP_SUBL: 561 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); 562 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); 563 /* Compute signed overflow for subtraction. */ 564 t0 = tcg_temp_new(); 565 t1 = tcg_temp_new(); 566 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V); 567 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1); 568 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); 569 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); 570 tcg_temp_free(t0); 571 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1); 572 tcg_temp_free(t1); 573 break; 574 575 case CC_OP_CMPB: 576 case CC_OP_CMPW: 577 case CC_OP_CMPL: 578 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V); 579 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V); 580 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1); 581 /* Compute signed overflow for subtraction. */ 582 t0 = tcg_temp_new(); 583 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N); 584 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N); 585 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0); 586 tcg_temp_free(t0); 587 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z); 588 break; 589 590 case CC_OP_LOGIC: 591 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); 592 tcg_gen_movi_i32(QREG_CC_C, 0); 593 tcg_gen_movi_i32(QREG_CC_V, 0); 594 break; 595 596 case CC_OP_DYNAMIC: 597 gen_helper_flush_flags(cpu_env, QREG_CC_OP); 598 s->cc_op_synced = 1; 599 break; 600 601 default: 602 t0 = tcg_const_i32(s->cc_op); 603 gen_helper_flush_flags(cpu_env, t0); 604 tcg_temp_free(t0); 605 s->cc_op_synced = 1; 606 break; 607 } 608 609 /* Note that flush_flags also assigned to env->cc_op. */ 610 s->cc_op = CC_OP_FLAGS; 611 } 612 613 static inline TCGv gen_extend(TCGv val, int opsize, int sign) 614 { 615 TCGv tmp; 616 617 if (opsize == OS_LONG) { 618 tmp = val; 619 } else { 620 tmp = tcg_temp_new(); 621 gen_ext(tmp, val, opsize, sign); 622 } 623 624 return tmp; 625 } 626 627 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) 628 { 629 gen_ext(QREG_CC_N, val, opsize, 1); 630 set_cc_op(s, CC_OP_LOGIC); 631 } 632 633 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize) 634 { 635 tcg_gen_mov_i32(QREG_CC_N, dest); 636 tcg_gen_mov_i32(QREG_CC_V, src); 637 set_cc_op(s, CC_OP_CMPB + opsize); 638 } 639 640 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize) 641 { 642 gen_ext(QREG_CC_N, dest, opsize, 1); 643 tcg_gen_mov_i32(QREG_CC_V, src); 644 } 645 646 static inline int opsize_bytes(int opsize) 647 { 648 switch (opsize) { 649 case OS_BYTE: return 1; 650 case OS_WORD: return 2; 651 case OS_LONG: return 4; 652 case OS_SINGLE: return 4; 653 case OS_DOUBLE: return 8; 654 case OS_EXTENDED: return 12; 655 case OS_PACKED: return 12; 656 default: 657 g_assert_not_reached(); 658 } 659 } 660 661 static inline int insn_opsize(int insn) 662 { 663 switch ((insn >> 6) & 3) { 664 case 0: return OS_BYTE; 665 case 1: return OS_WORD; 666 case 2: return OS_LONG; 667 default: 668 g_assert_not_reached(); 669 } 670 } 671 672 /* Assign value to a register. If the width is less than the register width 673 only the low part of the register is set. */ 674 static void gen_partset_reg(int opsize, TCGv reg, TCGv val) 675 { 676 TCGv tmp; 677 switch (opsize) { 678 case OS_BYTE: 679 tcg_gen_andi_i32(reg, reg, 0xffffff00); 680 tmp = tcg_temp_new(); 681 tcg_gen_ext8u_i32(tmp, val); 682 tcg_gen_or_i32(reg, reg, tmp); 683 tcg_temp_free(tmp); 684 break; 685 case OS_WORD: 686 tcg_gen_andi_i32(reg, reg, 0xffff0000); 687 tmp = tcg_temp_new(); 688 tcg_gen_ext16u_i32(tmp, val); 689 tcg_gen_or_i32(reg, reg, tmp); 690 tcg_temp_free(tmp); 691 break; 692 case OS_LONG: 693 case OS_SINGLE: 694 tcg_gen_mov_i32(reg, val); 695 break; 696 default: 697 g_assert_not_reached(); 698 } 699 } 700 701 /* Generate code for an "effective address". Does not adjust the base 702 register for autoincrement addressing modes. */ 703 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s, 704 int mode, int reg0, int opsize) 705 { 706 TCGv reg; 707 TCGv tmp; 708 uint16_t ext; 709 uint32_t offset; 710 711 switch (mode) { 712 case 0: /* Data register direct. */ 713 case 1: /* Address register direct. */ 714 return NULL_QREG; 715 case 3: /* Indirect postincrement. */ 716 if (opsize == OS_UNSIZED) { 717 return NULL_QREG; 718 } 719 /* fallthru */ 720 case 2: /* Indirect register */ 721 return get_areg(s, reg0); 722 case 4: /* Indirect predecrememnt. */ 723 if (opsize == OS_UNSIZED) { 724 return NULL_QREG; 725 } 726 reg = get_areg(s, reg0); 727 tmp = tcg_temp_new(); 728 if (reg0 == 7 && opsize == OS_BYTE && 729 m68k_feature(s->env, M68K_FEATURE_M68000)) { 730 tcg_gen_subi_i32(tmp, reg, 2); 731 } else { 732 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); 733 } 734 return tmp; 735 case 5: /* Indirect displacement. */ 736 reg = get_areg(s, reg0); 737 tmp = tcg_temp_new(); 738 ext = read_im16(env, s); 739 tcg_gen_addi_i32(tmp, reg, (int16_t)ext); 740 return tmp; 741 case 6: /* Indirect index + displacement. */ 742 reg = get_areg(s, reg0); 743 return gen_lea_indexed(env, s, reg); 744 case 7: /* Other */ 745 switch (reg0) { 746 case 0: /* Absolute short. */ 747 offset = (int16_t)read_im16(env, s); 748 return tcg_const_i32(offset); 749 case 1: /* Absolute long. */ 750 offset = read_im32(env, s); 751 return tcg_const_i32(offset); 752 case 2: /* pc displacement */ 753 offset = s->pc; 754 offset += (int16_t)read_im16(env, s); 755 return tcg_const_i32(offset); 756 case 3: /* pc index+displacement. */ 757 return gen_lea_indexed(env, s, NULL_QREG); 758 case 4: /* Immediate. */ 759 default: 760 return NULL_QREG; 761 } 762 } 763 /* Should never happen. */ 764 return NULL_QREG; 765 } 766 767 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, 768 int opsize) 769 { 770 int mode = extract32(insn, 3, 3); 771 int reg0 = REG(insn, 0); 772 return gen_lea_mode(env, s, mode, reg0, opsize); 773 } 774 775 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is 776 a write otherwise it is a read (0 == sign extend, -1 == zero extend). 777 ADDRP is non-null for readwrite operands. */ 778 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, 779 int opsize, TCGv val, TCGv *addrp, ea_what what) 780 { 781 TCGv reg, tmp, result; 782 int32_t offset; 783 784 switch (mode) { 785 case 0: /* Data register direct. */ 786 reg = cpu_dregs[reg0]; 787 if (what == EA_STORE) { 788 gen_partset_reg(opsize, reg, val); 789 return store_dummy; 790 } else { 791 return gen_extend(reg, opsize, what == EA_LOADS); 792 } 793 case 1: /* Address register direct. */ 794 reg = get_areg(s, reg0); 795 if (what == EA_STORE) { 796 tcg_gen_mov_i32(reg, val); 797 return store_dummy; 798 } else { 799 return gen_extend(reg, opsize, what == EA_LOADS); 800 } 801 case 2: /* Indirect register */ 802 reg = get_areg(s, reg0); 803 return gen_ldst(s, opsize, reg, val, what); 804 case 3: /* Indirect postincrement. */ 805 reg = get_areg(s, reg0); 806 result = gen_ldst(s, opsize, reg, val, what); 807 if (what == EA_STORE || !addrp) { 808 TCGv tmp = tcg_temp_new(); 809 if (reg0 == 7 && opsize == OS_BYTE && 810 m68k_feature(s->env, M68K_FEATURE_M68000)) { 811 tcg_gen_addi_i32(tmp, reg, 2); 812 } else { 813 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize)); 814 } 815 delay_set_areg(s, reg0, tmp, true); 816 } 817 return result; 818 case 4: /* Indirect predecrememnt. */ 819 if (addrp && what == EA_STORE) { 820 tmp = *addrp; 821 } else { 822 tmp = gen_lea_mode(env, s, mode, reg0, opsize); 823 if (IS_NULL_QREG(tmp)) { 824 return tmp; 825 } 826 if (addrp) { 827 *addrp = tmp; 828 } 829 } 830 result = gen_ldst(s, opsize, tmp, val, what); 831 if (what == EA_STORE || !addrp) { 832 delay_set_areg(s, reg0, tmp, false); 833 } 834 return result; 835 case 5: /* Indirect displacement. */ 836 case 6: /* Indirect index + displacement. */ 837 do_indirect: 838 if (addrp && what == EA_STORE) { 839 tmp = *addrp; 840 } else { 841 tmp = gen_lea_mode(env, s, mode, reg0, opsize); 842 if (IS_NULL_QREG(tmp)) { 843 return tmp; 844 } 845 if (addrp) { 846 *addrp = tmp; 847 } 848 } 849 return gen_ldst(s, opsize, tmp, val, what); 850 case 7: /* Other */ 851 switch (reg0) { 852 case 0: /* Absolute short. */ 853 case 1: /* Absolute long. */ 854 case 2: /* pc displacement */ 855 case 3: /* pc index+displacement. */ 856 goto do_indirect; 857 case 4: /* Immediate. */ 858 /* Sign extend values for consistency. */ 859 switch (opsize) { 860 case OS_BYTE: 861 if (what == EA_LOADS) { 862 offset = (int8_t)read_im8(env, s); 863 } else { 864 offset = read_im8(env, s); 865 } 866 break; 867 case OS_WORD: 868 if (what == EA_LOADS) { 869 offset = (int16_t)read_im16(env, s); 870 } else { 871 offset = read_im16(env, s); 872 } 873 break; 874 case OS_LONG: 875 offset = read_im32(env, s); 876 break; 877 default: 878 g_assert_not_reached(); 879 } 880 return tcg_const_i32(offset); 881 default: 882 return NULL_QREG; 883 } 884 } 885 /* Should never happen. */ 886 return NULL_QREG; 887 } 888 889 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, 890 int opsize, TCGv val, TCGv *addrp, ea_what what) 891 { 892 int mode = extract32(insn, 3, 3); 893 int reg0 = REG(insn, 0); 894 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what); 895 } 896 897 typedef struct { 898 TCGCond tcond; 899 bool g1; 900 bool g2; 901 TCGv v1; 902 TCGv v2; 903 } DisasCompare; 904 905 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) 906 { 907 TCGv tmp, tmp2; 908 TCGCond tcond; 909 CCOp op = s->cc_op; 910 911 /* The CC_OP_CMP form can handle most normal comparisons directly. */ 912 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) { 913 c->g1 = c->g2 = 1; 914 c->v1 = QREG_CC_N; 915 c->v2 = QREG_CC_V; 916 switch (cond) { 917 case 2: /* HI */ 918 case 3: /* LS */ 919 tcond = TCG_COND_LEU; 920 goto done; 921 case 4: /* CC */ 922 case 5: /* CS */ 923 tcond = TCG_COND_LTU; 924 goto done; 925 case 6: /* NE */ 926 case 7: /* EQ */ 927 tcond = TCG_COND_EQ; 928 goto done; 929 case 10: /* PL */ 930 case 11: /* MI */ 931 c->g1 = c->g2 = 0; 932 c->v2 = tcg_const_i32(0); 933 c->v1 = tmp = tcg_temp_new(); 934 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); 935 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1); 936 /* fallthru */ 937 case 12: /* GE */ 938 case 13: /* LT */ 939 tcond = TCG_COND_LT; 940 goto done; 941 case 14: /* GT */ 942 case 15: /* LE */ 943 tcond = TCG_COND_LE; 944 goto done; 945 } 946 } 947 948 c->g1 = 1; 949 c->g2 = 0; 950 c->v2 = tcg_const_i32(0); 951 952 switch (cond) { 953 case 0: /* T */ 954 case 1: /* F */ 955 c->v1 = c->v2; 956 tcond = TCG_COND_NEVER; 957 goto done; 958 case 14: /* GT (!(Z || (N ^ V))) */ 959 case 15: /* LE (Z || (N ^ V)) */ 960 /* Logic operations clear V, which simplifies LE to (Z || N), 961 and since Z and N are co-located, this becomes a normal 962 comparison vs N. */ 963 if (op == CC_OP_LOGIC) { 964 c->v1 = QREG_CC_N; 965 tcond = TCG_COND_LE; 966 goto done; 967 } 968 break; 969 case 12: /* GE (!(N ^ V)) */ 970 case 13: /* LT (N ^ V) */ 971 /* Logic operations clear V, which simplifies this to N. */ 972 if (op != CC_OP_LOGIC) { 973 break; 974 } 975 /* fallthru */ 976 case 10: /* PL (!N) */ 977 case 11: /* MI (N) */ 978 /* Several cases represent N normally. */ 979 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || 980 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL || 981 op == CC_OP_LOGIC) { 982 c->v1 = QREG_CC_N; 983 tcond = TCG_COND_LT; 984 goto done; 985 } 986 break; 987 case 6: /* NE (!Z) */ 988 case 7: /* EQ (Z) */ 989 /* Some cases fold Z into N. */ 990 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || 991 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL || 992 op == CC_OP_LOGIC) { 993 tcond = TCG_COND_EQ; 994 c->v1 = QREG_CC_N; 995 goto done; 996 } 997 break; 998 case 4: /* CC (!C) */ 999 case 5: /* CS (C) */ 1000 /* Some cases fold C into X. */ 1001 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || 1002 op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL) { 1003 tcond = TCG_COND_NE; 1004 c->v1 = QREG_CC_X; 1005 goto done; 1006 } 1007 /* fallthru */ 1008 case 8: /* VC (!V) */ 1009 case 9: /* VS (V) */ 1010 /* Logic operations clear V and C. */ 1011 if (op == CC_OP_LOGIC) { 1012 tcond = TCG_COND_NEVER; 1013 c->v1 = c->v2; 1014 goto done; 1015 } 1016 break; 1017 } 1018 1019 /* Otherwise, flush flag state to CC_OP_FLAGS. */ 1020 gen_flush_flags(s); 1021 1022 switch (cond) { 1023 case 0: /* T */ 1024 case 1: /* F */ 1025 default: 1026 /* Invalid, or handled above. */ 1027 abort(); 1028 case 2: /* HI (!C && !Z) -> !(C || Z)*/ 1029 case 3: /* LS (C || Z) */ 1030 c->v1 = tmp = tcg_temp_new(); 1031 c->g1 = 0; 1032 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); 1033 tcg_gen_or_i32(tmp, tmp, QREG_CC_C); 1034 tcond = TCG_COND_NE; 1035 break; 1036 case 4: /* CC (!C) */ 1037 case 5: /* CS (C) */ 1038 c->v1 = QREG_CC_C; 1039 tcond = TCG_COND_NE; 1040 break; 1041 case 6: /* NE (!Z) */ 1042 case 7: /* EQ (Z) */ 1043 c->v1 = QREG_CC_Z; 1044 tcond = TCG_COND_EQ; 1045 break; 1046 case 8: /* VC (!V) */ 1047 case 9: /* VS (V) */ 1048 c->v1 = QREG_CC_V; 1049 tcond = TCG_COND_LT; 1050 break; 1051 case 10: /* PL (!N) */ 1052 case 11: /* MI (N) */ 1053 c->v1 = QREG_CC_N; 1054 tcond = TCG_COND_LT; 1055 break; 1056 case 12: /* GE (!(N ^ V)) */ 1057 case 13: /* LT (N ^ V) */ 1058 c->v1 = tmp = tcg_temp_new(); 1059 c->g1 = 0; 1060 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); 1061 tcond = TCG_COND_LT; 1062 break; 1063 case 14: /* GT (!(Z || (N ^ V))) */ 1064 case 15: /* LE (Z || (N ^ V)) */ 1065 c->v1 = tmp = tcg_temp_new(); 1066 c->g1 = 0; 1067 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); 1068 tcg_gen_neg_i32(tmp, tmp); 1069 tmp2 = tcg_temp_new(); 1070 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); 1071 tcg_gen_or_i32(tmp, tmp, tmp2); 1072 tcg_temp_free(tmp2); 1073 tcond = TCG_COND_LT; 1074 break; 1075 } 1076 1077 done: 1078 if ((cond & 1) == 0) { 1079 tcond = tcg_invert_cond(tcond); 1080 } 1081 c->tcond = tcond; 1082 } 1083 1084 static void free_cond(DisasCompare *c) 1085 { 1086 if (!c->g1) { 1087 tcg_temp_free(c->v1); 1088 } 1089 if (!c->g2) { 1090 tcg_temp_free(c->v2); 1091 } 1092 } 1093 1094 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) 1095 { 1096 DisasCompare c; 1097 1098 gen_cc_cond(&c, s, cond); 1099 update_cc_op(s); 1100 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); 1101 free_cond(&c); 1102 } 1103 1104 /* Force a TB lookup after an instruction that changes the CPU state. */ 1105 static void gen_lookup_tb(DisasContext *s) 1106 { 1107 update_cc_op(s); 1108 tcg_gen_movi_i32(QREG_PC, s->pc); 1109 s->is_jmp = DISAS_UPDATE; 1110 } 1111 1112 /* Generate a jump to an immediate address. */ 1113 static void gen_jmp_im(DisasContext *s, uint32_t dest) 1114 { 1115 update_cc_op(s); 1116 tcg_gen_movi_i32(QREG_PC, dest); 1117 s->is_jmp = DISAS_JUMP; 1118 } 1119 1120 /* Generate a jump to the address in qreg DEST. */ 1121 static void gen_jmp(DisasContext *s, TCGv dest) 1122 { 1123 update_cc_op(s); 1124 tcg_gen_mov_i32(QREG_PC, dest); 1125 s->is_jmp = DISAS_JUMP; 1126 } 1127 1128 static void gen_raise_exception(int nr) 1129 { 1130 TCGv_i32 tmp = tcg_const_i32(nr); 1131 1132 gen_helper_raise_exception(cpu_env, tmp); 1133 tcg_temp_free_i32(tmp); 1134 } 1135 1136 static void gen_exception(DisasContext *s, uint32_t where, int nr) 1137 { 1138 update_cc_op(s); 1139 gen_jmp_im(s, where); 1140 gen_raise_exception(nr); 1141 } 1142 1143 static inline void gen_addr_fault(DisasContext *s) 1144 { 1145 gen_exception(s, s->insn_pc, EXCP_ADDRESS); 1146 } 1147 1148 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ 1149 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ 1150 op_sign ? EA_LOADS : EA_LOADU); \ 1151 if (IS_NULL_QREG(result)) { \ 1152 gen_addr_fault(s); \ 1153 return; \ 1154 } \ 1155 } while (0) 1156 1157 #define DEST_EA(env, insn, opsize, val, addrp) do { \ 1158 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ 1159 if (IS_NULL_QREG(ea_result)) { \ 1160 gen_addr_fault(s); \ 1161 return; \ 1162 } \ 1163 } while (0) 1164 1165 static inline bool use_goto_tb(DisasContext *s, uint32_t dest) 1166 { 1167 #ifndef CONFIG_USER_ONLY 1168 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || 1169 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 1170 #else 1171 return true; 1172 #endif 1173 } 1174 1175 /* Generate a jump to an immediate address. */ 1176 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) 1177 { 1178 if (unlikely(s->singlestep_enabled)) { 1179 gen_exception(s, dest, EXCP_DEBUG); 1180 } else if (use_goto_tb(s, dest)) { 1181 tcg_gen_goto_tb(n); 1182 tcg_gen_movi_i32(QREG_PC, dest); 1183 tcg_gen_exit_tb((uintptr_t)s->tb + n); 1184 } else { 1185 gen_jmp_im(s, dest); 1186 tcg_gen_exit_tb(0); 1187 } 1188 s->is_jmp = DISAS_TB_JUMP; 1189 } 1190 1191 DISAS_INSN(scc) 1192 { 1193 DisasCompare c; 1194 int cond; 1195 TCGv tmp; 1196 1197 cond = (insn >> 8) & 0xf; 1198 gen_cc_cond(&c, s, cond); 1199 1200 tmp = tcg_temp_new(); 1201 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); 1202 free_cond(&c); 1203 1204 tcg_gen_neg_i32(tmp, tmp); 1205 DEST_EA(env, insn, OS_BYTE, tmp, NULL); 1206 tcg_temp_free(tmp); 1207 } 1208 1209 DISAS_INSN(dbcc) 1210 { 1211 TCGLabel *l1; 1212 TCGv reg; 1213 TCGv tmp; 1214 int16_t offset; 1215 uint32_t base; 1216 1217 reg = DREG(insn, 0); 1218 base = s->pc; 1219 offset = (int16_t)read_im16(env, s); 1220 l1 = gen_new_label(); 1221 gen_jmpcc(s, (insn >> 8) & 0xf, l1); 1222 1223 tmp = tcg_temp_new(); 1224 tcg_gen_ext16s_i32(tmp, reg); 1225 tcg_gen_addi_i32(tmp, tmp, -1); 1226 gen_partset_reg(OS_WORD, reg, tmp); 1227 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1); 1228 gen_jmp_tb(s, 1, base + offset); 1229 gen_set_label(l1); 1230 gen_jmp_tb(s, 0, s->pc); 1231 } 1232 1233 DISAS_INSN(undef_mac) 1234 { 1235 gen_exception(s, s->pc - 2, EXCP_LINEA); 1236 } 1237 1238 DISAS_INSN(undef_fpu) 1239 { 1240 gen_exception(s, s->pc - 2, EXCP_LINEF); 1241 } 1242 1243 DISAS_INSN(undef) 1244 { 1245 /* ??? This is both instructions that are as yet unimplemented 1246 for the 680x0 series, as well as those that are implemented 1247 but actually illegal for CPU32 or pre-68020. */ 1248 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x", 1249 insn, s->pc - 2); 1250 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); 1251 } 1252 1253 DISAS_INSN(mulw) 1254 { 1255 TCGv reg; 1256 TCGv tmp; 1257 TCGv src; 1258 int sign; 1259 1260 sign = (insn & 0x100) != 0; 1261 reg = DREG(insn, 9); 1262 tmp = tcg_temp_new(); 1263 if (sign) 1264 tcg_gen_ext16s_i32(tmp, reg); 1265 else 1266 tcg_gen_ext16u_i32(tmp, reg); 1267 SRC_EA(env, src, OS_WORD, sign, NULL); 1268 tcg_gen_mul_i32(tmp, tmp, src); 1269 tcg_gen_mov_i32(reg, tmp); 1270 gen_logic_cc(s, tmp, OS_LONG); 1271 tcg_temp_free(tmp); 1272 } 1273 1274 DISAS_INSN(divw) 1275 { 1276 int sign; 1277 TCGv src; 1278 TCGv destr; 1279 1280 /* divX.w <EA>,Dn 32/16 -> 16r:16q */ 1281 1282 sign = (insn & 0x100) != 0; 1283 1284 /* dest.l / src.w */ 1285 1286 SRC_EA(env, src, OS_WORD, sign, NULL); 1287 destr = tcg_const_i32(REG(insn, 9)); 1288 if (sign) { 1289 gen_helper_divsw(cpu_env, destr, src); 1290 } else { 1291 gen_helper_divuw(cpu_env, destr, src); 1292 } 1293 tcg_temp_free(destr); 1294 1295 set_cc_op(s, CC_OP_FLAGS); 1296 } 1297 1298 DISAS_INSN(divl) 1299 { 1300 TCGv num, reg, den; 1301 int sign; 1302 uint16_t ext; 1303 1304 ext = read_im16(env, s); 1305 1306 sign = (ext & 0x0800) != 0; 1307 1308 if (ext & 0x400) { 1309 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) { 1310 gen_exception(s, s->insn_pc, EXCP_ILLEGAL); 1311 return; 1312 } 1313 1314 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */ 1315 1316 SRC_EA(env, den, OS_LONG, 0, NULL); 1317 num = tcg_const_i32(REG(ext, 12)); 1318 reg = tcg_const_i32(REG(ext, 0)); 1319 if (sign) { 1320 gen_helper_divsll(cpu_env, num, reg, den); 1321 } else { 1322 gen_helper_divull(cpu_env, num, reg, den); 1323 } 1324 tcg_temp_free(reg); 1325 tcg_temp_free(num); 1326 set_cc_op(s, CC_OP_FLAGS); 1327 return; 1328 } 1329 1330 /* divX.l <EA>, Dq 32/32 -> 32q */ 1331 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */ 1332 1333 SRC_EA(env, den, OS_LONG, 0, NULL); 1334 num = tcg_const_i32(REG(ext, 12)); 1335 reg = tcg_const_i32(REG(ext, 0)); 1336 if (sign) { 1337 gen_helper_divsl(cpu_env, num, reg, den); 1338 } else { 1339 gen_helper_divul(cpu_env, num, reg, den); 1340 } 1341 tcg_temp_free(reg); 1342 tcg_temp_free(num); 1343 1344 set_cc_op(s, CC_OP_FLAGS); 1345 } 1346 1347 static void bcd_add(TCGv dest, TCGv src) 1348 { 1349 TCGv t0, t1; 1350 1351 /* dest10 = dest10 + src10 + X 1352 * 1353 * t1 = src 1354 * t2 = t1 + 0x066 1355 * t3 = t2 + dest + X 1356 * t4 = t2 ^ dest 1357 * t5 = t3 ^ t4 1358 * t6 = ~t5 & 0x110 1359 * t7 = (t6 >> 2) | (t6 >> 3) 1360 * return t3 - t7 1361 */ 1362 1363 /* t1 = (src + 0x066) + dest + X 1364 * = result with some possible exceding 0x6 1365 */ 1366 1367 t0 = tcg_const_i32(0x066); 1368 tcg_gen_add_i32(t0, t0, src); 1369 1370 t1 = tcg_temp_new(); 1371 tcg_gen_add_i32(t1, t0, dest); 1372 tcg_gen_add_i32(t1, t1, QREG_CC_X); 1373 1374 /* we will remove exceding 0x6 where there is no carry */ 1375 1376 /* t0 = (src + 0x0066) ^ dest 1377 * = t1 without carries 1378 */ 1379 1380 tcg_gen_xor_i32(t0, t0, dest); 1381 1382 /* extract the carries 1383 * t0 = t0 ^ t1 1384 * = only the carries 1385 */ 1386 1387 tcg_gen_xor_i32(t0, t0, t1); 1388 1389 /* generate 0x1 where there is no carry 1390 * and for each 0x10, generate a 0x6 1391 */ 1392 1393 tcg_gen_shri_i32(t0, t0, 3); 1394 tcg_gen_not_i32(t0, t0); 1395 tcg_gen_andi_i32(t0, t0, 0x22); 1396 tcg_gen_add_i32(dest, t0, t0); 1397 tcg_gen_add_i32(dest, dest, t0); 1398 tcg_temp_free(t0); 1399 1400 /* remove the exceding 0x6 1401 * for digits that have not generated a carry 1402 */ 1403 1404 tcg_gen_sub_i32(dest, t1, dest); 1405 tcg_temp_free(t1); 1406 } 1407 1408 static void bcd_sub(TCGv dest, TCGv src) 1409 { 1410 TCGv t0, t1, t2; 1411 1412 /* dest10 = dest10 - src10 - X 1413 * = bcd_add(dest + 1 - X, 0x199 - src) 1414 */ 1415 1416 /* t0 = 0x066 + (0x199 - src) */ 1417 1418 t0 = tcg_temp_new(); 1419 tcg_gen_subfi_i32(t0, 0x1ff, src); 1420 1421 /* t1 = t0 + dest + 1 - X*/ 1422 1423 t1 = tcg_temp_new(); 1424 tcg_gen_add_i32(t1, t0, dest); 1425 tcg_gen_addi_i32(t1, t1, 1); 1426 tcg_gen_sub_i32(t1, t1, QREG_CC_X); 1427 1428 /* t2 = t0 ^ dest */ 1429 1430 t2 = tcg_temp_new(); 1431 tcg_gen_xor_i32(t2, t0, dest); 1432 1433 /* t0 = t1 ^ t2 */ 1434 1435 tcg_gen_xor_i32(t0, t1, t2); 1436 1437 /* t2 = ~t0 & 0x110 1438 * t0 = (t2 >> 2) | (t2 >> 3) 1439 * 1440 * to fit on 8bit operands, changed in: 1441 * 1442 * t2 = ~(t0 >> 3) & 0x22 1443 * t0 = t2 + t2 1444 * t0 = t0 + t2 1445 */ 1446 1447 tcg_gen_shri_i32(t2, t0, 3); 1448 tcg_gen_not_i32(t2, t2); 1449 tcg_gen_andi_i32(t2, t2, 0x22); 1450 tcg_gen_add_i32(t0, t2, t2); 1451 tcg_gen_add_i32(t0, t0, t2); 1452 tcg_temp_free(t2); 1453 1454 /* return t1 - t0 */ 1455 1456 tcg_gen_sub_i32(dest, t1, t0); 1457 tcg_temp_free(t0); 1458 tcg_temp_free(t1); 1459 } 1460 1461 static void bcd_flags(TCGv val) 1462 { 1463 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff); 1464 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C); 1465 1466 tcg_gen_shri_i32(QREG_CC_C, val, 8); 1467 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); 1468 1469 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); 1470 } 1471 1472 DISAS_INSN(abcd_reg) 1473 { 1474 TCGv src; 1475 TCGv dest; 1476 1477 gen_flush_flags(s); /* !Z is sticky */ 1478 1479 src = gen_extend(DREG(insn, 0), OS_BYTE, 0); 1480 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); 1481 bcd_add(dest, src); 1482 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); 1483 1484 bcd_flags(dest); 1485 } 1486 1487 DISAS_INSN(abcd_mem) 1488 { 1489 TCGv src, dest, addr; 1490 1491 gen_flush_flags(s); /* !Z is sticky */ 1492 1493 /* Indirect pre-decrement load (mode 4) */ 1494 1495 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, 1496 NULL_QREG, NULL, EA_LOADU); 1497 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, 1498 NULL_QREG, &addr, EA_LOADU); 1499 1500 bcd_add(dest, src); 1501 1502 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); 1503 1504 bcd_flags(dest); 1505 } 1506 1507 DISAS_INSN(sbcd_reg) 1508 { 1509 TCGv src, dest; 1510 1511 gen_flush_flags(s); /* !Z is sticky */ 1512 1513 src = gen_extend(DREG(insn, 0), OS_BYTE, 0); 1514 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); 1515 1516 bcd_sub(dest, src); 1517 1518 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); 1519 1520 bcd_flags(dest); 1521 } 1522 1523 DISAS_INSN(sbcd_mem) 1524 { 1525 TCGv src, dest, addr; 1526 1527 gen_flush_flags(s); /* !Z is sticky */ 1528 1529 /* Indirect pre-decrement load (mode 4) */ 1530 1531 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, 1532 NULL_QREG, NULL, EA_LOADU); 1533 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, 1534 NULL_QREG, &addr, EA_LOADU); 1535 1536 bcd_sub(dest, src); 1537 1538 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); 1539 1540 bcd_flags(dest); 1541 } 1542 1543 DISAS_INSN(nbcd) 1544 { 1545 TCGv src, dest; 1546 TCGv addr; 1547 1548 gen_flush_flags(s); /* !Z is sticky */ 1549 1550 SRC_EA(env, src, OS_BYTE, 0, &addr); 1551 1552 dest = tcg_const_i32(0); 1553 bcd_sub(dest, src); 1554 1555 DEST_EA(env, insn, OS_BYTE, dest, &addr); 1556 1557 bcd_flags(dest); 1558 1559 tcg_temp_free(dest); 1560 } 1561 1562 DISAS_INSN(addsub) 1563 { 1564 TCGv reg; 1565 TCGv dest; 1566 TCGv src; 1567 TCGv tmp; 1568 TCGv addr; 1569 int add; 1570 int opsize; 1571 1572 add = (insn & 0x4000) != 0; 1573 opsize = insn_opsize(insn); 1574 reg = gen_extend(DREG(insn, 9), opsize, 1); 1575 dest = tcg_temp_new(); 1576 if (insn & 0x100) { 1577 SRC_EA(env, tmp, opsize, 1, &addr); 1578 src = reg; 1579 } else { 1580 tmp = reg; 1581 SRC_EA(env, src, opsize, 1, NULL); 1582 } 1583 if (add) { 1584 tcg_gen_add_i32(dest, tmp, src); 1585 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); 1586 set_cc_op(s, CC_OP_ADDB + opsize); 1587 } else { 1588 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); 1589 tcg_gen_sub_i32(dest, tmp, src); 1590 set_cc_op(s, CC_OP_SUBB + opsize); 1591 } 1592 gen_update_cc_add(dest, src, opsize); 1593 if (insn & 0x100) { 1594 DEST_EA(env, insn, opsize, dest, &addr); 1595 } else { 1596 gen_partset_reg(opsize, DREG(insn, 9), dest); 1597 } 1598 tcg_temp_free(dest); 1599 } 1600 1601 /* Reverse the order of the bits in REG. */ 1602 DISAS_INSN(bitrev) 1603 { 1604 TCGv reg; 1605 reg = DREG(insn, 0); 1606 gen_helper_bitrev(reg, reg); 1607 } 1608 1609 DISAS_INSN(bitop_reg) 1610 { 1611 int opsize; 1612 int op; 1613 TCGv src1; 1614 TCGv src2; 1615 TCGv tmp; 1616 TCGv addr; 1617 TCGv dest; 1618 1619 if ((insn & 0x38) != 0) 1620 opsize = OS_BYTE; 1621 else 1622 opsize = OS_LONG; 1623 op = (insn >> 6) & 3; 1624 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); 1625 1626 gen_flush_flags(s); 1627 src2 = tcg_temp_new(); 1628 if (opsize == OS_BYTE) 1629 tcg_gen_andi_i32(src2, DREG(insn, 9), 7); 1630 else 1631 tcg_gen_andi_i32(src2, DREG(insn, 9), 31); 1632 1633 tmp = tcg_const_i32(1); 1634 tcg_gen_shl_i32(tmp, tmp, src2); 1635 tcg_temp_free(src2); 1636 1637 tcg_gen_and_i32(QREG_CC_Z, src1, tmp); 1638 1639 dest = tcg_temp_new(); 1640 switch (op) { 1641 case 1: /* bchg */ 1642 tcg_gen_xor_i32(dest, src1, tmp); 1643 break; 1644 case 2: /* bclr */ 1645 tcg_gen_andc_i32(dest, src1, tmp); 1646 break; 1647 case 3: /* bset */ 1648 tcg_gen_or_i32(dest, src1, tmp); 1649 break; 1650 default: /* btst */ 1651 break; 1652 } 1653 tcg_temp_free(tmp); 1654 if (op) { 1655 DEST_EA(env, insn, opsize, dest, &addr); 1656 } 1657 tcg_temp_free(dest); 1658 } 1659 1660 DISAS_INSN(sats) 1661 { 1662 TCGv reg; 1663 reg = DREG(insn, 0); 1664 gen_flush_flags(s); 1665 gen_helper_sats(reg, reg, QREG_CC_V); 1666 gen_logic_cc(s, reg, OS_LONG); 1667 } 1668 1669 static void gen_push(DisasContext *s, TCGv val) 1670 { 1671 TCGv tmp; 1672 1673 tmp = tcg_temp_new(); 1674 tcg_gen_subi_i32(tmp, QREG_SP, 4); 1675 gen_store(s, OS_LONG, tmp, val); 1676 tcg_gen_mov_i32(QREG_SP, tmp); 1677 tcg_temp_free(tmp); 1678 } 1679 1680 static TCGv mreg(int reg) 1681 { 1682 if (reg < 8) { 1683 /* Dx */ 1684 return cpu_dregs[reg]; 1685 } 1686 /* Ax */ 1687 return cpu_aregs[reg & 7]; 1688 } 1689 1690 DISAS_INSN(movem) 1691 { 1692 TCGv addr, incr, tmp, r[16]; 1693 int is_load = (insn & 0x0400) != 0; 1694 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD; 1695 uint16_t mask = read_im16(env, s); 1696 int mode = extract32(insn, 3, 3); 1697 int reg0 = REG(insn, 0); 1698 int i; 1699 1700 tmp = cpu_aregs[reg0]; 1701 1702 switch (mode) { 1703 case 0: /* data register direct */ 1704 case 1: /* addr register direct */ 1705 do_addr_fault: 1706 gen_addr_fault(s); 1707 return; 1708 1709 case 2: /* indirect */ 1710 break; 1711 1712 case 3: /* indirect post-increment */ 1713 if (!is_load) { 1714 /* post-increment is not allowed */ 1715 goto do_addr_fault; 1716 } 1717 break; 1718 1719 case 4: /* indirect pre-decrement */ 1720 if (is_load) { 1721 /* pre-decrement is not allowed */ 1722 goto do_addr_fault; 1723 } 1724 /* We want a bare copy of the address reg, without any pre-decrement 1725 adjustment, as gen_lea would provide. */ 1726 break; 1727 1728 default: 1729 tmp = gen_lea_mode(env, s, mode, reg0, opsize); 1730 if (IS_NULL_QREG(tmp)) { 1731 goto do_addr_fault; 1732 } 1733 break; 1734 } 1735 1736 addr = tcg_temp_new(); 1737 tcg_gen_mov_i32(addr, tmp); 1738 incr = tcg_const_i32(opsize_bytes(opsize)); 1739 1740 if (is_load) { 1741 /* memory to register */ 1742 for (i = 0; i < 16; i++) { 1743 if (mask & (1 << i)) { 1744 r[i] = gen_load(s, opsize, addr, 1); 1745 tcg_gen_add_i32(addr, addr, incr); 1746 } 1747 } 1748 for (i = 0; i < 16; i++) { 1749 if (mask & (1 << i)) { 1750 tcg_gen_mov_i32(mreg(i), r[i]); 1751 tcg_temp_free(r[i]); 1752 } 1753 } 1754 if (mode == 3) { 1755 /* post-increment: movem (An)+,X */ 1756 tcg_gen_mov_i32(cpu_aregs[reg0], addr); 1757 } 1758 } else { 1759 /* register to memory */ 1760 if (mode == 4) { 1761 /* pre-decrement: movem X,-(An) */ 1762 for (i = 15; i >= 0; i--) { 1763 if ((mask << i) & 0x8000) { 1764 tcg_gen_sub_i32(addr, addr, incr); 1765 if (reg0 + 8 == i && 1766 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) { 1767 /* M68020+: if the addressing register is the 1768 * register moved to memory, the value written 1769 * is the initial value decremented by the size of 1770 * the operation, regardless of how many actual 1771 * stores have been performed until this point. 1772 * M68000/M68010: the value is the initial value. 1773 */ 1774 tmp = tcg_temp_new(); 1775 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr); 1776 gen_store(s, opsize, addr, tmp); 1777 tcg_temp_free(tmp); 1778 } else { 1779 gen_store(s, opsize, addr, mreg(i)); 1780 } 1781 } 1782 } 1783 tcg_gen_mov_i32(cpu_aregs[reg0], addr); 1784 } else { 1785 for (i = 0; i < 16; i++) { 1786 if (mask & (1 << i)) { 1787 gen_store(s, opsize, addr, mreg(i)); 1788 tcg_gen_add_i32(addr, addr, incr); 1789 } 1790 } 1791 } 1792 } 1793 1794 tcg_temp_free(incr); 1795 tcg_temp_free(addr); 1796 } 1797 1798 DISAS_INSN(bitop_im) 1799 { 1800 int opsize; 1801 int op; 1802 TCGv src1; 1803 uint32_t mask; 1804 int bitnum; 1805 TCGv tmp; 1806 TCGv addr; 1807 1808 if ((insn & 0x38) != 0) 1809 opsize = OS_BYTE; 1810 else 1811 opsize = OS_LONG; 1812 op = (insn >> 6) & 3; 1813 1814 bitnum = read_im16(env, s); 1815 if (m68k_feature(s->env, M68K_FEATURE_M68000)) { 1816 if (bitnum & 0xfe00) { 1817 disas_undef(env, s, insn); 1818 return; 1819 } 1820 } else { 1821 if (bitnum & 0xff00) { 1822 disas_undef(env, s, insn); 1823 return; 1824 } 1825 } 1826 1827 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); 1828 1829 gen_flush_flags(s); 1830 if (opsize == OS_BYTE) 1831 bitnum &= 7; 1832 else 1833 bitnum &= 31; 1834 mask = 1 << bitnum; 1835 1836 tcg_gen_andi_i32(QREG_CC_Z, src1, mask); 1837 1838 if (op) { 1839 tmp = tcg_temp_new(); 1840 switch (op) { 1841 case 1: /* bchg */ 1842 tcg_gen_xori_i32(tmp, src1, mask); 1843 break; 1844 case 2: /* bclr */ 1845 tcg_gen_andi_i32(tmp, src1, ~mask); 1846 break; 1847 case 3: /* bset */ 1848 tcg_gen_ori_i32(tmp, src1, mask); 1849 break; 1850 default: /* btst */ 1851 break; 1852 } 1853 DEST_EA(env, insn, opsize, tmp, &addr); 1854 tcg_temp_free(tmp); 1855 } 1856 } 1857 1858 DISAS_INSN(arith_im) 1859 { 1860 int op; 1861 TCGv im; 1862 TCGv src1; 1863 TCGv dest; 1864 TCGv addr; 1865 int opsize; 1866 1867 op = (insn >> 9) & 7; 1868 opsize = insn_opsize(insn); 1869 switch (opsize) { 1870 case OS_BYTE: 1871 im = tcg_const_i32((int8_t)read_im8(env, s)); 1872 break; 1873 case OS_WORD: 1874 im = tcg_const_i32((int16_t)read_im16(env, s)); 1875 break; 1876 case OS_LONG: 1877 im = tcg_const_i32(read_im32(env, s)); 1878 break; 1879 default: 1880 abort(); 1881 } 1882 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr); 1883 dest = tcg_temp_new(); 1884 switch (op) { 1885 case 0: /* ori */ 1886 tcg_gen_or_i32(dest, src1, im); 1887 gen_logic_cc(s, dest, opsize); 1888 break; 1889 case 1: /* andi */ 1890 tcg_gen_and_i32(dest, src1, im); 1891 gen_logic_cc(s, dest, opsize); 1892 break; 1893 case 2: /* subi */ 1894 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im); 1895 tcg_gen_sub_i32(dest, src1, im); 1896 gen_update_cc_add(dest, im, opsize); 1897 set_cc_op(s, CC_OP_SUBB + opsize); 1898 break; 1899 case 3: /* addi */ 1900 tcg_gen_add_i32(dest, src1, im); 1901 gen_update_cc_add(dest, im, opsize); 1902 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im); 1903 set_cc_op(s, CC_OP_ADDB + opsize); 1904 break; 1905 case 5: /* eori */ 1906 tcg_gen_xor_i32(dest, src1, im); 1907 gen_logic_cc(s, dest, opsize); 1908 break; 1909 case 6: /* cmpi */ 1910 gen_update_cc_cmp(s, src1, im, opsize); 1911 break; 1912 default: 1913 abort(); 1914 } 1915 tcg_temp_free(im); 1916 if (op != 6) { 1917 DEST_EA(env, insn, opsize, dest, &addr); 1918 } 1919 tcg_temp_free(dest); 1920 } 1921 1922 DISAS_INSN(cas) 1923 { 1924 int opsize; 1925 TCGv addr; 1926 uint16_t ext; 1927 TCGv load; 1928 TCGv cmp; 1929 TCGMemOp opc; 1930 1931 switch ((insn >> 9) & 3) { 1932 case 1: 1933 opsize = OS_BYTE; 1934 opc = MO_SB; 1935 break; 1936 case 2: 1937 opsize = OS_WORD; 1938 opc = MO_TESW; 1939 break; 1940 case 3: 1941 opsize = OS_LONG; 1942 opc = MO_TESL; 1943 break; 1944 default: 1945 g_assert_not_reached(); 1946 } 1947 1948 ext = read_im16(env, s); 1949 1950 /* cas Dc,Du,<EA> */ 1951 1952 addr = gen_lea(env, s, insn, opsize); 1953 if (IS_NULL_QREG(addr)) { 1954 gen_addr_fault(s); 1955 return; 1956 } 1957 1958 cmp = gen_extend(DREG(ext, 0), opsize, 1); 1959 1960 /* if <EA> == Dc then 1961 * <EA> = Du 1962 * Dc = <EA> (because <EA> == Dc) 1963 * else 1964 * Dc = <EA> 1965 */ 1966 1967 load = tcg_temp_new(); 1968 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6), 1969 IS_USER(s), opc); 1970 /* update flags before setting cmp to load */ 1971 gen_update_cc_cmp(s, load, cmp, opsize); 1972 gen_partset_reg(opsize, DREG(ext, 0), load); 1973 1974 tcg_temp_free(load); 1975 1976 switch (extract32(insn, 3, 3)) { 1977 case 3: /* Indirect postincrement. */ 1978 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize)); 1979 break; 1980 case 4: /* Indirect predecrememnt. */ 1981 tcg_gen_mov_i32(AREG(insn, 0), addr); 1982 break; 1983 } 1984 } 1985 1986 DISAS_INSN(cas2w) 1987 { 1988 uint16_t ext1, ext2; 1989 TCGv addr1, addr2; 1990 TCGv regs; 1991 1992 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ 1993 1994 ext1 = read_im16(env, s); 1995 1996 if (ext1 & 0x8000) { 1997 /* Address Register */ 1998 addr1 = AREG(ext1, 12); 1999 } else { 2000 /* Data Register */ 2001 addr1 = DREG(ext1, 12); 2002 } 2003 2004 ext2 = read_im16(env, s); 2005 if (ext2 & 0x8000) { 2006 /* Address Register */ 2007 addr2 = AREG(ext2, 12); 2008 } else { 2009 /* Data Register */ 2010 addr2 = DREG(ext2, 12); 2011 } 2012 2013 /* if (R1) == Dc1 && (R2) == Dc2 then 2014 * (R1) = Du1 2015 * (R2) = Du2 2016 * else 2017 * Dc1 = (R1) 2018 * Dc2 = (R2) 2019 */ 2020 2021 regs = tcg_const_i32(REG(ext2, 6) | 2022 (REG(ext1, 6) << 3) | 2023 (REG(ext2, 0) << 6) | 2024 (REG(ext1, 0) << 9)); 2025 gen_helper_cas2w(cpu_env, regs, addr1, addr2); 2026 tcg_temp_free(regs); 2027 2028 /* Note that cas2w also assigned to env->cc_op. */ 2029 s->cc_op = CC_OP_CMPW; 2030 s->cc_op_synced = 1; 2031 } 2032 2033 DISAS_INSN(cas2l) 2034 { 2035 uint16_t ext1, ext2; 2036 TCGv addr1, addr2, regs; 2037 2038 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ 2039 2040 ext1 = read_im16(env, s); 2041 2042 if (ext1 & 0x8000) { 2043 /* Address Register */ 2044 addr1 = AREG(ext1, 12); 2045 } else { 2046 /* Data Register */ 2047 addr1 = DREG(ext1, 12); 2048 } 2049 2050 ext2 = read_im16(env, s); 2051 if (ext2 & 0x8000) { 2052 /* Address Register */ 2053 addr2 = AREG(ext2, 12); 2054 } else { 2055 /* Data Register */ 2056 addr2 = DREG(ext2, 12); 2057 } 2058 2059 /* if (R1) == Dc1 && (R2) == Dc2 then 2060 * (R1) = Du1 2061 * (R2) = Du2 2062 * else 2063 * Dc1 = (R1) 2064 * Dc2 = (R2) 2065 */ 2066 2067 regs = tcg_const_i32(REG(ext2, 6) | 2068 (REG(ext1, 6) << 3) | 2069 (REG(ext2, 0) << 6) | 2070 (REG(ext1, 0) << 9)); 2071 gen_helper_cas2l(cpu_env, regs, addr1, addr2); 2072 tcg_temp_free(regs); 2073 2074 /* Note that cas2l also assigned to env->cc_op. */ 2075 s->cc_op = CC_OP_CMPL; 2076 s->cc_op_synced = 1; 2077 } 2078 2079 DISAS_INSN(byterev) 2080 { 2081 TCGv reg; 2082 2083 reg = DREG(insn, 0); 2084 tcg_gen_bswap32_i32(reg, reg); 2085 } 2086 2087 DISAS_INSN(move) 2088 { 2089 TCGv src; 2090 TCGv dest; 2091 int op; 2092 int opsize; 2093 2094 switch (insn >> 12) { 2095 case 1: /* move.b */ 2096 opsize = OS_BYTE; 2097 break; 2098 case 2: /* move.l */ 2099 opsize = OS_LONG; 2100 break; 2101 case 3: /* move.w */ 2102 opsize = OS_WORD; 2103 break; 2104 default: 2105 abort(); 2106 } 2107 SRC_EA(env, src, opsize, 1, NULL); 2108 op = (insn >> 6) & 7; 2109 if (op == 1) { 2110 /* movea */ 2111 /* The value will already have been sign extended. */ 2112 dest = AREG(insn, 9); 2113 tcg_gen_mov_i32(dest, src); 2114 } else { 2115 /* normal move */ 2116 uint16_t dest_ea; 2117 dest_ea = ((insn >> 9) & 7) | (op << 3); 2118 DEST_EA(env, dest_ea, opsize, src, NULL); 2119 /* This will be correct because loads sign extend. */ 2120 gen_logic_cc(s, src, opsize); 2121 } 2122 } 2123 2124 DISAS_INSN(negx) 2125 { 2126 TCGv z; 2127 TCGv src; 2128 TCGv addr; 2129 int opsize; 2130 2131 opsize = insn_opsize(insn); 2132 SRC_EA(env, src, opsize, 1, &addr); 2133 2134 gen_flush_flags(s); /* compute old Z */ 2135 2136 /* Perform substract with borrow. 2137 * (X, N) = -(src + X); 2138 */ 2139 2140 z = tcg_const_i32(0); 2141 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z); 2142 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X); 2143 tcg_temp_free(z); 2144 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); 2145 2146 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); 2147 2148 /* Compute signed-overflow for negation. The normal formula for 2149 * subtraction is (res ^ src) & (src ^ dest), but with dest==0 2150 * this simplies to res & src. 2151 */ 2152 2153 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src); 2154 2155 /* Copy the rest of the results into place. */ 2156 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ 2157 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); 2158 2159 set_cc_op(s, CC_OP_FLAGS); 2160 2161 /* result is in QREG_CC_N */ 2162 2163 DEST_EA(env, insn, opsize, QREG_CC_N, &addr); 2164 } 2165 2166 DISAS_INSN(lea) 2167 { 2168 TCGv reg; 2169 TCGv tmp; 2170 2171 reg = AREG(insn, 9); 2172 tmp = gen_lea(env, s, insn, OS_LONG); 2173 if (IS_NULL_QREG(tmp)) { 2174 gen_addr_fault(s); 2175 return; 2176 } 2177 tcg_gen_mov_i32(reg, tmp); 2178 } 2179 2180 DISAS_INSN(clr) 2181 { 2182 int opsize; 2183 TCGv zero; 2184 2185 zero = tcg_const_i32(0); 2186 2187 opsize = insn_opsize(insn); 2188 DEST_EA(env, insn, opsize, zero, NULL); 2189 gen_logic_cc(s, zero, opsize); 2190 tcg_temp_free(zero); 2191 } 2192 2193 static TCGv gen_get_ccr(DisasContext *s) 2194 { 2195 TCGv dest; 2196 2197 gen_flush_flags(s); 2198 update_cc_op(s); 2199 dest = tcg_temp_new(); 2200 gen_helper_get_ccr(dest, cpu_env); 2201 return dest; 2202 } 2203 2204 DISAS_INSN(move_from_ccr) 2205 { 2206 TCGv ccr; 2207 2208 ccr = gen_get_ccr(s); 2209 DEST_EA(env, insn, OS_WORD, ccr, NULL); 2210 } 2211 2212 DISAS_INSN(neg) 2213 { 2214 TCGv src1; 2215 TCGv dest; 2216 TCGv addr; 2217 int opsize; 2218 2219 opsize = insn_opsize(insn); 2220 SRC_EA(env, src1, opsize, 1, &addr); 2221 dest = tcg_temp_new(); 2222 tcg_gen_neg_i32(dest, src1); 2223 set_cc_op(s, CC_OP_SUBB + opsize); 2224 gen_update_cc_add(dest, src1, opsize); 2225 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0); 2226 DEST_EA(env, insn, opsize, dest, &addr); 2227 tcg_temp_free(dest); 2228 } 2229 2230 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) 2231 { 2232 if (ccr_only) { 2233 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0); 2234 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0); 2235 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1); 2236 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); 2237 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); 2238 } else { 2239 gen_helper_set_sr(cpu_env, tcg_const_i32(val)); 2240 } 2241 set_cc_op(s, CC_OP_FLAGS); 2242 } 2243 2244 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, 2245 int ccr_only) 2246 { 2247 if ((insn & 0x38) == 0) { 2248 if (ccr_only) { 2249 gen_helper_set_ccr(cpu_env, DREG(insn, 0)); 2250 } else { 2251 gen_helper_set_sr(cpu_env, DREG(insn, 0)); 2252 } 2253 set_cc_op(s, CC_OP_FLAGS); 2254 } else if ((insn & 0x3f) == 0x3c) { 2255 uint16_t val; 2256 val = read_im16(env, s); 2257 gen_set_sr_im(s, val, ccr_only); 2258 } else { 2259 disas_undef(env, s, insn); 2260 } 2261 } 2262 2263 2264 DISAS_INSN(move_to_ccr) 2265 { 2266 gen_set_sr(env, s, insn, 1); 2267 } 2268 2269 DISAS_INSN(not) 2270 { 2271 TCGv src1; 2272 TCGv dest; 2273 TCGv addr; 2274 int opsize; 2275 2276 opsize = insn_opsize(insn); 2277 SRC_EA(env, src1, opsize, 1, &addr); 2278 dest = tcg_temp_new(); 2279 tcg_gen_not_i32(dest, src1); 2280 DEST_EA(env, insn, opsize, dest, &addr); 2281 gen_logic_cc(s, dest, opsize); 2282 } 2283 2284 DISAS_INSN(swap) 2285 { 2286 TCGv src1; 2287 TCGv src2; 2288 TCGv reg; 2289 2290 src1 = tcg_temp_new(); 2291 src2 = tcg_temp_new(); 2292 reg = DREG(insn, 0); 2293 tcg_gen_shli_i32(src1, reg, 16); 2294 tcg_gen_shri_i32(src2, reg, 16); 2295 tcg_gen_or_i32(reg, src1, src2); 2296 tcg_temp_free(src2); 2297 tcg_temp_free(src1); 2298 gen_logic_cc(s, reg, OS_LONG); 2299 } 2300 2301 DISAS_INSN(bkpt) 2302 { 2303 gen_exception(s, s->pc - 2, EXCP_DEBUG); 2304 } 2305 2306 DISAS_INSN(pea) 2307 { 2308 TCGv tmp; 2309 2310 tmp = gen_lea(env, s, insn, OS_LONG); 2311 if (IS_NULL_QREG(tmp)) { 2312 gen_addr_fault(s); 2313 return; 2314 } 2315 gen_push(s, tmp); 2316 } 2317 2318 DISAS_INSN(ext) 2319 { 2320 int op; 2321 TCGv reg; 2322 TCGv tmp; 2323 2324 reg = DREG(insn, 0); 2325 op = (insn >> 6) & 7; 2326 tmp = tcg_temp_new(); 2327 if (op == 3) 2328 tcg_gen_ext16s_i32(tmp, reg); 2329 else 2330 tcg_gen_ext8s_i32(tmp, reg); 2331 if (op == 2) 2332 gen_partset_reg(OS_WORD, reg, tmp); 2333 else 2334 tcg_gen_mov_i32(reg, tmp); 2335 gen_logic_cc(s, tmp, OS_LONG); 2336 tcg_temp_free(tmp); 2337 } 2338 2339 DISAS_INSN(tst) 2340 { 2341 int opsize; 2342 TCGv tmp; 2343 2344 opsize = insn_opsize(insn); 2345 SRC_EA(env, tmp, opsize, 1, NULL); 2346 gen_logic_cc(s, tmp, opsize); 2347 } 2348 2349 DISAS_INSN(pulse) 2350 { 2351 /* Implemented as a NOP. */ 2352 } 2353 2354 DISAS_INSN(illegal) 2355 { 2356 gen_exception(s, s->pc - 2, EXCP_ILLEGAL); 2357 } 2358 2359 /* ??? This should be atomic. */ 2360 DISAS_INSN(tas) 2361 { 2362 TCGv dest; 2363 TCGv src1; 2364 TCGv addr; 2365 2366 dest = tcg_temp_new(); 2367 SRC_EA(env, src1, OS_BYTE, 1, &addr); 2368 gen_logic_cc(s, src1, OS_BYTE); 2369 tcg_gen_ori_i32(dest, src1, 0x80); 2370 DEST_EA(env, insn, OS_BYTE, dest, &addr); 2371 tcg_temp_free(dest); 2372 } 2373 2374 DISAS_INSN(mull) 2375 { 2376 uint16_t ext; 2377 TCGv src1; 2378 int sign; 2379 2380 ext = read_im16(env, s); 2381 2382 sign = ext & 0x800; 2383 2384 if (ext & 0x400) { 2385 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) { 2386 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); 2387 return; 2388 } 2389 2390 SRC_EA(env, src1, OS_LONG, 0, NULL); 2391 2392 if (sign) { 2393 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12)); 2394 } else { 2395 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12)); 2396 } 2397 /* if Dl == Dh, 68040 returns low word */ 2398 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N); 2399 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z); 2400 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); 2401 2402 tcg_gen_movi_i32(QREG_CC_V, 0); 2403 tcg_gen_movi_i32(QREG_CC_C, 0); 2404 2405 set_cc_op(s, CC_OP_FLAGS); 2406 return; 2407 } 2408 SRC_EA(env, src1, OS_LONG, 0, NULL); 2409 if (m68k_feature(s->env, M68K_FEATURE_M68000)) { 2410 tcg_gen_movi_i32(QREG_CC_C, 0); 2411 if (sign) { 2412 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); 2413 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */ 2414 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31); 2415 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z); 2416 } else { 2417 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); 2418 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */ 2419 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C); 2420 } 2421 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); 2422 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N); 2423 2424 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); 2425 2426 set_cc_op(s, CC_OP_FLAGS); 2427 } else { 2428 /* The upper 32 bits of the product are discarded, so 2429 muls.l and mulu.l are functionally equivalent. */ 2430 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12)); 2431 gen_logic_cc(s, DREG(ext, 12), OS_LONG); 2432 } 2433 } 2434 2435 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset) 2436 { 2437 TCGv reg; 2438 TCGv tmp; 2439 2440 reg = AREG(insn, 0); 2441 tmp = tcg_temp_new(); 2442 tcg_gen_subi_i32(tmp, QREG_SP, 4); 2443 gen_store(s, OS_LONG, tmp, reg); 2444 if ((insn & 7) != 7) { 2445 tcg_gen_mov_i32(reg, tmp); 2446 } 2447 tcg_gen_addi_i32(QREG_SP, tmp, offset); 2448 tcg_temp_free(tmp); 2449 } 2450 2451 DISAS_INSN(link) 2452 { 2453 int16_t offset; 2454 2455 offset = read_im16(env, s); 2456 gen_link(s, insn, offset); 2457 } 2458 2459 DISAS_INSN(linkl) 2460 { 2461 int32_t offset; 2462 2463 offset = read_im32(env, s); 2464 gen_link(s, insn, offset); 2465 } 2466 2467 DISAS_INSN(unlk) 2468 { 2469 TCGv src; 2470 TCGv reg; 2471 TCGv tmp; 2472 2473 src = tcg_temp_new(); 2474 reg = AREG(insn, 0); 2475 tcg_gen_mov_i32(src, reg); 2476 tmp = gen_load(s, OS_LONG, src, 0); 2477 tcg_gen_mov_i32(reg, tmp); 2478 tcg_gen_addi_i32(QREG_SP, src, 4); 2479 tcg_temp_free(src); 2480 } 2481 2482 DISAS_INSN(nop) 2483 { 2484 } 2485 2486 DISAS_INSN(rtd) 2487 { 2488 TCGv tmp; 2489 int16_t offset = read_im16(env, s); 2490 2491 tmp = gen_load(s, OS_LONG, QREG_SP, 0); 2492 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4); 2493 gen_jmp(s, tmp); 2494 } 2495 2496 DISAS_INSN(rts) 2497 { 2498 TCGv tmp; 2499 2500 tmp = gen_load(s, OS_LONG, QREG_SP, 0); 2501 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); 2502 gen_jmp(s, tmp); 2503 } 2504 2505 DISAS_INSN(jump) 2506 { 2507 TCGv tmp; 2508 2509 /* Load the target address first to ensure correct exception 2510 behavior. */ 2511 tmp = gen_lea(env, s, insn, OS_LONG); 2512 if (IS_NULL_QREG(tmp)) { 2513 gen_addr_fault(s); 2514 return; 2515 } 2516 if ((insn & 0x40) == 0) { 2517 /* jsr */ 2518 gen_push(s, tcg_const_i32(s->pc)); 2519 } 2520 gen_jmp(s, tmp); 2521 } 2522 2523 DISAS_INSN(addsubq) 2524 { 2525 TCGv src; 2526 TCGv dest; 2527 TCGv val; 2528 int imm; 2529 TCGv addr; 2530 int opsize; 2531 2532 if ((insn & 070) == 010) { 2533 /* Operation on address register is always long. */ 2534 opsize = OS_LONG; 2535 } else { 2536 opsize = insn_opsize(insn); 2537 } 2538 SRC_EA(env, src, opsize, 1, &addr); 2539 imm = (insn >> 9) & 7; 2540 if (imm == 0) { 2541 imm = 8; 2542 } 2543 val = tcg_const_i32(imm); 2544 dest = tcg_temp_new(); 2545 tcg_gen_mov_i32(dest, src); 2546 if ((insn & 0x38) == 0x08) { 2547 /* Don't update condition codes if the destination is an 2548 address register. */ 2549 if (insn & 0x0100) { 2550 tcg_gen_sub_i32(dest, dest, val); 2551 } else { 2552 tcg_gen_add_i32(dest, dest, val); 2553 } 2554 } else { 2555 if (insn & 0x0100) { 2556 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); 2557 tcg_gen_sub_i32(dest, dest, val); 2558 set_cc_op(s, CC_OP_SUBB + opsize); 2559 } else { 2560 tcg_gen_add_i32(dest, dest, val); 2561 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); 2562 set_cc_op(s, CC_OP_ADDB + opsize); 2563 } 2564 gen_update_cc_add(dest, val, opsize); 2565 } 2566 tcg_temp_free(val); 2567 DEST_EA(env, insn, opsize, dest, &addr); 2568 tcg_temp_free(dest); 2569 } 2570 2571 DISAS_INSN(tpf) 2572 { 2573 switch (insn & 7) { 2574 case 2: /* One extension word. */ 2575 s->pc += 2; 2576 break; 2577 case 3: /* Two extension words. */ 2578 s->pc += 4; 2579 break; 2580 case 4: /* No extension words. */ 2581 break; 2582 default: 2583 disas_undef(env, s, insn); 2584 } 2585 } 2586 2587 DISAS_INSN(branch) 2588 { 2589 int32_t offset; 2590 uint32_t base; 2591 int op; 2592 TCGLabel *l1; 2593 2594 base = s->pc; 2595 op = (insn >> 8) & 0xf; 2596 offset = (int8_t)insn; 2597 if (offset == 0) { 2598 offset = (int16_t)read_im16(env, s); 2599 } else if (offset == -1) { 2600 offset = read_im32(env, s); 2601 } 2602 if (op == 1) { 2603 /* bsr */ 2604 gen_push(s, tcg_const_i32(s->pc)); 2605 } 2606 if (op > 1) { 2607 /* Bcc */ 2608 l1 = gen_new_label(); 2609 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); 2610 gen_jmp_tb(s, 1, base + offset); 2611 gen_set_label(l1); 2612 gen_jmp_tb(s, 0, s->pc); 2613 } else { 2614 /* Unconditional branch. */ 2615 gen_jmp_tb(s, 0, base + offset); 2616 } 2617 } 2618 2619 DISAS_INSN(moveq) 2620 { 2621 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn); 2622 gen_logic_cc(s, DREG(insn, 9), OS_LONG); 2623 } 2624 2625 DISAS_INSN(mvzs) 2626 { 2627 int opsize; 2628 TCGv src; 2629 TCGv reg; 2630 2631 if (insn & 0x40) 2632 opsize = OS_WORD; 2633 else 2634 opsize = OS_BYTE; 2635 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); 2636 reg = DREG(insn, 9); 2637 tcg_gen_mov_i32(reg, src); 2638 gen_logic_cc(s, src, opsize); 2639 } 2640 2641 DISAS_INSN(or) 2642 { 2643 TCGv reg; 2644 TCGv dest; 2645 TCGv src; 2646 TCGv addr; 2647 int opsize; 2648 2649 opsize = insn_opsize(insn); 2650 reg = gen_extend(DREG(insn, 9), opsize, 0); 2651 dest = tcg_temp_new(); 2652 if (insn & 0x100) { 2653 SRC_EA(env, src, opsize, 0, &addr); 2654 tcg_gen_or_i32(dest, src, reg); 2655 DEST_EA(env, insn, opsize, dest, &addr); 2656 } else { 2657 SRC_EA(env, src, opsize, 0, NULL); 2658 tcg_gen_or_i32(dest, src, reg); 2659 gen_partset_reg(opsize, DREG(insn, 9), dest); 2660 } 2661 gen_logic_cc(s, dest, opsize); 2662 tcg_temp_free(dest); 2663 } 2664 2665 DISAS_INSN(suba) 2666 { 2667 TCGv src; 2668 TCGv reg; 2669 2670 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL); 2671 reg = AREG(insn, 9); 2672 tcg_gen_sub_i32(reg, reg, src); 2673 } 2674 2675 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize) 2676 { 2677 TCGv tmp; 2678 2679 gen_flush_flags(s); /* compute old Z */ 2680 2681 /* Perform substract with borrow. 2682 * (X, N) = dest - (src + X); 2683 */ 2684 2685 tmp = tcg_const_i32(0); 2686 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp); 2687 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X); 2688 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); 2689 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); 2690 2691 /* Compute signed-overflow for substract. */ 2692 2693 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest); 2694 tcg_gen_xor_i32(tmp, dest, src); 2695 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp); 2696 tcg_temp_free(tmp); 2697 2698 /* Copy the rest of the results into place. */ 2699 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ 2700 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); 2701 2702 set_cc_op(s, CC_OP_FLAGS); 2703 2704 /* result is in QREG_CC_N */ 2705 } 2706 2707 DISAS_INSN(subx_reg) 2708 { 2709 TCGv dest; 2710 TCGv src; 2711 int opsize; 2712 2713 opsize = insn_opsize(insn); 2714 2715 src = gen_extend(DREG(insn, 0), opsize, 1); 2716 dest = gen_extend(DREG(insn, 9), opsize, 1); 2717 2718 gen_subx(s, src, dest, opsize); 2719 2720 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N); 2721 } 2722 2723 DISAS_INSN(subx_mem) 2724 { 2725 TCGv src; 2726 TCGv addr_src; 2727 TCGv dest; 2728 TCGv addr_dest; 2729 int opsize; 2730 2731 opsize = insn_opsize(insn); 2732 2733 addr_src = AREG(insn, 0); 2734 tcg_gen_subi_i32(addr_src, addr_src, opsize); 2735 src = gen_load(s, opsize, addr_src, 1); 2736 2737 addr_dest = AREG(insn, 9); 2738 tcg_gen_subi_i32(addr_dest, addr_dest, opsize); 2739 dest = gen_load(s, opsize, addr_dest, 1); 2740 2741 gen_subx(s, src, dest, opsize); 2742 2743 gen_store(s, opsize, addr_dest, QREG_CC_N); 2744 } 2745 2746 DISAS_INSN(mov3q) 2747 { 2748 TCGv src; 2749 int val; 2750 2751 val = (insn >> 9) & 7; 2752 if (val == 0) 2753 val = -1; 2754 src = tcg_const_i32(val); 2755 gen_logic_cc(s, src, OS_LONG); 2756 DEST_EA(env, insn, OS_LONG, src, NULL); 2757 tcg_temp_free(src); 2758 } 2759 2760 DISAS_INSN(cmp) 2761 { 2762 TCGv src; 2763 TCGv reg; 2764 int opsize; 2765 2766 opsize = insn_opsize(insn); 2767 SRC_EA(env, src, opsize, 1, NULL); 2768 reg = gen_extend(DREG(insn, 9), opsize, 1); 2769 gen_update_cc_cmp(s, reg, src, opsize); 2770 } 2771 2772 DISAS_INSN(cmpa) 2773 { 2774 int opsize; 2775 TCGv src; 2776 TCGv reg; 2777 2778 if (insn & 0x100) { 2779 opsize = OS_LONG; 2780 } else { 2781 opsize = OS_WORD; 2782 } 2783 SRC_EA(env, src, opsize, 1, NULL); 2784 reg = AREG(insn, 9); 2785 gen_update_cc_cmp(s, reg, src, OS_LONG); 2786 } 2787 2788 DISAS_INSN(cmpm) 2789 { 2790 int opsize = insn_opsize(insn); 2791 TCGv src, dst; 2792 2793 /* Post-increment load (mode 3) from Ay. */ 2794 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize, 2795 NULL_QREG, NULL, EA_LOADS); 2796 /* Post-increment load (mode 3) from Ax. */ 2797 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize, 2798 NULL_QREG, NULL, EA_LOADS); 2799 2800 gen_update_cc_cmp(s, dst, src, opsize); 2801 } 2802 2803 DISAS_INSN(eor) 2804 { 2805 TCGv src; 2806 TCGv dest; 2807 TCGv addr; 2808 int opsize; 2809 2810 opsize = insn_opsize(insn); 2811 2812 SRC_EA(env, src, opsize, 0, &addr); 2813 dest = tcg_temp_new(); 2814 tcg_gen_xor_i32(dest, src, DREG(insn, 9)); 2815 gen_logic_cc(s, dest, opsize); 2816 DEST_EA(env, insn, opsize, dest, &addr); 2817 tcg_temp_free(dest); 2818 } 2819 2820 static void do_exg(TCGv reg1, TCGv reg2) 2821 { 2822 TCGv temp = tcg_temp_new(); 2823 tcg_gen_mov_i32(temp, reg1); 2824 tcg_gen_mov_i32(reg1, reg2); 2825 tcg_gen_mov_i32(reg2, temp); 2826 tcg_temp_free(temp); 2827 } 2828 2829 DISAS_INSN(exg_dd) 2830 { 2831 /* exchange Dx and Dy */ 2832 do_exg(DREG(insn, 9), DREG(insn, 0)); 2833 } 2834 2835 DISAS_INSN(exg_aa) 2836 { 2837 /* exchange Ax and Ay */ 2838 do_exg(AREG(insn, 9), AREG(insn, 0)); 2839 } 2840 2841 DISAS_INSN(exg_da) 2842 { 2843 /* exchange Dx and Ay */ 2844 do_exg(DREG(insn, 9), AREG(insn, 0)); 2845 } 2846 2847 DISAS_INSN(and) 2848 { 2849 TCGv src; 2850 TCGv reg; 2851 TCGv dest; 2852 TCGv addr; 2853 int opsize; 2854 2855 dest = tcg_temp_new(); 2856 2857 opsize = insn_opsize(insn); 2858 reg = DREG(insn, 9); 2859 if (insn & 0x100) { 2860 SRC_EA(env, src, opsize, 0, &addr); 2861 tcg_gen_and_i32(dest, src, reg); 2862 DEST_EA(env, insn, opsize, dest, &addr); 2863 } else { 2864 SRC_EA(env, src, opsize, 0, NULL); 2865 tcg_gen_and_i32(dest, src, reg); 2866 gen_partset_reg(opsize, reg, dest); 2867 } 2868 gen_logic_cc(s, dest, opsize); 2869 tcg_temp_free(dest); 2870 } 2871 2872 DISAS_INSN(adda) 2873 { 2874 TCGv src; 2875 TCGv reg; 2876 2877 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL); 2878 reg = AREG(insn, 9); 2879 tcg_gen_add_i32(reg, reg, src); 2880 } 2881 2882 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize) 2883 { 2884 TCGv tmp; 2885 2886 gen_flush_flags(s); /* compute old Z */ 2887 2888 /* Perform addition with carry. 2889 * (X, N) = src + dest + X; 2890 */ 2891 2892 tmp = tcg_const_i32(0); 2893 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp); 2894 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp); 2895 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); 2896 2897 /* Compute signed-overflow for addition. */ 2898 2899 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); 2900 tcg_gen_xor_i32(tmp, dest, src); 2901 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp); 2902 tcg_temp_free(tmp); 2903 2904 /* Copy the rest of the results into place. */ 2905 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ 2906 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); 2907 2908 set_cc_op(s, CC_OP_FLAGS); 2909 2910 /* result is in QREG_CC_N */ 2911 } 2912 2913 DISAS_INSN(addx_reg) 2914 { 2915 TCGv dest; 2916 TCGv src; 2917 int opsize; 2918 2919 opsize = insn_opsize(insn); 2920 2921 dest = gen_extend(DREG(insn, 9), opsize, 1); 2922 src = gen_extend(DREG(insn, 0), opsize, 1); 2923 2924 gen_addx(s, src, dest, opsize); 2925 2926 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N); 2927 } 2928 2929 DISAS_INSN(addx_mem) 2930 { 2931 TCGv src; 2932 TCGv addr_src; 2933 TCGv dest; 2934 TCGv addr_dest; 2935 int opsize; 2936 2937 opsize = insn_opsize(insn); 2938 2939 addr_src = AREG(insn, 0); 2940 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize)); 2941 src = gen_load(s, opsize, addr_src, 1); 2942 2943 addr_dest = AREG(insn, 9); 2944 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize)); 2945 dest = gen_load(s, opsize, addr_dest, 1); 2946 2947 gen_addx(s, src, dest, opsize); 2948 2949 gen_store(s, opsize, addr_dest, QREG_CC_N); 2950 } 2951 2952 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize) 2953 { 2954 int count = (insn >> 9) & 7; 2955 int logical = insn & 8; 2956 int left = insn & 0x100; 2957 int bits = opsize_bytes(opsize) * 8; 2958 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical); 2959 2960 if (count == 0) { 2961 count = 8; 2962 } 2963 2964 tcg_gen_movi_i32(QREG_CC_V, 0); 2965 if (left) { 2966 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count); 2967 tcg_gen_shli_i32(QREG_CC_N, reg, count); 2968 2969 /* Note that ColdFire always clears V (done above), 2970 while M68000 sets if the most significant bit is changed at 2971 any time during the shift operation */ 2972 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { 2973 /* if shift count >= bits, V is (reg != 0) */ 2974 if (count >= bits) { 2975 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V); 2976 } else { 2977 TCGv t0 = tcg_temp_new(); 2978 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1); 2979 tcg_gen_sari_i32(t0, reg, bits - count - 1); 2980 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0); 2981 tcg_temp_free(t0); 2982 } 2983 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); 2984 } 2985 } else { 2986 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); 2987 if (logical) { 2988 tcg_gen_shri_i32(QREG_CC_N, reg, count); 2989 } else { 2990 tcg_gen_sari_i32(QREG_CC_N, reg, count); 2991 } 2992 } 2993 2994 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); 2995 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); 2996 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); 2997 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); 2998 2999 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); 3000 set_cc_op(s, CC_OP_FLAGS); 3001 } 3002 3003 static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize) 3004 { 3005 int logical = insn & 8; 3006 int left = insn & 0x100; 3007 int bits = opsize_bytes(opsize) * 8; 3008 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical); 3009 TCGv s32; 3010 TCGv_i64 t64, s64; 3011 3012 t64 = tcg_temp_new_i64(); 3013 s64 = tcg_temp_new_i64(); 3014 s32 = tcg_temp_new(); 3015 3016 /* Note that m68k truncates the shift count modulo 64, not 32. 3017 In addition, a 64-bit shift makes it easy to find "the last 3018 bit shifted out", for the carry flag. */ 3019 tcg_gen_andi_i32(s32, DREG(insn, 9), 63); 3020 tcg_gen_extu_i32_i64(s64, s32); 3021 tcg_gen_extu_i32_i64(t64, reg); 3022 3023 /* Optimistically set V=0. Also used as a zero source below. */ 3024 tcg_gen_movi_i32(QREG_CC_V, 0); 3025 if (left) { 3026 tcg_gen_shl_i64(t64, t64, s64); 3027 3028 if (opsize == OS_LONG) { 3029 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); 3030 /* Note that C=0 if shift count is 0, and we get that for free. */ 3031 } else { 3032 TCGv zero = tcg_const_i32(0); 3033 tcg_gen_extrl_i64_i32(QREG_CC_N, t64); 3034 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits); 3035 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, 3036 s32, zero, zero, QREG_CC_C); 3037 tcg_temp_free(zero); 3038 } 3039 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); 3040 3041 /* X = C, but only if the shift count was non-zero. */ 3042 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, 3043 QREG_CC_C, QREG_CC_X); 3044 3045 /* M68000 sets V if the most significant bit is changed at 3046 * any time during the shift operation. Do this via creating 3047 * an extension of the sign bit, comparing, and discarding 3048 * the bits below the sign bit. I.e. 3049 * int64_t s = (intN_t)reg; 3050 * int64_t t = (int64_t)(intN_t)reg << count; 3051 * V = ((s ^ t) & (-1 << (bits - 1))) != 0 3052 */ 3053 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { 3054 TCGv_i64 tt = tcg_const_i64(32); 3055 /* if shift is greater than 32, use 32 */ 3056 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64); 3057 tcg_temp_free_i64(tt); 3058 /* Sign extend the input to 64 bits; re-do the shift. */ 3059 tcg_gen_ext_i32_i64(t64, reg); 3060 tcg_gen_shl_i64(s64, t64, s64); 3061 /* Clear all bits that are unchanged. */ 3062 tcg_gen_xor_i64(t64, t64, s64); 3063 /* Ignore the bits below the sign bit. */ 3064 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1)); 3065 /* If any bits remain set, we have overflow. */ 3066 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0); 3067 tcg_gen_extrl_i64_i32(QREG_CC_V, t64); 3068 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); 3069 } 3070 } else { 3071 tcg_gen_shli_i64(t64, t64, 32); 3072 if (logical) { 3073 tcg_gen_shr_i64(t64, t64, s64); 3074 } else { 3075 tcg_gen_sar_i64(t64, t64, s64); 3076 } 3077 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64); 3078 3079 /* Note that C=0 if shift count is 0, and we get that for free. */ 3080 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31); 3081 3082 /* X = C, but only if the shift count was non-zero. */ 3083 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, 3084 QREG_CC_C, QREG_CC_X); 3085 } 3086 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); 3087 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); 3088 3089 tcg_temp_free(s32); 3090 tcg_temp_free_i64(s64); 3091 tcg_temp_free_i64(t64); 3092 3093 /* Write back the result. */ 3094 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); 3095 set_cc_op(s, CC_OP_FLAGS); 3096 } 3097 3098 DISAS_INSN(shift8_im) 3099 { 3100 shift_im(s, insn, OS_BYTE); 3101 } 3102 3103 DISAS_INSN(shift16_im) 3104 { 3105 shift_im(s, insn, OS_WORD); 3106 } 3107 3108 DISAS_INSN(shift_im) 3109 { 3110 shift_im(s, insn, OS_LONG); 3111 } 3112 3113 DISAS_INSN(shift8_reg) 3114 { 3115 shift_reg(s, insn, OS_BYTE); 3116 } 3117 3118 DISAS_INSN(shift16_reg) 3119 { 3120 shift_reg(s, insn, OS_WORD); 3121 } 3122 3123 DISAS_INSN(shift_reg) 3124 { 3125 shift_reg(s, insn, OS_LONG); 3126 } 3127 3128 DISAS_INSN(shift_mem) 3129 { 3130 int logical = insn & 8; 3131 int left = insn & 0x100; 3132 TCGv src; 3133 TCGv addr; 3134 3135 SRC_EA(env, src, OS_WORD, !logical, &addr); 3136 tcg_gen_movi_i32(QREG_CC_V, 0); 3137 if (left) { 3138 tcg_gen_shri_i32(QREG_CC_C, src, 15); 3139 tcg_gen_shli_i32(QREG_CC_N, src, 1); 3140 3141 /* Note that ColdFire always clears V, 3142 while M68000 sets if the most significant bit is changed at 3143 any time during the shift operation */ 3144 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { 3145 src = gen_extend(src, OS_WORD, 1); 3146 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); 3147 } 3148 } else { 3149 tcg_gen_mov_i32(QREG_CC_C, src); 3150 if (logical) { 3151 tcg_gen_shri_i32(QREG_CC_N, src, 1); 3152 } else { 3153 tcg_gen_sari_i32(QREG_CC_N, src, 1); 3154 } 3155 } 3156 3157 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1); 3158 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); 3159 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); 3160 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); 3161 3162 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr); 3163 set_cc_op(s, CC_OP_FLAGS); 3164 } 3165 3166 static void rotate(TCGv reg, TCGv shift, int left, int size) 3167 { 3168 switch (size) { 3169 case 8: 3170 /* Replicate the 8-bit input so that a 32-bit rotate works. */ 3171 tcg_gen_ext8u_i32(reg, reg); 3172 tcg_gen_muli_i32(reg, reg, 0x01010101); 3173 goto do_long; 3174 case 16: 3175 /* Replicate the 16-bit input so that a 32-bit rotate works. */ 3176 tcg_gen_deposit_i32(reg, reg, reg, 16, 16); 3177 goto do_long; 3178 do_long: 3179 default: 3180 if (left) { 3181 tcg_gen_rotl_i32(reg, reg, shift); 3182 } else { 3183 tcg_gen_rotr_i32(reg, reg, shift); 3184 } 3185 } 3186 3187 /* compute flags */ 3188 3189 switch (size) { 3190 case 8: 3191 tcg_gen_ext8s_i32(reg, reg); 3192 break; 3193 case 16: 3194 tcg_gen_ext16s_i32(reg, reg); 3195 break; 3196 default: 3197 break; 3198 } 3199 3200 /* QREG_CC_X is not affected */ 3201 3202 tcg_gen_mov_i32(QREG_CC_N, reg); 3203 tcg_gen_mov_i32(QREG_CC_Z, reg); 3204 3205 if (left) { 3206 tcg_gen_andi_i32(QREG_CC_C, reg, 1); 3207 } else { 3208 tcg_gen_shri_i32(QREG_CC_C, reg, 31); 3209 } 3210 3211 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */ 3212 } 3213 3214 static void rotate_x_flags(TCGv reg, TCGv X, int size) 3215 { 3216 switch (size) { 3217 case 8: 3218 tcg_gen_ext8s_i32(reg, reg); 3219 break; 3220 case 16: 3221 tcg_gen_ext16s_i32(reg, reg); 3222 break; 3223 default: 3224 break; 3225 } 3226 tcg_gen_mov_i32(QREG_CC_N, reg); 3227 tcg_gen_mov_i32(QREG_CC_Z, reg); 3228 tcg_gen_mov_i32(QREG_CC_X, X); 3229 tcg_gen_mov_i32(QREG_CC_C, X); 3230 tcg_gen_movi_i32(QREG_CC_V, 0); 3231 } 3232 3233 /* Result of rotate_x() is valid if 0 <= shift <= size */ 3234 static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size) 3235 { 3236 TCGv X, shl, shr, shx, sz, zero; 3237 3238 sz = tcg_const_i32(size); 3239 3240 shr = tcg_temp_new(); 3241 shl = tcg_temp_new(); 3242 shx = tcg_temp_new(); 3243 if (left) { 3244 tcg_gen_mov_i32(shl, shift); /* shl = shift */ 3245 tcg_gen_movi_i32(shr, size + 1); 3246 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */ 3247 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */ 3248 /* shx = shx < 0 ? size : shx; */ 3249 zero = tcg_const_i32(0); 3250 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx); 3251 tcg_temp_free(zero); 3252 } else { 3253 tcg_gen_mov_i32(shr, shift); /* shr = shift */ 3254 tcg_gen_movi_i32(shl, size + 1); 3255 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */ 3256 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */ 3257 } 3258 3259 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */ 3260 3261 tcg_gen_shl_i32(shl, reg, shl); 3262 tcg_gen_shr_i32(shr, reg, shr); 3263 tcg_gen_or_i32(reg, shl, shr); 3264 tcg_temp_free(shl); 3265 tcg_temp_free(shr); 3266 tcg_gen_shl_i32(shx, QREG_CC_X, shx); 3267 tcg_gen_or_i32(reg, reg, shx); 3268 tcg_temp_free(shx); 3269 3270 /* X = (reg >> size) & 1 */ 3271 3272 X = tcg_temp_new(); 3273 tcg_gen_shr_i32(X, reg, sz); 3274 tcg_gen_andi_i32(X, X, 1); 3275 tcg_temp_free(sz); 3276 3277 return X; 3278 } 3279 3280 /* Result of rotate32_x() is valid if 0 <= shift < 33 */ 3281 static TCGv rotate32_x(TCGv reg, TCGv shift, int left) 3282 { 3283 TCGv_i64 t0, shift64; 3284 TCGv X, lo, hi, zero; 3285 3286 shift64 = tcg_temp_new_i64(); 3287 tcg_gen_extu_i32_i64(shift64, shift); 3288 3289 t0 = tcg_temp_new_i64(); 3290 3291 X = tcg_temp_new(); 3292 lo = tcg_temp_new(); 3293 hi = tcg_temp_new(); 3294 3295 if (left) { 3296 /* create [reg:X:..] */ 3297 3298 tcg_gen_shli_i32(lo, QREG_CC_X, 31); 3299 tcg_gen_concat_i32_i64(t0, lo, reg); 3300 3301 /* rotate */ 3302 3303 tcg_gen_rotl_i64(t0, t0, shift64); 3304 tcg_temp_free_i64(shift64); 3305 3306 /* result is [reg:..:reg:X] */ 3307 3308 tcg_gen_extr_i64_i32(lo, hi, t0); 3309 tcg_gen_andi_i32(X, lo, 1); 3310 3311 tcg_gen_shri_i32(lo, lo, 1); 3312 } else { 3313 /* create [..:X:reg] */ 3314 3315 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X); 3316 3317 tcg_gen_rotr_i64(t0, t0, shift64); 3318 tcg_temp_free_i64(shift64); 3319 3320 /* result is value: [X:reg:..:reg] */ 3321 3322 tcg_gen_extr_i64_i32(lo, hi, t0); 3323 3324 /* extract X */ 3325 3326 tcg_gen_shri_i32(X, hi, 31); 3327 3328 /* extract result */ 3329 3330 tcg_gen_shli_i32(hi, hi, 1); 3331 } 3332 tcg_temp_free_i64(t0); 3333 tcg_gen_or_i32(lo, lo, hi); 3334 tcg_temp_free(hi); 3335 3336 /* if shift == 0, register and X are not affected */ 3337 3338 zero = tcg_const_i32(0); 3339 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X); 3340 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo); 3341 tcg_temp_free(zero); 3342 tcg_temp_free(lo); 3343 3344 return X; 3345 } 3346 3347 DISAS_INSN(rotate_im) 3348 { 3349 TCGv shift; 3350 int tmp; 3351 int left = (insn & 0x100); 3352 3353 tmp = (insn >> 9) & 7; 3354 if (tmp == 0) { 3355 tmp = 8; 3356 } 3357 3358 shift = tcg_const_i32(tmp); 3359 if (insn & 8) { 3360 rotate(DREG(insn, 0), shift, left, 32); 3361 } else { 3362 TCGv X = rotate32_x(DREG(insn, 0), shift, left); 3363 rotate_x_flags(DREG(insn, 0), X, 32); 3364 tcg_temp_free(X); 3365 } 3366 tcg_temp_free(shift); 3367 3368 set_cc_op(s, CC_OP_FLAGS); 3369 } 3370 3371 DISAS_INSN(rotate8_im) 3372 { 3373 int left = (insn & 0x100); 3374 TCGv reg; 3375 TCGv shift; 3376 int tmp; 3377 3378 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); 3379 3380 tmp = (insn >> 9) & 7; 3381 if (tmp == 0) { 3382 tmp = 8; 3383 } 3384 3385 shift = tcg_const_i32(tmp); 3386 if (insn & 8) { 3387 rotate(reg, shift, left, 8); 3388 } else { 3389 TCGv X = rotate_x(reg, shift, left, 8); 3390 rotate_x_flags(reg, X, 8); 3391 tcg_temp_free(X); 3392 } 3393 tcg_temp_free(shift); 3394 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); 3395 set_cc_op(s, CC_OP_FLAGS); 3396 } 3397 3398 DISAS_INSN(rotate16_im) 3399 { 3400 int left = (insn & 0x100); 3401 TCGv reg; 3402 TCGv shift; 3403 int tmp; 3404 3405 reg = gen_extend(DREG(insn, 0), OS_WORD, 0); 3406 tmp = (insn >> 9) & 7; 3407 if (tmp == 0) { 3408 tmp = 8; 3409 } 3410 3411 shift = tcg_const_i32(tmp); 3412 if (insn & 8) { 3413 rotate(reg, shift, left, 16); 3414 } else { 3415 TCGv X = rotate_x(reg, shift, left, 16); 3416 rotate_x_flags(reg, X, 16); 3417 tcg_temp_free(X); 3418 } 3419 tcg_temp_free(shift); 3420 gen_partset_reg(OS_WORD, DREG(insn, 0), reg); 3421 set_cc_op(s, CC_OP_FLAGS); 3422 } 3423 3424 DISAS_INSN(rotate_reg) 3425 { 3426 TCGv reg; 3427 TCGv src; 3428 TCGv t0, t1; 3429 int left = (insn & 0x100); 3430 3431 reg = DREG(insn, 0); 3432 src = DREG(insn, 9); 3433 /* shift in [0..63] */ 3434 t0 = tcg_temp_new(); 3435 tcg_gen_andi_i32(t0, src, 63); 3436 t1 = tcg_temp_new_i32(); 3437 if (insn & 8) { 3438 tcg_gen_andi_i32(t1, src, 31); 3439 rotate(reg, t1, left, 32); 3440 /* if shift == 0, clear C */ 3441 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, 3442 t0, QREG_CC_V /* 0 */, 3443 QREG_CC_V /* 0 */, QREG_CC_C); 3444 } else { 3445 TCGv X; 3446 /* modulo 33 */ 3447 tcg_gen_movi_i32(t1, 33); 3448 tcg_gen_remu_i32(t1, t0, t1); 3449 X = rotate32_x(DREG(insn, 0), t1, left); 3450 rotate_x_flags(DREG(insn, 0), X, 32); 3451 tcg_temp_free(X); 3452 } 3453 tcg_temp_free(t1); 3454 tcg_temp_free(t0); 3455 set_cc_op(s, CC_OP_FLAGS); 3456 } 3457 3458 DISAS_INSN(rotate8_reg) 3459 { 3460 TCGv reg; 3461 TCGv src; 3462 TCGv t0, t1; 3463 int left = (insn & 0x100); 3464 3465 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); 3466 src = DREG(insn, 9); 3467 /* shift in [0..63] */ 3468 t0 = tcg_temp_new_i32(); 3469 tcg_gen_andi_i32(t0, src, 63); 3470 t1 = tcg_temp_new_i32(); 3471 if (insn & 8) { 3472 tcg_gen_andi_i32(t1, src, 7); 3473 rotate(reg, t1, left, 8); 3474 /* if shift == 0, clear C */ 3475 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, 3476 t0, QREG_CC_V /* 0 */, 3477 QREG_CC_V /* 0 */, QREG_CC_C); 3478 } else { 3479 TCGv X; 3480 /* modulo 9 */ 3481 tcg_gen_movi_i32(t1, 9); 3482 tcg_gen_remu_i32(t1, t0, t1); 3483 X = rotate_x(reg, t1, left, 8); 3484 rotate_x_flags(reg, X, 8); 3485 tcg_temp_free(X); 3486 } 3487 tcg_temp_free(t1); 3488 tcg_temp_free(t0); 3489 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); 3490 set_cc_op(s, CC_OP_FLAGS); 3491 } 3492 3493 DISAS_INSN(rotate16_reg) 3494 { 3495 TCGv reg; 3496 TCGv src; 3497 TCGv t0, t1; 3498 int left = (insn & 0x100); 3499 3500 reg = gen_extend(DREG(insn, 0), OS_WORD, 0); 3501 src = DREG(insn, 9); 3502 /* shift in [0..63] */ 3503 t0 = tcg_temp_new_i32(); 3504 tcg_gen_andi_i32(t0, src, 63); 3505 t1 = tcg_temp_new_i32(); 3506 if (insn & 8) { 3507 tcg_gen_andi_i32(t1, src, 15); 3508 rotate(reg, t1, left, 16); 3509 /* if shift == 0, clear C */ 3510 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, 3511 t0, QREG_CC_V /* 0 */, 3512 QREG_CC_V /* 0 */, QREG_CC_C); 3513 } else { 3514 TCGv X; 3515 /* modulo 17 */ 3516 tcg_gen_movi_i32(t1, 17); 3517 tcg_gen_remu_i32(t1, t0, t1); 3518 X = rotate_x(reg, t1, left, 16); 3519 rotate_x_flags(reg, X, 16); 3520 tcg_temp_free(X); 3521 } 3522 tcg_temp_free(t1); 3523 tcg_temp_free(t0); 3524 gen_partset_reg(OS_WORD, DREG(insn, 0), reg); 3525 set_cc_op(s, CC_OP_FLAGS); 3526 } 3527 3528 DISAS_INSN(rotate_mem) 3529 { 3530 TCGv src; 3531 TCGv addr; 3532 TCGv shift; 3533 int left = (insn & 0x100); 3534 3535 SRC_EA(env, src, OS_WORD, 0, &addr); 3536 3537 shift = tcg_const_i32(1); 3538 if (insn & 0x0200) { 3539 rotate(src, shift, left, 16); 3540 } else { 3541 TCGv X = rotate_x(src, shift, left, 16); 3542 rotate_x_flags(src, X, 16); 3543 tcg_temp_free(X); 3544 } 3545 tcg_temp_free(shift); 3546 DEST_EA(env, insn, OS_WORD, src, &addr); 3547 set_cc_op(s, CC_OP_FLAGS); 3548 } 3549 3550 DISAS_INSN(bfext_reg) 3551 { 3552 int ext = read_im16(env, s); 3553 int is_sign = insn & 0x200; 3554 TCGv src = DREG(insn, 0); 3555 TCGv dst = DREG(ext, 12); 3556 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1; 3557 int ofs = extract32(ext, 6, 5); /* big bit-endian */ 3558 int pos = 32 - ofs - len; /* little bit-endian */ 3559 TCGv tmp = tcg_temp_new(); 3560 TCGv shift; 3561 3562 /* In general, we're going to rotate the field so that it's at the 3563 top of the word and then right-shift by the compliment of the 3564 width to extend the field. */ 3565 if (ext & 0x20) { 3566 /* Variable width. */ 3567 if (ext & 0x800) { 3568 /* Variable offset. */ 3569 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31); 3570 tcg_gen_rotl_i32(tmp, src, tmp); 3571 } else { 3572 tcg_gen_rotli_i32(tmp, src, ofs); 3573 } 3574 3575 shift = tcg_temp_new(); 3576 tcg_gen_neg_i32(shift, DREG(ext, 0)); 3577 tcg_gen_andi_i32(shift, shift, 31); 3578 tcg_gen_sar_i32(QREG_CC_N, tmp, shift); 3579 if (is_sign) { 3580 tcg_gen_mov_i32(dst, QREG_CC_N); 3581 } else { 3582 tcg_gen_shr_i32(dst, tmp, shift); 3583 } 3584 tcg_temp_free(shift); 3585 } else { 3586 /* Immediate width. */ 3587 if (ext & 0x800) { 3588 /* Variable offset */ 3589 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31); 3590 tcg_gen_rotl_i32(tmp, src, tmp); 3591 src = tmp; 3592 pos = 32 - len; 3593 } else { 3594 /* Immediate offset. If the field doesn't wrap around the 3595 end of the word, rely on (s)extract completely. */ 3596 if (pos < 0) { 3597 tcg_gen_rotli_i32(tmp, src, ofs); 3598 src = tmp; 3599 pos = 32 - len; 3600 } 3601 } 3602 3603 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len); 3604 if (is_sign) { 3605 tcg_gen_mov_i32(dst, QREG_CC_N); 3606 } else { 3607 tcg_gen_extract_i32(dst, src, pos, len); 3608 } 3609 } 3610 3611 tcg_temp_free(tmp); 3612 set_cc_op(s, CC_OP_LOGIC); 3613 } 3614 3615 DISAS_INSN(bfext_mem) 3616 { 3617 int ext = read_im16(env, s); 3618 int is_sign = insn & 0x200; 3619 TCGv dest = DREG(ext, 12); 3620 TCGv addr, len, ofs; 3621 3622 addr = gen_lea(env, s, insn, OS_UNSIZED); 3623 if (IS_NULL_QREG(addr)) { 3624 gen_addr_fault(s); 3625 return; 3626 } 3627 3628 if (ext & 0x20) { 3629 len = DREG(ext, 0); 3630 } else { 3631 len = tcg_const_i32(extract32(ext, 0, 5)); 3632 } 3633 if (ext & 0x800) { 3634 ofs = DREG(ext, 6); 3635 } else { 3636 ofs = tcg_const_i32(extract32(ext, 6, 5)); 3637 } 3638 3639 if (is_sign) { 3640 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len); 3641 tcg_gen_mov_i32(QREG_CC_N, dest); 3642 } else { 3643 TCGv_i64 tmp = tcg_temp_new_i64(); 3644 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len); 3645 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp); 3646 tcg_temp_free_i64(tmp); 3647 } 3648 set_cc_op(s, CC_OP_LOGIC); 3649 3650 if (!(ext & 0x20)) { 3651 tcg_temp_free(len); 3652 } 3653 if (!(ext & 0x800)) { 3654 tcg_temp_free(ofs); 3655 } 3656 } 3657 3658 DISAS_INSN(bfop_reg) 3659 { 3660 int ext = read_im16(env, s); 3661 TCGv src = DREG(insn, 0); 3662 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1; 3663 int ofs = extract32(ext, 6, 5); /* big bit-endian */ 3664 TCGv mask, tofs, tlen; 3665 3666 TCGV_UNUSED(tofs); 3667 TCGV_UNUSED(tlen); 3668 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */ 3669 tofs = tcg_temp_new(); 3670 tlen = tcg_temp_new(); 3671 } 3672 3673 if ((ext & 0x820) == 0) { 3674 /* Immediate width and offset. */ 3675 uint32_t maski = 0x7fffffffu >> (len - 1); 3676 if (ofs + len <= 32) { 3677 tcg_gen_shli_i32(QREG_CC_N, src, ofs); 3678 } else { 3679 tcg_gen_rotli_i32(QREG_CC_N, src, ofs); 3680 } 3681 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski); 3682 mask = tcg_const_i32(ror32(maski, ofs)); 3683 if (!TCGV_IS_UNUSED(tofs)) { 3684 tcg_gen_movi_i32(tofs, ofs); 3685 tcg_gen_movi_i32(tlen, len); 3686 } 3687 } else { 3688 TCGv tmp = tcg_temp_new(); 3689 if (ext & 0x20) { 3690 /* Variable width */ 3691 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1); 3692 tcg_gen_andi_i32(tmp, tmp, 31); 3693 mask = tcg_const_i32(0x7fffffffu); 3694 tcg_gen_shr_i32(mask, mask, tmp); 3695 if (!TCGV_IS_UNUSED(tlen)) { 3696 tcg_gen_addi_i32(tlen, tmp, 1); 3697 } 3698 } else { 3699 /* Immediate width */ 3700 mask = tcg_const_i32(0x7fffffffu >> (len - 1)); 3701 if (!TCGV_IS_UNUSED(tlen)) { 3702 tcg_gen_movi_i32(tlen, len); 3703 } 3704 } 3705 if (ext & 0x800) { 3706 /* Variable offset */ 3707 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31); 3708 tcg_gen_rotl_i32(QREG_CC_N, src, tmp); 3709 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask); 3710 tcg_gen_rotr_i32(mask, mask, tmp); 3711 if (!TCGV_IS_UNUSED(tofs)) { 3712 tcg_gen_mov_i32(tofs, tmp); 3713 } 3714 } else { 3715 /* Immediate offset (and variable width) */ 3716 tcg_gen_rotli_i32(QREG_CC_N, src, ofs); 3717 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask); 3718 tcg_gen_rotri_i32(mask, mask, ofs); 3719 if (!TCGV_IS_UNUSED(tofs)) { 3720 tcg_gen_movi_i32(tofs, ofs); 3721 } 3722 } 3723 tcg_temp_free(tmp); 3724 } 3725 set_cc_op(s, CC_OP_LOGIC); 3726 3727 switch (insn & 0x0f00) { 3728 case 0x0a00: /* bfchg */ 3729 tcg_gen_eqv_i32(src, src, mask); 3730 break; 3731 case 0x0c00: /* bfclr */ 3732 tcg_gen_and_i32(src, src, mask); 3733 break; 3734 case 0x0d00: /* bfffo */ 3735 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen); 3736 tcg_temp_free(tlen); 3737 tcg_temp_free(tofs); 3738 break; 3739 case 0x0e00: /* bfset */ 3740 tcg_gen_orc_i32(src, src, mask); 3741 break; 3742 case 0x0800: /* bftst */ 3743 /* flags already set; no other work to do. */ 3744 break; 3745 default: 3746 g_assert_not_reached(); 3747 } 3748 tcg_temp_free(mask); 3749 } 3750 3751 DISAS_INSN(bfop_mem) 3752 { 3753 int ext = read_im16(env, s); 3754 TCGv addr, len, ofs; 3755 TCGv_i64 t64; 3756 3757 addr = gen_lea(env, s, insn, OS_UNSIZED); 3758 if (IS_NULL_QREG(addr)) { 3759 gen_addr_fault(s); 3760 return; 3761 } 3762 3763 if (ext & 0x20) { 3764 len = DREG(ext, 0); 3765 } else { 3766 len = tcg_const_i32(extract32(ext, 0, 5)); 3767 } 3768 if (ext & 0x800) { 3769 ofs = DREG(ext, 6); 3770 } else { 3771 ofs = tcg_const_i32(extract32(ext, 6, 5)); 3772 } 3773 3774 switch (insn & 0x0f00) { 3775 case 0x0a00: /* bfchg */ 3776 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len); 3777 break; 3778 case 0x0c00: /* bfclr */ 3779 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len); 3780 break; 3781 case 0x0d00: /* bfffo */ 3782 t64 = tcg_temp_new_i64(); 3783 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len); 3784 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64); 3785 tcg_temp_free_i64(t64); 3786 break; 3787 case 0x0e00: /* bfset */ 3788 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len); 3789 break; 3790 case 0x0800: /* bftst */ 3791 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len); 3792 break; 3793 default: 3794 g_assert_not_reached(); 3795 } 3796 set_cc_op(s, CC_OP_LOGIC); 3797 3798 if (!(ext & 0x20)) { 3799 tcg_temp_free(len); 3800 } 3801 if (!(ext & 0x800)) { 3802 tcg_temp_free(ofs); 3803 } 3804 } 3805 3806 DISAS_INSN(bfins_reg) 3807 { 3808 int ext = read_im16(env, s); 3809 TCGv dst = DREG(insn, 0); 3810 TCGv src = DREG(ext, 12); 3811 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1; 3812 int ofs = extract32(ext, 6, 5); /* big bit-endian */ 3813 int pos = 32 - ofs - len; /* little bit-endian */ 3814 TCGv tmp; 3815 3816 tmp = tcg_temp_new(); 3817 3818 if (ext & 0x20) { 3819 /* Variable width */ 3820 tcg_gen_neg_i32(tmp, DREG(ext, 0)); 3821 tcg_gen_andi_i32(tmp, tmp, 31); 3822 tcg_gen_shl_i32(QREG_CC_N, src, tmp); 3823 } else { 3824 /* Immediate width */ 3825 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len); 3826 } 3827 set_cc_op(s, CC_OP_LOGIC); 3828 3829 /* Immediate width and offset */ 3830 if ((ext & 0x820) == 0) { 3831 /* Check for suitability for deposit. */ 3832 if (pos >= 0) { 3833 tcg_gen_deposit_i32(dst, dst, src, pos, len); 3834 } else { 3835 uint32_t maski = -2U << (len - 1); 3836 uint32_t roti = (ofs + len) & 31; 3837 tcg_gen_andi_i32(tmp, src, ~maski); 3838 tcg_gen_rotri_i32(tmp, tmp, roti); 3839 tcg_gen_andi_i32(dst, dst, ror32(maski, roti)); 3840 tcg_gen_or_i32(dst, dst, tmp); 3841 } 3842 } else { 3843 TCGv mask = tcg_temp_new(); 3844 TCGv rot = tcg_temp_new(); 3845 3846 if (ext & 0x20) { 3847 /* Variable width */ 3848 tcg_gen_subi_i32(rot, DREG(ext, 0), 1); 3849 tcg_gen_andi_i32(rot, rot, 31); 3850 tcg_gen_movi_i32(mask, -2); 3851 tcg_gen_shl_i32(mask, mask, rot); 3852 tcg_gen_mov_i32(rot, DREG(ext, 0)); 3853 tcg_gen_andc_i32(tmp, src, mask); 3854 } else { 3855 /* Immediate width (variable offset) */ 3856 uint32_t maski = -2U << (len - 1); 3857 tcg_gen_andi_i32(tmp, src, ~maski); 3858 tcg_gen_movi_i32(mask, maski); 3859 tcg_gen_movi_i32(rot, len & 31); 3860 } 3861 if (ext & 0x800) { 3862 /* Variable offset */ 3863 tcg_gen_add_i32(rot, rot, DREG(ext, 6)); 3864 } else { 3865 /* Immediate offset (variable width) */ 3866 tcg_gen_addi_i32(rot, rot, ofs); 3867 } 3868 tcg_gen_andi_i32(rot, rot, 31); 3869 tcg_gen_rotr_i32(mask, mask, rot); 3870 tcg_gen_rotr_i32(tmp, tmp, rot); 3871 tcg_gen_and_i32(dst, dst, mask); 3872 tcg_gen_or_i32(dst, dst, tmp); 3873 3874 tcg_temp_free(rot); 3875 tcg_temp_free(mask); 3876 } 3877 tcg_temp_free(tmp); 3878 } 3879 3880 DISAS_INSN(bfins_mem) 3881 { 3882 int ext = read_im16(env, s); 3883 TCGv src = DREG(ext, 12); 3884 TCGv addr, len, ofs; 3885 3886 addr = gen_lea(env, s, insn, OS_UNSIZED); 3887 if (IS_NULL_QREG(addr)) { 3888 gen_addr_fault(s); 3889 return; 3890 } 3891 3892 if (ext & 0x20) { 3893 len = DREG(ext, 0); 3894 } else { 3895 len = tcg_const_i32(extract32(ext, 0, 5)); 3896 } 3897 if (ext & 0x800) { 3898 ofs = DREG(ext, 6); 3899 } else { 3900 ofs = tcg_const_i32(extract32(ext, 6, 5)); 3901 } 3902 3903 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len); 3904 set_cc_op(s, CC_OP_LOGIC); 3905 3906 if (!(ext & 0x20)) { 3907 tcg_temp_free(len); 3908 } 3909 if (!(ext & 0x800)) { 3910 tcg_temp_free(ofs); 3911 } 3912 } 3913 3914 DISAS_INSN(ff1) 3915 { 3916 TCGv reg; 3917 reg = DREG(insn, 0); 3918 gen_logic_cc(s, reg, OS_LONG); 3919 gen_helper_ff1(reg, reg); 3920 } 3921 3922 static TCGv gen_get_sr(DisasContext *s) 3923 { 3924 TCGv ccr; 3925 TCGv sr; 3926 3927 ccr = gen_get_ccr(s); 3928 sr = tcg_temp_new(); 3929 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); 3930 tcg_gen_or_i32(sr, sr, ccr); 3931 return sr; 3932 } 3933 3934 DISAS_INSN(strldsr) 3935 { 3936 uint16_t ext; 3937 uint32_t addr; 3938 3939 addr = s->pc - 2; 3940 ext = read_im16(env, s); 3941 if (ext != 0x46FC) { 3942 gen_exception(s, addr, EXCP_UNSUPPORTED); 3943 return; 3944 } 3945 ext = read_im16(env, s); 3946 if (IS_USER(s) || (ext & SR_S) == 0) { 3947 gen_exception(s, addr, EXCP_PRIVILEGE); 3948 return; 3949 } 3950 gen_push(s, gen_get_sr(s)); 3951 gen_set_sr_im(s, ext, 0); 3952 } 3953 3954 DISAS_INSN(move_from_sr) 3955 { 3956 TCGv sr; 3957 3958 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) { 3959 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 3960 return; 3961 } 3962 sr = gen_get_sr(s); 3963 DEST_EA(env, insn, OS_WORD, sr, NULL); 3964 } 3965 3966 DISAS_INSN(move_to_sr) 3967 { 3968 if (IS_USER(s)) { 3969 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 3970 return; 3971 } 3972 gen_set_sr(env, s, insn, 0); 3973 gen_lookup_tb(s); 3974 } 3975 3976 DISAS_INSN(move_from_usp) 3977 { 3978 if (IS_USER(s)) { 3979 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 3980 return; 3981 } 3982 tcg_gen_ld_i32(AREG(insn, 0), cpu_env, 3983 offsetof(CPUM68KState, sp[M68K_USP])); 3984 } 3985 3986 DISAS_INSN(move_to_usp) 3987 { 3988 if (IS_USER(s)) { 3989 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 3990 return; 3991 } 3992 tcg_gen_st_i32(AREG(insn, 0), cpu_env, 3993 offsetof(CPUM68KState, sp[M68K_USP])); 3994 } 3995 3996 DISAS_INSN(halt) 3997 { 3998 gen_exception(s, s->pc, EXCP_HALT_INSN); 3999 } 4000 4001 DISAS_INSN(stop) 4002 { 4003 uint16_t ext; 4004 4005 if (IS_USER(s)) { 4006 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 4007 return; 4008 } 4009 4010 ext = read_im16(env, s); 4011 4012 gen_set_sr_im(s, ext, 0); 4013 tcg_gen_movi_i32(cpu_halted, 1); 4014 gen_exception(s, s->pc, EXCP_HLT); 4015 } 4016 4017 DISAS_INSN(rte) 4018 { 4019 if (IS_USER(s)) { 4020 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 4021 return; 4022 } 4023 gen_exception(s, s->pc - 2, EXCP_RTE); 4024 } 4025 4026 DISAS_INSN(movec) 4027 { 4028 uint16_t ext; 4029 TCGv reg; 4030 4031 if (IS_USER(s)) { 4032 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 4033 return; 4034 } 4035 4036 ext = read_im16(env, s); 4037 4038 if (ext & 0x8000) { 4039 reg = AREG(ext, 12); 4040 } else { 4041 reg = DREG(ext, 12); 4042 } 4043 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); 4044 gen_lookup_tb(s); 4045 } 4046 4047 DISAS_INSN(intouch) 4048 { 4049 if (IS_USER(s)) { 4050 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 4051 return; 4052 } 4053 /* ICache fetch. Implement as no-op. */ 4054 } 4055 4056 DISAS_INSN(cpushl) 4057 { 4058 if (IS_USER(s)) { 4059 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 4060 return; 4061 } 4062 /* Cache push/invalidate. Implement as no-op. */ 4063 } 4064 4065 DISAS_INSN(wddata) 4066 { 4067 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 4068 } 4069 4070 DISAS_INSN(wdebug) 4071 { 4072 M68kCPU *cpu = m68k_env_get_cpu(env); 4073 4074 if (IS_USER(s)) { 4075 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); 4076 return; 4077 } 4078 /* TODO: Implement wdebug. */ 4079 cpu_abort(CPU(cpu), "WDEBUG not implemented"); 4080 } 4081 4082 DISAS_INSN(trap) 4083 { 4084 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); 4085 } 4086 4087 /* ??? FP exceptions are not implemented. Most exceptions are deferred until 4088 immediately before the next FP instruction is executed. */ 4089 DISAS_INSN(fpu) 4090 { 4091 uint16_t ext; 4092 int32_t offset; 4093 int opmode; 4094 TCGv_i64 src; 4095 TCGv_i64 dest; 4096 TCGv_i64 res; 4097 TCGv tmp32; 4098 int round; 4099 int set_dest; 4100 int opsize; 4101 4102 ext = read_im16(env, s); 4103 opmode = ext & 0x7f; 4104 switch ((ext >> 13) & 7) { 4105 case 0: case 2: 4106 break; 4107 case 1: 4108 goto undef; 4109 case 3: /* fmove out */ 4110 src = FREG(ext, 7); 4111 tmp32 = tcg_temp_new_i32(); 4112 /* fmove */ 4113 /* ??? TODO: Proper behavior on overflow. */ 4114 switch ((ext >> 10) & 7) { 4115 case 0: 4116 opsize = OS_LONG; 4117 gen_helper_f64_to_i32(tmp32, cpu_env, src); 4118 break; 4119 case 1: 4120 opsize = OS_SINGLE; 4121 gen_helper_f64_to_f32(tmp32, cpu_env, src); 4122 break; 4123 case 4: 4124 opsize = OS_WORD; 4125 gen_helper_f64_to_i32(tmp32, cpu_env, src); 4126 break; 4127 case 5: /* OS_DOUBLE */ 4128 tcg_gen_mov_i32(tmp32, AREG(insn, 0)); 4129 switch ((insn >> 3) & 7) { 4130 case 2: 4131 case 3: 4132 break; 4133 case 4: 4134 tcg_gen_addi_i32(tmp32, tmp32, -8); 4135 break; 4136 case 5: 4137 offset = cpu_ldsw_code(env, s->pc); 4138 s->pc += 2; 4139 tcg_gen_addi_i32(tmp32, tmp32, offset); 4140 break; 4141 default: 4142 goto undef; 4143 } 4144 gen_store64(s, tmp32, src); 4145 switch ((insn >> 3) & 7) { 4146 case 3: 4147 tcg_gen_addi_i32(tmp32, tmp32, 8); 4148 tcg_gen_mov_i32(AREG(insn, 0), tmp32); 4149 break; 4150 case 4: 4151 tcg_gen_mov_i32(AREG(insn, 0), tmp32); 4152 break; 4153 } 4154 tcg_temp_free_i32(tmp32); 4155 return; 4156 case 6: 4157 opsize = OS_BYTE; 4158 gen_helper_f64_to_i32(tmp32, cpu_env, src); 4159 break; 4160 default: 4161 goto undef; 4162 } 4163 DEST_EA(env, insn, opsize, tmp32, NULL); 4164 tcg_temp_free_i32(tmp32); 4165 return; 4166 case 4: /* fmove to control register. */ 4167 switch ((ext >> 10) & 7) { 4168 case 4: /* FPCR */ 4169 /* Not implemented. Ignore writes. */ 4170 break; 4171 case 1: /* FPIAR */ 4172 case 2: /* FPSR */ 4173 default: 4174 cpu_abort(NULL, "Unimplemented: fmove to control %d", 4175 (ext >> 10) & 7); 4176 } 4177 break; 4178 case 5: /* fmove from control register. */ 4179 switch ((ext >> 10) & 7) { 4180 case 4: /* FPCR */ 4181 /* Not implemented. Always return zero. */ 4182 tmp32 = tcg_const_i32(0); 4183 break; 4184 case 1: /* FPIAR */ 4185 case 2: /* FPSR */ 4186 default: 4187 cpu_abort(NULL, "Unimplemented: fmove from control %d", 4188 (ext >> 10) & 7); 4189 goto undef; 4190 } 4191 DEST_EA(env, insn, OS_LONG, tmp32, NULL); 4192 break; 4193 case 6: /* fmovem */ 4194 case 7: 4195 { 4196 TCGv addr; 4197 uint16_t mask; 4198 int i; 4199 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) 4200 goto undef; 4201 tmp32 = gen_lea(env, s, insn, OS_LONG); 4202 if (IS_NULL_QREG(tmp32)) { 4203 gen_addr_fault(s); 4204 return; 4205 } 4206 addr = tcg_temp_new_i32(); 4207 tcg_gen_mov_i32(addr, tmp32); 4208 mask = 0x80; 4209 for (i = 0; i < 8; i++) { 4210 if (ext & mask) { 4211 dest = FREG(i, 0); 4212 if (ext & (1 << 13)) { 4213 /* store */ 4214 tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); 4215 } else { 4216 /* load */ 4217 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); 4218 } 4219 if (ext & (mask - 1)) 4220 tcg_gen_addi_i32(addr, addr, 8); 4221 } 4222 mask >>= 1; 4223 } 4224 tcg_temp_free_i32(addr); 4225 } 4226 return; 4227 } 4228 if (ext & (1 << 14)) { 4229 /* Source effective address. */ 4230 switch ((ext >> 10) & 7) { 4231 case 0: opsize = OS_LONG; break; 4232 case 1: opsize = OS_SINGLE; break; 4233 case 4: opsize = OS_WORD; break; 4234 case 5: opsize = OS_DOUBLE; break; 4235 case 6: opsize = OS_BYTE; break; 4236 default: 4237 goto undef; 4238 } 4239 if (opsize == OS_DOUBLE) { 4240 tmp32 = tcg_temp_new_i32(); 4241 tcg_gen_mov_i32(tmp32, AREG(insn, 0)); 4242 switch ((insn >> 3) & 7) { 4243 case 2: 4244 case 3: 4245 break; 4246 case 4: 4247 tcg_gen_addi_i32(tmp32, tmp32, -8); 4248 break; 4249 case 5: 4250 offset = cpu_ldsw_code(env, s->pc); 4251 s->pc += 2; 4252 tcg_gen_addi_i32(tmp32, tmp32, offset); 4253 break; 4254 case 7: 4255 offset = cpu_ldsw_code(env, s->pc); 4256 offset += s->pc - 2; 4257 s->pc += 2; 4258 tcg_gen_addi_i32(tmp32, tmp32, offset); 4259 break; 4260 default: 4261 goto undef; 4262 } 4263 src = gen_load64(s, tmp32); 4264 switch ((insn >> 3) & 7) { 4265 case 3: 4266 tcg_gen_addi_i32(tmp32, tmp32, 8); 4267 tcg_gen_mov_i32(AREG(insn, 0), tmp32); 4268 break; 4269 case 4: 4270 tcg_gen_mov_i32(AREG(insn, 0), tmp32); 4271 break; 4272 } 4273 tcg_temp_free_i32(tmp32); 4274 } else { 4275 SRC_EA(env, tmp32, opsize, 1, NULL); 4276 src = tcg_temp_new_i64(); 4277 switch (opsize) { 4278 case OS_LONG: 4279 case OS_WORD: 4280 case OS_BYTE: 4281 gen_helper_i32_to_f64(src, cpu_env, tmp32); 4282 break; 4283 case OS_SINGLE: 4284 gen_helper_f32_to_f64(src, cpu_env, tmp32); 4285 break; 4286 } 4287 } 4288 } else { 4289 /* Source register. */ 4290 src = FREG(ext, 10); 4291 } 4292 dest = FREG(ext, 7); 4293 res = tcg_temp_new_i64(); 4294 if (opmode != 0x3a) 4295 tcg_gen_mov_f64(res, dest); 4296 round = 1; 4297 set_dest = 1; 4298 switch (opmode) { 4299 case 0: case 0x40: case 0x44: /* fmove */ 4300 tcg_gen_mov_f64(res, src); 4301 break; 4302 case 1: /* fint */ 4303 gen_helper_iround_f64(res, cpu_env, src); 4304 round = 0; 4305 break; 4306 case 3: /* fintrz */ 4307 gen_helper_itrunc_f64(res, cpu_env, src); 4308 round = 0; 4309 break; 4310 case 4: case 0x41: case 0x45: /* fsqrt */ 4311 gen_helper_sqrt_f64(res, cpu_env, src); 4312 break; 4313 case 0x18: case 0x58: case 0x5c: /* fabs */ 4314 gen_helper_abs_f64(res, src); 4315 break; 4316 case 0x1a: case 0x5a: case 0x5e: /* fneg */ 4317 gen_helper_chs_f64(res, src); 4318 break; 4319 case 0x20: case 0x60: case 0x64: /* fdiv */ 4320 gen_helper_div_f64(res, cpu_env, res, src); 4321 break; 4322 case 0x22: case 0x62: case 0x66: /* fadd */ 4323 gen_helper_add_f64(res, cpu_env, res, src); 4324 break; 4325 case 0x23: case 0x63: case 0x67: /* fmul */ 4326 gen_helper_mul_f64(res, cpu_env, res, src); 4327 break; 4328 case 0x28: case 0x68: case 0x6c: /* fsub */ 4329 gen_helper_sub_f64(res, cpu_env, res, src); 4330 break; 4331 case 0x38: /* fcmp */ 4332 gen_helper_sub_cmp_f64(res, cpu_env, res, src); 4333 set_dest = 0; 4334 round = 0; 4335 break; 4336 case 0x3a: /* ftst */ 4337 tcg_gen_mov_f64(res, src); 4338 set_dest = 0; 4339 round = 0; 4340 break; 4341 default: 4342 goto undef; 4343 } 4344 if (ext & (1 << 14)) { 4345 tcg_temp_free_i64(src); 4346 } 4347 if (round) { 4348 if (opmode & 0x40) { 4349 if ((opmode & 0x4) != 0) 4350 round = 0; 4351 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { 4352 round = 0; 4353 } 4354 } 4355 if (round) { 4356 TCGv tmp = tcg_temp_new_i32(); 4357 gen_helper_f64_to_f32(tmp, cpu_env, res); 4358 gen_helper_f32_to_f64(res, cpu_env, tmp); 4359 tcg_temp_free_i32(tmp); 4360 } 4361 tcg_gen_mov_f64(QREG_FP_RESULT, res); 4362 if (set_dest) { 4363 tcg_gen_mov_f64(dest, res); 4364 } 4365 tcg_temp_free_i64(res); 4366 return; 4367 undef: 4368 /* FIXME: Is this right for offset addressing modes? */ 4369 s->pc -= 2; 4370 disas_undef_fpu(env, s, insn); 4371 } 4372 4373 DISAS_INSN(fbcc) 4374 { 4375 uint32_t offset; 4376 uint32_t addr; 4377 TCGv flag; 4378 TCGLabel *l1; 4379 4380 addr = s->pc; 4381 offset = cpu_ldsw_code(env, s->pc); 4382 s->pc += 2; 4383 if (insn & (1 << 6)) { 4384 offset = (offset << 16) | read_im16(env, s); 4385 } 4386 4387 l1 = gen_new_label(); 4388 /* TODO: Raise BSUN exception. */ 4389 flag = tcg_temp_new(); 4390 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); 4391 /* Jump to l1 if condition is true. */ 4392 switch (insn & 0xf) { 4393 case 0: /* f */ 4394 break; 4395 case 1: /* eq (=0) */ 4396 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); 4397 break; 4398 case 2: /* ogt (=1) */ 4399 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); 4400 break; 4401 case 3: /* oge (=0 or =1) */ 4402 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); 4403 break; 4404 case 4: /* olt (=-1) */ 4405 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); 4406 break; 4407 case 5: /* ole (=-1 or =0) */ 4408 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); 4409 break; 4410 case 6: /* ogl (=-1 or =1) */ 4411 tcg_gen_andi_i32(flag, flag, 1); 4412 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); 4413 break; 4414 case 7: /* or (=2) */ 4415 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); 4416 break; 4417 case 8: /* un (<2) */ 4418 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); 4419 break; 4420 case 9: /* ueq (=0 or =2) */ 4421 tcg_gen_andi_i32(flag, flag, 1); 4422 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); 4423 break; 4424 case 10: /* ugt (>0) */ 4425 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); 4426 break; 4427 case 11: /* uge (>=0) */ 4428 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); 4429 break; 4430 case 12: /* ult (=-1 or =2) */ 4431 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); 4432 break; 4433 case 13: /* ule (!=1) */ 4434 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); 4435 break; 4436 case 14: /* ne (!=0) */ 4437 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); 4438 break; 4439 case 15: /* t */ 4440 tcg_gen_br(l1); 4441 break; 4442 } 4443 gen_jmp_tb(s, 0, s->pc); 4444 gen_set_label(l1); 4445 gen_jmp_tb(s, 1, addr + offset); 4446 } 4447 4448 DISAS_INSN(frestore) 4449 { 4450 M68kCPU *cpu = m68k_env_get_cpu(env); 4451 4452 /* TODO: Implement frestore. */ 4453 cpu_abort(CPU(cpu), "FRESTORE not implemented"); 4454 } 4455 4456 DISAS_INSN(fsave) 4457 { 4458 M68kCPU *cpu = m68k_env_get_cpu(env); 4459 4460 /* TODO: Implement fsave. */ 4461 cpu_abort(CPU(cpu), "FSAVE not implemented"); 4462 } 4463 4464 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) 4465 { 4466 TCGv tmp = tcg_temp_new(); 4467 if (s->env->macsr & MACSR_FI) { 4468 if (upper) 4469 tcg_gen_andi_i32(tmp, val, 0xffff0000); 4470 else 4471 tcg_gen_shli_i32(tmp, val, 16); 4472 } else if (s->env->macsr & MACSR_SU) { 4473 if (upper) 4474 tcg_gen_sari_i32(tmp, val, 16); 4475 else 4476 tcg_gen_ext16s_i32(tmp, val); 4477 } else { 4478 if (upper) 4479 tcg_gen_shri_i32(tmp, val, 16); 4480 else 4481 tcg_gen_ext16u_i32(tmp, val); 4482 } 4483 return tmp; 4484 } 4485 4486 static void gen_mac_clear_flags(void) 4487 { 4488 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, 4489 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); 4490 } 4491 4492 DISAS_INSN(mac) 4493 { 4494 TCGv rx; 4495 TCGv ry; 4496 uint16_t ext; 4497 int acc; 4498 TCGv tmp; 4499 TCGv addr; 4500 TCGv loadval; 4501 int dual; 4502 TCGv saved_flags; 4503 4504 if (!s->done_mac) { 4505 s->mactmp = tcg_temp_new_i64(); 4506 s->done_mac = 1; 4507 } 4508 4509 ext = read_im16(env, s); 4510 4511 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); 4512 dual = ((insn & 0x30) != 0 && (ext & 3) != 0); 4513 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { 4514 disas_undef(env, s, insn); 4515 return; 4516 } 4517 if (insn & 0x30) { 4518 /* MAC with load. */ 4519 tmp = gen_lea(env, s, insn, OS_LONG); 4520 addr = tcg_temp_new(); 4521 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); 4522 /* Load the value now to ensure correct exception behavior. 4523 Perform writeback after reading the MAC inputs. */ 4524 loadval = gen_load(s, OS_LONG, addr, 0); 4525 4526 acc ^= 1; 4527 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); 4528 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); 4529 } else { 4530 loadval = addr = NULL_QREG; 4531 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); 4532 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); 4533 } 4534 4535 gen_mac_clear_flags(); 4536 #if 0 4537 l1 = -1; 4538 /* Disabled because conditional branches clobber temporary vars. */ 4539 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { 4540 /* Skip the multiply if we know we will ignore it. */ 4541 l1 = gen_new_label(); 4542 tmp = tcg_temp_new(); 4543 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); 4544 gen_op_jmp_nz32(tmp, l1); 4545 } 4546 #endif 4547 4548 if ((ext & 0x0800) == 0) { 4549 /* Word. */ 4550 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); 4551 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); 4552 } 4553 if (s->env->macsr & MACSR_FI) { 4554 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); 4555 } else { 4556 if (s->env->macsr & MACSR_SU) 4557 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); 4558 else 4559 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); 4560 switch ((ext >> 9) & 3) { 4561 case 1: 4562 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); 4563 break; 4564 case 3: 4565 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); 4566 break; 4567 } 4568 } 4569 4570 if (dual) { 4571 /* Save the overflow flag from the multiply. */ 4572 saved_flags = tcg_temp_new(); 4573 tcg_gen_mov_i32(saved_flags, QREG_MACSR); 4574 } else { 4575 saved_flags = NULL_QREG; 4576 } 4577 4578 #if 0 4579 /* Disabled because conditional branches clobber temporary vars. */ 4580 if ((s->env->macsr & MACSR_OMC) != 0 && dual) { 4581 /* Skip the accumulate if the value is already saturated. */ 4582 l1 = gen_new_label(); 4583 tmp = tcg_temp_new(); 4584 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); 4585 gen_op_jmp_nz32(tmp, l1); 4586 } 4587 #endif 4588 4589 if (insn & 0x100) 4590 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); 4591 else 4592 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); 4593 4594 if (s->env->macsr & MACSR_FI) 4595 gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); 4596 else if (s->env->macsr & MACSR_SU) 4597 gen_helper_macsats(cpu_env, tcg_const_i32(acc)); 4598 else 4599 gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); 4600 4601 #if 0 4602 /* Disabled because conditional branches clobber temporary vars. */ 4603 if (l1 != -1) 4604 gen_set_label(l1); 4605 #endif 4606 4607 if (dual) { 4608 /* Dual accumulate variant. */ 4609 acc = (ext >> 2) & 3; 4610 /* Restore the overflow flag from the multiplier. */ 4611 tcg_gen_mov_i32(QREG_MACSR, saved_flags); 4612 #if 0 4613 /* Disabled because conditional branches clobber temporary vars. */ 4614 if ((s->env->macsr & MACSR_OMC) != 0) { 4615 /* Skip the accumulate if the value is already saturated. */ 4616 l1 = gen_new_label(); 4617 tmp = tcg_temp_new(); 4618 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); 4619 gen_op_jmp_nz32(tmp, l1); 4620 } 4621 #endif 4622 if (ext & 2) 4623 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); 4624 else 4625 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); 4626 if (s->env->macsr & MACSR_FI) 4627 gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); 4628 else if (s->env->macsr & MACSR_SU) 4629 gen_helper_macsats(cpu_env, tcg_const_i32(acc)); 4630 else 4631 gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); 4632 #if 0 4633 /* Disabled because conditional branches clobber temporary vars. */ 4634 if (l1 != -1) 4635 gen_set_label(l1); 4636 #endif 4637 } 4638 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); 4639 4640 if (insn & 0x30) { 4641 TCGv rw; 4642 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); 4643 tcg_gen_mov_i32(rw, loadval); 4644 /* FIXME: Should address writeback happen with the masked or 4645 unmasked value? */ 4646 switch ((insn >> 3) & 7) { 4647 case 3: /* Post-increment. */ 4648 tcg_gen_addi_i32(AREG(insn, 0), addr, 4); 4649 break; 4650 case 4: /* Pre-decrement. */ 4651 tcg_gen_mov_i32(AREG(insn, 0), addr); 4652 } 4653 } 4654 } 4655 4656 DISAS_INSN(from_mac) 4657 { 4658 TCGv rx; 4659 TCGv_i64 acc; 4660 int accnum; 4661 4662 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); 4663 accnum = (insn >> 9) & 3; 4664 acc = MACREG(accnum); 4665 if (s->env->macsr & MACSR_FI) { 4666 gen_helper_get_macf(rx, cpu_env, acc); 4667 } else if ((s->env->macsr & MACSR_OMC) == 0) { 4668 tcg_gen_extrl_i64_i32(rx, acc); 4669 } else if (s->env->macsr & MACSR_SU) { 4670 gen_helper_get_macs(rx, acc); 4671 } else { 4672 gen_helper_get_macu(rx, acc); 4673 } 4674 if (insn & 0x40) { 4675 tcg_gen_movi_i64(acc, 0); 4676 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); 4677 } 4678 } 4679 4680 DISAS_INSN(move_mac) 4681 { 4682 /* FIXME: This can be done without a helper. */ 4683 int src; 4684 TCGv dest; 4685 src = insn & 3; 4686 dest = tcg_const_i32((insn >> 9) & 3); 4687 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); 4688 gen_mac_clear_flags(); 4689 gen_helper_mac_set_flags(cpu_env, dest); 4690 } 4691 4692 DISAS_INSN(from_macsr) 4693 { 4694 TCGv reg; 4695 4696 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); 4697 tcg_gen_mov_i32(reg, QREG_MACSR); 4698 } 4699 4700 DISAS_INSN(from_mask) 4701 { 4702 TCGv reg; 4703 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); 4704 tcg_gen_mov_i32(reg, QREG_MAC_MASK); 4705 } 4706 4707 DISAS_INSN(from_mext) 4708 { 4709 TCGv reg; 4710 TCGv acc; 4711 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); 4712 acc = tcg_const_i32((insn & 0x400) ? 2 : 0); 4713 if (s->env->macsr & MACSR_FI) 4714 gen_helper_get_mac_extf(reg, cpu_env, acc); 4715 else 4716 gen_helper_get_mac_exti(reg, cpu_env, acc); 4717 } 4718 4719 DISAS_INSN(macsr_to_ccr) 4720 { 4721 TCGv tmp = tcg_temp_new(); 4722 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); 4723 gen_helper_set_sr(cpu_env, tmp); 4724 tcg_temp_free(tmp); 4725 set_cc_op(s, CC_OP_FLAGS); 4726 } 4727 4728 DISAS_INSN(to_mac) 4729 { 4730 TCGv_i64 acc; 4731 TCGv val; 4732 int accnum; 4733 accnum = (insn >> 9) & 3; 4734 acc = MACREG(accnum); 4735 SRC_EA(env, val, OS_LONG, 0, NULL); 4736 if (s->env->macsr & MACSR_FI) { 4737 tcg_gen_ext_i32_i64(acc, val); 4738 tcg_gen_shli_i64(acc, acc, 8); 4739 } else if (s->env->macsr & MACSR_SU) { 4740 tcg_gen_ext_i32_i64(acc, val); 4741 } else { 4742 tcg_gen_extu_i32_i64(acc, val); 4743 } 4744 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); 4745 gen_mac_clear_flags(); 4746 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); 4747 } 4748 4749 DISAS_INSN(to_macsr) 4750 { 4751 TCGv val; 4752 SRC_EA(env, val, OS_LONG, 0, NULL); 4753 gen_helper_set_macsr(cpu_env, val); 4754 gen_lookup_tb(s); 4755 } 4756 4757 DISAS_INSN(to_mask) 4758 { 4759 TCGv val; 4760 SRC_EA(env, val, OS_LONG, 0, NULL); 4761 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); 4762 } 4763 4764 DISAS_INSN(to_mext) 4765 { 4766 TCGv val; 4767 TCGv acc; 4768 SRC_EA(env, val, OS_LONG, 0, NULL); 4769 acc = tcg_const_i32((insn & 0x400) ? 2 : 0); 4770 if (s->env->macsr & MACSR_FI) 4771 gen_helper_set_mac_extf(cpu_env, val, acc); 4772 else if (s->env->macsr & MACSR_SU) 4773 gen_helper_set_mac_exts(cpu_env, val, acc); 4774 else 4775 gen_helper_set_mac_extu(cpu_env, val, acc); 4776 } 4777 4778 static disas_proc opcode_table[65536]; 4779 4780 static void 4781 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) 4782 { 4783 int i; 4784 int from; 4785 int to; 4786 4787 /* Sanity check. All set bits must be included in the mask. */ 4788 if (opcode & ~mask) { 4789 fprintf(stderr, 4790 "qemu internal error: bogus opcode definition %04x/%04x\n", 4791 opcode, mask); 4792 abort(); 4793 } 4794 /* This could probably be cleverer. For now just optimize the case where 4795 the top bits are known. */ 4796 /* Find the first zero bit in the mask. */ 4797 i = 0x8000; 4798 while ((i & mask) != 0) 4799 i >>= 1; 4800 /* Iterate over all combinations of this and lower bits. */ 4801 if (i == 0) 4802 i = 1; 4803 else 4804 i <<= 1; 4805 from = opcode & ~(i - 1); 4806 to = from + i; 4807 for (i = from; i < to; i++) { 4808 if ((i & mask) == opcode) 4809 opcode_table[i] = proc; 4810 } 4811 } 4812 4813 /* Register m68k opcode handlers. Order is important. 4814 Later insn override earlier ones. */ 4815 void register_m68k_insns (CPUM68KState *env) 4816 { 4817 /* Build the opcode table only once to avoid 4818 multithreading issues. */ 4819 if (opcode_table[0] != NULL) { 4820 return; 4821 } 4822 4823 /* use BASE() for instruction available 4824 * for CF_ISA_A and M68000. 4825 */ 4826 #define BASE(name, opcode, mask) \ 4827 register_opcode(disas_##name, 0x##opcode, 0x##mask) 4828 #define INSN(name, opcode, mask, feature) do { \ 4829 if (m68k_feature(env, M68K_FEATURE_##feature)) \ 4830 BASE(name, opcode, mask); \ 4831 } while(0) 4832 BASE(undef, 0000, 0000); 4833 INSN(arith_im, 0080, fff8, CF_ISA_A); 4834 INSN(arith_im, 0000, ff00, M68000); 4835 INSN(undef, 00c0, ffc0, M68000); 4836 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); 4837 BASE(bitop_reg, 0100, f1c0); 4838 BASE(bitop_reg, 0140, f1c0); 4839 BASE(bitop_reg, 0180, f1c0); 4840 BASE(bitop_reg, 01c0, f1c0); 4841 INSN(arith_im, 0280, fff8, CF_ISA_A); 4842 INSN(arith_im, 0200, ff00, M68000); 4843 INSN(undef, 02c0, ffc0, M68000); 4844 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); 4845 INSN(arith_im, 0480, fff8, CF_ISA_A); 4846 INSN(arith_im, 0400, ff00, M68000); 4847 INSN(undef, 04c0, ffc0, M68000); 4848 INSN(arith_im, 0600, ff00, M68000); 4849 INSN(undef, 06c0, ffc0, M68000); 4850 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); 4851 INSN(arith_im, 0680, fff8, CF_ISA_A); 4852 INSN(arith_im, 0c00, ff38, CF_ISA_A); 4853 INSN(arith_im, 0c00, ff00, M68000); 4854 BASE(bitop_im, 0800, ffc0); 4855 BASE(bitop_im, 0840, ffc0); 4856 BASE(bitop_im, 0880, ffc0); 4857 BASE(bitop_im, 08c0, ffc0); 4858 INSN(arith_im, 0a80, fff8, CF_ISA_A); 4859 INSN(arith_im, 0a00, ff00, M68000); 4860 INSN(cas, 0ac0, ffc0, CAS); 4861 INSN(cas, 0cc0, ffc0, CAS); 4862 INSN(cas, 0ec0, ffc0, CAS); 4863 INSN(cas2w, 0cfc, ffff, CAS); 4864 INSN(cas2l, 0efc, ffff, CAS); 4865 BASE(move, 1000, f000); 4866 BASE(move, 2000, f000); 4867 BASE(move, 3000, f000); 4868 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); 4869 INSN(negx, 4080, fff8, CF_ISA_A); 4870 INSN(negx, 4000, ff00, M68000); 4871 INSN(undef, 40c0, ffc0, M68000); 4872 INSN(move_from_sr, 40c0, fff8, CF_ISA_A); 4873 INSN(move_from_sr, 40c0, ffc0, M68000); 4874 BASE(lea, 41c0, f1c0); 4875 BASE(clr, 4200, ff00); 4876 BASE(undef, 42c0, ffc0); 4877 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); 4878 INSN(move_from_ccr, 42c0, ffc0, M68000); 4879 INSN(neg, 4480, fff8, CF_ISA_A); 4880 INSN(neg, 4400, ff00, M68000); 4881 INSN(undef, 44c0, ffc0, M68000); 4882 BASE(move_to_ccr, 44c0, ffc0); 4883 INSN(not, 4680, fff8, CF_ISA_A); 4884 INSN(not, 4600, ff00, M68000); 4885 INSN(undef, 46c0, ffc0, M68000); 4886 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); 4887 INSN(nbcd, 4800, ffc0, M68000); 4888 INSN(linkl, 4808, fff8, M68000); 4889 BASE(pea, 4840, ffc0); 4890 BASE(swap, 4840, fff8); 4891 INSN(bkpt, 4848, fff8, BKPT); 4892 INSN(movem, 48d0, fbf8, CF_ISA_A); 4893 INSN(movem, 48e8, fbf8, CF_ISA_A); 4894 INSN(movem, 4880, fb80, M68000); 4895 BASE(ext, 4880, fff8); 4896 BASE(ext, 48c0, fff8); 4897 BASE(ext, 49c0, fff8); 4898 BASE(tst, 4a00, ff00); 4899 INSN(tas, 4ac0, ffc0, CF_ISA_B); 4900 INSN(tas, 4ac0, ffc0, M68000); 4901 INSN(halt, 4ac8, ffff, CF_ISA_A); 4902 INSN(pulse, 4acc, ffff, CF_ISA_A); 4903 BASE(illegal, 4afc, ffff); 4904 INSN(mull, 4c00, ffc0, CF_ISA_A); 4905 INSN(mull, 4c00, ffc0, LONG_MULDIV); 4906 INSN(divl, 4c40, ffc0, CF_ISA_A); 4907 INSN(divl, 4c40, ffc0, LONG_MULDIV); 4908 INSN(sats, 4c80, fff8, CF_ISA_B); 4909 BASE(trap, 4e40, fff0); 4910 BASE(link, 4e50, fff8); 4911 BASE(unlk, 4e58, fff8); 4912 INSN(move_to_usp, 4e60, fff8, USP); 4913 INSN(move_from_usp, 4e68, fff8, USP); 4914 BASE(nop, 4e71, ffff); 4915 BASE(stop, 4e72, ffff); 4916 BASE(rte, 4e73, ffff); 4917 INSN(rtd, 4e74, ffff, RTD); 4918 BASE(rts, 4e75, ffff); 4919 INSN(movec, 4e7b, ffff, CF_ISA_A); 4920 BASE(jump, 4e80, ffc0); 4921 BASE(jump, 4ec0, ffc0); 4922 INSN(addsubq, 5000, f080, M68000); 4923 BASE(addsubq, 5080, f0c0); 4924 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ 4925 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */ 4926 INSN(dbcc, 50c8, f0f8, M68000); 4927 INSN(tpf, 51f8, fff8, CF_ISA_A); 4928 4929 /* Branch instructions. */ 4930 BASE(branch, 6000, f000); 4931 /* Disable long branch instructions, then add back the ones we want. */ 4932 BASE(undef, 60ff, f0ff); /* All long branches. */ 4933 INSN(branch, 60ff, f0ff, CF_ISA_B); 4934 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ 4935 INSN(branch, 60ff, ffff, BRAL); 4936 INSN(branch, 60ff, f0ff, BCCL); 4937 4938 BASE(moveq, 7000, f100); 4939 INSN(mvzs, 7100, f100, CF_ISA_B); 4940 BASE(or, 8000, f000); 4941 BASE(divw, 80c0, f0c0); 4942 INSN(sbcd_reg, 8100, f1f8, M68000); 4943 INSN(sbcd_mem, 8108, f1f8, M68000); 4944 BASE(addsub, 9000, f000); 4945 INSN(undef, 90c0, f0c0, CF_ISA_A); 4946 INSN(subx_reg, 9180, f1f8, CF_ISA_A); 4947 INSN(subx_reg, 9100, f138, M68000); 4948 INSN(subx_mem, 9108, f138, M68000); 4949 INSN(suba, 91c0, f1c0, CF_ISA_A); 4950 INSN(suba, 90c0, f0c0, M68000); 4951 4952 BASE(undef_mac, a000, f000); 4953 INSN(mac, a000, f100, CF_EMAC); 4954 INSN(from_mac, a180, f9b0, CF_EMAC); 4955 INSN(move_mac, a110, f9fc, CF_EMAC); 4956 INSN(from_macsr,a980, f9f0, CF_EMAC); 4957 INSN(from_mask, ad80, fff0, CF_EMAC); 4958 INSN(from_mext, ab80, fbf0, CF_EMAC); 4959 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); 4960 INSN(to_mac, a100, f9c0, CF_EMAC); 4961 INSN(to_macsr, a900, ffc0, CF_EMAC); 4962 INSN(to_mext, ab00, fbc0, CF_EMAC); 4963 INSN(to_mask, ad00, ffc0, CF_EMAC); 4964 4965 INSN(mov3q, a140, f1c0, CF_ISA_B); 4966 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ 4967 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ 4968 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ 4969 INSN(cmp, b080, f1c0, CF_ISA_A); 4970 INSN(cmpa, b1c0, f1c0, CF_ISA_A); 4971 INSN(cmp, b000, f100, M68000); 4972 INSN(eor, b100, f100, M68000); 4973 INSN(cmpm, b108, f138, M68000); 4974 INSN(cmpa, b0c0, f0c0, M68000); 4975 INSN(eor, b180, f1c0, CF_ISA_A); 4976 BASE(and, c000, f000); 4977 INSN(exg_dd, c140, f1f8, M68000); 4978 INSN(exg_aa, c148, f1f8, M68000); 4979 INSN(exg_da, c188, f1f8, M68000); 4980 BASE(mulw, c0c0, f0c0); 4981 INSN(abcd_reg, c100, f1f8, M68000); 4982 INSN(abcd_mem, c108, f1f8, M68000); 4983 BASE(addsub, d000, f000); 4984 INSN(undef, d0c0, f0c0, CF_ISA_A); 4985 INSN(addx_reg, d180, f1f8, CF_ISA_A); 4986 INSN(addx_reg, d100, f138, M68000); 4987 INSN(addx_mem, d108, f138, M68000); 4988 INSN(adda, d1c0, f1c0, CF_ISA_A); 4989 INSN(adda, d0c0, f0c0, M68000); 4990 INSN(shift_im, e080, f0f0, CF_ISA_A); 4991 INSN(shift_reg, e0a0, f0f0, CF_ISA_A); 4992 INSN(shift8_im, e000, f0f0, M68000); 4993 INSN(shift16_im, e040, f0f0, M68000); 4994 INSN(shift_im, e080, f0f0, M68000); 4995 INSN(shift8_reg, e020, f0f0, M68000); 4996 INSN(shift16_reg, e060, f0f0, M68000); 4997 INSN(shift_reg, e0a0, f0f0, M68000); 4998 INSN(shift_mem, e0c0, fcc0, M68000); 4999 INSN(rotate_im, e090, f0f0, M68000); 5000 INSN(rotate8_im, e010, f0f0, M68000); 5001 INSN(rotate16_im, e050, f0f0, M68000); 5002 INSN(rotate_reg, e0b0, f0f0, M68000); 5003 INSN(rotate8_reg, e030, f0f0, M68000); 5004 INSN(rotate16_reg, e070, f0f0, M68000); 5005 INSN(rotate_mem, e4c0, fcc0, M68000); 5006 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */ 5007 INSN(bfext_reg, e9c0, fdf8, BITFIELD); 5008 INSN(bfins_mem, efc0, ffc0, BITFIELD); 5009 INSN(bfins_reg, efc0, fff8, BITFIELD); 5010 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */ 5011 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */ 5012 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */ 5013 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */ 5014 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */ 5015 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */ 5016 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */ 5017 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */ 5018 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */ 5019 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */ 5020 INSN(undef_fpu, f000, f000, CF_ISA_A); 5021 INSN(fpu, f200, ffc0, CF_FPU); 5022 INSN(fbcc, f280, ffc0, CF_FPU); 5023 INSN(frestore, f340, ffc0, CF_FPU); 5024 INSN(fsave, f340, ffc0, CF_FPU); 5025 INSN(intouch, f340, ffc0, CF_ISA_A); 5026 INSN(cpushl, f428, ff38, CF_ISA_A); 5027 INSN(wddata, fb00, ff00, CF_ISA_A); 5028 INSN(wdebug, fbc0, ffc0, CF_ISA_A); 5029 #undef INSN 5030 } 5031 5032 /* ??? Some of this implementation is not exception safe. We should always 5033 write back the result to memory before setting the condition codes. */ 5034 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) 5035 { 5036 uint16_t insn = read_im16(env, s); 5037 opcode_table[insn](env, s, insn); 5038 do_writebacks(s); 5039 } 5040 5041 /* generate intermediate code for basic block 'tb'. */ 5042 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) 5043 { 5044 M68kCPU *cpu = m68k_env_get_cpu(env); 5045 CPUState *cs = CPU(cpu); 5046 DisasContext dc1, *dc = &dc1; 5047 target_ulong pc_start; 5048 int pc_offset; 5049 int num_insns; 5050 int max_insns; 5051 5052 /* generate intermediate code */ 5053 pc_start = tb->pc; 5054 5055 dc->tb = tb; 5056 5057 dc->env = env; 5058 dc->is_jmp = DISAS_NEXT; 5059 dc->pc = pc_start; 5060 dc->cc_op = CC_OP_DYNAMIC; 5061 dc->cc_op_synced = 1; 5062 dc->singlestep_enabled = cs->singlestep_enabled; 5063 dc->fpcr = env->fpcr; 5064 dc->user = (env->sr & SR_S) == 0; 5065 dc->done_mac = 0; 5066 dc->writeback_mask = 0; 5067 num_insns = 0; 5068 max_insns = tb->cflags & CF_COUNT_MASK; 5069 if (max_insns == 0) { 5070 max_insns = CF_COUNT_MASK; 5071 } 5072 if (max_insns > TCG_MAX_INSNS) { 5073 max_insns = TCG_MAX_INSNS; 5074 } 5075 5076 gen_tb_start(tb); 5077 do { 5078 pc_offset = dc->pc - pc_start; 5079 gen_throws_exception = NULL; 5080 tcg_gen_insn_start(dc->pc, dc->cc_op); 5081 num_insns++; 5082 5083 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { 5084 gen_exception(dc, dc->pc, EXCP_DEBUG); 5085 dc->is_jmp = DISAS_JUMP; 5086 /* The address covered by the breakpoint must be included in 5087 [tb->pc, tb->pc + tb->size) in order to for it to be 5088 properly cleared -- thus we increment the PC here so that 5089 the logic setting tb->size below does the right thing. */ 5090 dc->pc += 2; 5091 break; 5092 } 5093 5094 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { 5095 gen_io_start(); 5096 } 5097 5098 dc->insn_pc = dc->pc; 5099 disas_m68k_insn(env, dc); 5100 } while (!dc->is_jmp && !tcg_op_buf_full() && 5101 !cs->singlestep_enabled && 5102 !singlestep && 5103 (pc_offset) < (TARGET_PAGE_SIZE - 32) && 5104 num_insns < max_insns); 5105 5106 if (tb->cflags & CF_LAST_IO) 5107 gen_io_end(); 5108 if (unlikely(cs->singlestep_enabled)) { 5109 /* Make sure the pc is updated, and raise a debug exception. */ 5110 if (!dc->is_jmp) { 5111 update_cc_op(dc); 5112 tcg_gen_movi_i32(QREG_PC, dc->pc); 5113 } 5114 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); 5115 } else { 5116 switch(dc->is_jmp) { 5117 case DISAS_NEXT: 5118 update_cc_op(dc); 5119 gen_jmp_tb(dc, 0, dc->pc); 5120 break; 5121 default: 5122 case DISAS_JUMP: 5123 case DISAS_UPDATE: 5124 update_cc_op(dc); 5125 /* indicate that the hash table must be used to find the next TB */ 5126 tcg_gen_exit_tb(0); 5127 break; 5128 case DISAS_TB_JUMP: 5129 /* nothing more to generate */ 5130 break; 5131 } 5132 } 5133 gen_tb_end(tb, num_insns); 5134 5135 #ifdef DEBUG_DISAS 5136 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 5137 && qemu_log_in_addr_range(pc_start)) { 5138 qemu_log_lock(); 5139 qemu_log("----------------\n"); 5140 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 5141 log_target_disas(cs, pc_start, dc->pc - pc_start, 0); 5142 qemu_log("\n"); 5143 qemu_log_unlock(); 5144 } 5145 #endif 5146 tb->size = dc->pc - pc_start; 5147 tb->icount = num_insns; 5148 } 5149 5150 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 5151 int flags) 5152 { 5153 M68kCPU *cpu = M68K_CPU(cs); 5154 CPUM68KState *env = &cpu->env; 5155 int i; 5156 uint16_t sr; 5157 CPU_DoubleU u; 5158 for (i = 0; i < 8; i++) 5159 { 5160 u.d = env->fregs[i]; 5161 cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", 5162 i, env->dregs[i], i, env->aregs[i], 5163 i, u.l.upper, u.l.lower, *(double *)&u.d); 5164 } 5165 cpu_fprintf (f, "PC = %08x ", env->pc); 5166 sr = env->sr | cpu_m68k_get_ccr(env); 5167 cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-', 5168 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', 5169 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); 5170 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); 5171 } 5172 5173 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, 5174 target_ulong *data) 5175 { 5176 int cc_op = data[1]; 5177 env->pc = data[0]; 5178 if (cc_op != CC_OP_DYNAMIC) { 5179 env->cc_op = cc_op; 5180 } 5181 } 5182