1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #define TARGET_LONG_BITS 32 25 26 #define CPUArchState struct CPUM68KState 27 28 #include "qemu-common.h" 29 #include "exec/cpu-defs.h" 30 #include "cpu-qom.h" 31 #include "fpu/softfloat.h" 32 33 #define OS_BYTE 0 34 #define OS_WORD 1 35 #define OS_LONG 2 36 #define OS_SINGLE 3 37 #define OS_DOUBLE 4 38 #define OS_EXTENDED 5 39 #define OS_PACKED 6 40 #define OS_UNSIZED 7 41 42 #define MAX_QREGS 32 43 44 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 45 #define EXCP_ADDRESS 3 /* Address error. */ 46 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 47 #define EXCP_DIV0 5 /* Divide by zero */ 48 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 49 #define EXCP_TRACE 9 50 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 51 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 52 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 53 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 54 #define EXCP_FORMAT 14 /* RTE format error. */ 55 #define EXCP_UNINITIALIZED 15 56 #define EXCP_TRAP0 32 /* User trap #0. */ 57 #define EXCP_TRAP15 47 /* User trap #15. */ 58 #define EXCP_UNSUPPORTED 61 59 #define EXCP_ICE 13 60 61 #define EXCP_RTE 0x100 62 #define EXCP_HALT_INSN 0x101 63 64 #define NB_MMU_MODES 2 65 #define TARGET_INSN_START_EXTRA_WORDS 1 66 67 typedef struct CPUM68KState { 68 uint32_t dregs[8]; 69 uint32_t aregs[8]; 70 uint32_t pc; 71 uint32_t sr; 72 73 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 74 int current_sp; 75 uint32_t sp[2]; 76 77 /* Condition flags. */ 78 uint32_t cc_op; 79 uint32_t cc_x; /* always 0/1 */ 80 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 81 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 82 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 83 uint32_t cc_z; /* == 0 or unused */ 84 85 float64 fregs[8]; 86 float64 fp_result; 87 uint32_t fpcr; 88 uint32_t fpsr; 89 float_status fp_status; 90 91 uint64_t mactmp; 92 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 93 two 8-bit parts. We store a single 64-bit value and 94 rearrange/extend this when changing modes. */ 95 uint64_t macc[4]; 96 uint32_t macsr; 97 uint32_t mac_mask; 98 99 /* MMU status. */ 100 struct { 101 uint32_t ar; 102 } mmu; 103 104 /* Control registers. */ 105 uint32_t vbr; 106 uint32_t mbar; 107 uint32_t rambar0; 108 uint32_t cacr; 109 110 int pending_vector; 111 int pending_level; 112 113 uint32_t qregs[MAX_QREGS]; 114 115 CPU_COMMON 116 117 /* Fields from here on are preserved across CPU reset. */ 118 uint32_t features; 119 } CPUM68KState; 120 121 /** 122 * M68kCPU: 123 * @env: #CPUM68KState 124 * 125 * A Motorola 68k CPU. 126 */ 127 struct M68kCPU { 128 /*< private >*/ 129 CPUState parent_obj; 130 /*< public >*/ 131 132 CPUM68KState env; 133 }; 134 135 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) 136 { 137 return container_of(env, M68kCPU, env); 138 } 139 140 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) 141 142 #define ENV_OFFSET offsetof(M68kCPU, env) 143 144 void m68k_cpu_do_interrupt(CPUState *cpu); 145 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 146 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 147 int flags); 148 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 149 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 150 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 151 152 void m68k_tcg_init(void); 153 void m68k_cpu_init_gdb(M68kCPU *cpu); 154 M68kCPU *cpu_m68k_init(const char *cpu_model); 155 /* you can call this signal handler from your SIGBUS and SIGSEGV 156 signal handlers to inform the virtual CPU of exceptions. non zero 157 is returned if the signal was handled by the virtual CPU. */ 158 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 159 void *puc); 160 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 161 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 162 163 164 /* Instead of computing the condition codes after each m68k instruction, 165 * QEMU just stores one operand (called CC_SRC), the result 166 * (called CC_DEST) and the type of operation (called CC_OP). When the 167 * condition codes are needed, the condition codes can be calculated 168 * using this information. Condition codes are not generated if they 169 * are only needed for conditional branches. 170 */ 171 typedef enum { 172 /* Translator only -- use env->cc_op. */ 173 CC_OP_DYNAMIC = -1, 174 175 /* Each flag bit computed into cc_[xcnvz]. */ 176 CC_OP_FLAGS, 177 178 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 179 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 180 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 181 182 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 183 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 184 185 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 186 CC_OP_LOGIC, 187 188 CC_OP_NB 189 } CCOp; 190 191 #define CCF_C 0x01 192 #define CCF_V 0x02 193 #define CCF_Z 0x04 194 #define CCF_N 0x08 195 #define CCF_X 0x10 196 197 #define SR_I_SHIFT 8 198 #define SR_I 0x0700 199 #define SR_M 0x1000 200 #define SR_S 0x2000 201 #define SR_T 0x8000 202 203 #define M68K_SSP 0 204 #define M68K_USP 1 205 206 /* CACR fields are implementation defined, but some bits are common. */ 207 #define M68K_CACR_EUSP 0x10 208 209 #define MACSR_PAV0 0x100 210 #define MACSR_OMC 0x080 211 #define MACSR_SU 0x040 212 #define MACSR_FI 0x020 213 #define MACSR_RT 0x010 214 #define MACSR_N 0x008 215 #define MACSR_Z 0x004 216 #define MACSR_V 0x002 217 #define MACSR_EV 0x001 218 219 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 220 void m68k_switch_sp(CPUM68KState *env); 221 222 #define M68K_FPCR_PREC (1 << 6) 223 224 void do_m68k_semihosting(CPUM68KState *env, int nr); 225 226 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 227 Each feature covers the subset of instructions common to the 228 ISA revisions mentioned. */ 229 230 enum m68k_features { 231 M68K_FEATURE_M68000, 232 M68K_FEATURE_CF_ISA_A, 233 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 234 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 235 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 236 M68K_FEATURE_CF_FPU, 237 M68K_FEATURE_CF_MAC, 238 M68K_FEATURE_CF_EMAC, 239 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 240 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 241 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 242 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 243 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 244 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 245 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 246 M68K_FEATURE_BCCL, /* Long conditional branches. */ 247 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 248 M68K_FEATURE_FPU, 249 M68K_FEATURE_CAS, 250 M68K_FEATURE_BKPT, 251 }; 252 253 static inline int m68k_feature(CPUM68KState *env, int feature) 254 { 255 return (env->features & (1u << feature)) != 0; 256 } 257 258 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf); 259 260 void register_m68k_insns (CPUM68KState *env); 261 262 #ifdef CONFIG_USER_ONLY 263 /* Coldfire Linux uses 8k pages 264 * and m68k linux uses 4k pages 265 * use the smaller one 266 */ 267 #define TARGET_PAGE_BITS 12 268 #else 269 /* Smallest TLB entry size is 1k. */ 270 #define TARGET_PAGE_BITS 10 271 #endif 272 273 #define TARGET_PHYS_ADDR_SPACE_BITS 32 274 #define TARGET_VIRT_ADDR_SPACE_BITS 32 275 276 #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model)) 277 278 #define cpu_signal_handler cpu_m68k_signal_handler 279 #define cpu_list m68k_cpu_list 280 281 /* MMU modes definitions */ 282 #define MMU_MODE0_SUFFIX _kernel 283 #define MMU_MODE1_SUFFIX _user 284 #define MMU_USER_IDX 1 285 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 286 { 287 return (env->sr & SR_S) == 0 ? 1 : 0; 288 } 289 290 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 291 int mmu_idx); 292 293 #include "exec/cpu-all.h" 294 295 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 296 target_ulong *cs_base, uint32_t *flags) 297 { 298 *pc = env->pc; 299 *cs_base = 0; 300 *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */ 301 | (env->sr & SR_S) /* Bit 13 */ 302 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ 303 } 304 305 #endif 306