1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "exec/cpu-defs.h" 25 #include "qemu/cpu-float.h" 26 #include "cpu-qom.h" 27 28 #define OS_BYTE 0 29 #define OS_WORD 1 30 #define OS_LONG 2 31 #define OS_SINGLE 3 32 #define OS_DOUBLE 4 33 #define OS_EXTENDED 5 34 #define OS_PACKED 6 35 #define OS_UNSIZED 7 36 37 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 38 #define EXCP_ADDRESS 3 /* Address error. */ 39 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 40 #define EXCP_DIV0 5 /* Divide by zero */ 41 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 42 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 43 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 44 #define EXCP_TRACE 9 45 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 46 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 47 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 48 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 49 #define EXCP_FORMAT 14 /* RTE format error. */ 50 #define EXCP_UNINITIALIZED 15 51 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 52 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 53 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 54 #define EXCP_TRAP0 32 /* User trap #0. */ 55 #define EXCP_TRAP15 47 /* User trap #15. */ 56 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 57 #define EXCP_FP_INEX 49 /* Inexact result */ 58 #define EXCP_FP_DZ 50 /* Divide by Zero */ 59 #define EXCP_FP_UNFL 51 /* Underflow */ 60 #define EXCP_FP_OPERR 52 /* Operand Error */ 61 #define EXCP_FP_OVFL 53 /* Overflow */ 62 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 63 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 64 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 65 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 66 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 67 68 #define EXCP_RTE 0x100 69 #define EXCP_HALT_INSN 0x101 70 71 #define M68K_DTTR0 0 72 #define M68K_DTTR1 1 73 #define M68K_ITTR0 2 74 #define M68K_ITTR1 3 75 76 #define M68K_MAX_TTR 2 77 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 78 79 #define TARGET_INSN_START_EXTRA_WORDS 1 80 81 typedef CPU_LDoubleU FPReg; 82 83 typedef struct CPUArchState { 84 uint32_t dregs[8]; 85 uint32_t aregs[8]; 86 uint32_t pc; 87 uint32_t sr; 88 89 /* 90 * The 68020/30/40 support two supervisor stacks, ISP and MSP. 91 * The 68000/10, Coldfire, and CPU32 only have USP/SSP. 92 * 93 * The current_sp is stored in aregs[7], the other here. 94 * The USP, SSP, and if used the additional ISP for 68020/30/40. 95 */ 96 int current_sp; 97 uint32_t sp[3]; 98 99 /* Condition flags. */ 100 uint32_t cc_op; 101 uint32_t cc_x; /* always 0/1 */ 102 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 103 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 104 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 105 uint32_t cc_z; /* == 0 or unused */ 106 107 FPReg fregs[8]; 108 FPReg fp_result; 109 uint32_t fpcr; 110 uint32_t fpsr; 111 float_status fp_status; 112 113 uint64_t mactmp; 114 /* 115 * EMAC Hardware deals with 48-bit values composed of one 32-bit and 116 * two 8-bit parts. We store a single 64-bit value and 117 * rearrange/extend this when changing modes. 118 */ 119 uint64_t macc[4]; 120 uint32_t macsr; 121 uint32_t mac_mask; 122 123 /* MMU status. */ 124 struct { 125 /* 126 * Holds the "address" value in between raising an exception 127 * and creation of the exception stack frame. 128 * Used for both Format 7 exceptions (Access, i.e. mmu) 129 * and Format 2 exceptions (chk, div0, trapcc, etc). 130 */ 131 uint32_t ar; 132 uint32_t ssw; 133 /* 68040 */ 134 uint16_t tcr; 135 uint32_t urp; 136 uint32_t srp; 137 bool fault; 138 uint32_t ttr[4]; 139 uint32_t mmusr; 140 } mmu; 141 142 /* Control registers. */ 143 uint32_t vbr; 144 uint32_t mbar; 145 uint32_t rambar0; 146 uint32_t cacr; 147 uint32_t sfc; 148 uint32_t dfc; 149 150 int pending_vector; 151 int pending_level; 152 153 /* Fields up to this point are cleared by a CPU reset */ 154 struct {} end_reset_fields; 155 156 /* Fields from here on are preserved across CPU reset. */ 157 uint64_t features; 158 } CPUM68KState; 159 160 /* 161 * M68kCPU: 162 * @env: #CPUM68KState 163 * 164 * A Motorola 68k CPU. 165 */ 166 struct ArchCPU { 167 CPUState parent_obj; 168 169 CPUM68KState env; 170 }; 171 172 /* 173 * M68kCPUClass: 174 * @parent_realize: The parent class' realize handler. 175 * @parent_phases: The parent class' reset phase handlers. 176 * 177 * A Motorola 68k CPU model. 178 */ 179 struct M68kCPUClass { 180 CPUClass parent_class; 181 182 DeviceRealize parent_realize; 183 ResettablePhases parent_phases; 184 }; 185 186 #ifndef CONFIG_USER_ONLY 187 void m68k_cpu_do_interrupt(CPUState *cpu); 188 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 189 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 190 #endif /* !CONFIG_USER_ONLY */ 191 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 192 int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 193 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 194 195 void m68k_tcg_init(void); 196 void m68k_cpu_init_gdb(M68kCPU *cpu); 197 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 198 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 199 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 200 void cpu_m68k_restore_fp_status(CPUM68KState *env); 201 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 202 203 204 /* 205 * Instead of computing the condition codes after each m68k instruction, 206 * QEMU just stores one operand (called CC_SRC), the result 207 * (called CC_DEST) and the type of operation (called CC_OP). When the 208 * condition codes are needed, the condition codes can be calculated 209 * using this information. Condition codes are not generated if they 210 * are only needed for conditional branches. 211 */ 212 typedef enum { 213 /* Translator only -- use env->cc_op. */ 214 CC_OP_DYNAMIC, 215 216 /* Each flag bit computed into cc_[xcnvz]. */ 217 CC_OP_FLAGS, 218 219 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 220 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 221 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 222 223 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 224 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 225 226 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 227 CC_OP_LOGIC, 228 229 CC_OP_NB 230 } CCOp; 231 232 #define CCF_C 0x01 233 #define CCF_V 0x02 234 #define CCF_Z 0x04 235 #define CCF_N 0x08 236 #define CCF_X 0x10 237 238 #define SR_I_SHIFT 8 239 #define SR_I 0x0700 240 #define SR_M 0x1000 241 #define SR_S 0x2000 242 #define SR_T_SHIFT 14 243 #define SR_T 0xc000 244 245 #define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT) 246 #define M68K_SR_TRACE_ANY_INS 0x2 247 248 #define M68K_SSP 0 249 #define M68K_USP 1 250 #define M68K_ISP 2 251 252 /* bits for 68040 special status word */ 253 #define M68K_CP_040 0x8000 254 #define M68K_CU_040 0x4000 255 #define M68K_CT_040 0x2000 256 #define M68K_CM_040 0x1000 257 #define M68K_MA_040 0x0800 258 #define M68K_ATC_040 0x0400 259 #define M68K_LK_040 0x0200 260 #define M68K_RW_040 0x0100 261 #define M68K_SIZ_040 0x0060 262 #define M68K_TT_040 0x0018 263 #define M68K_TM_040 0x0007 264 265 #define M68K_TM_040_DATA 0x0001 266 #define M68K_TM_040_CODE 0x0002 267 #define M68K_TM_040_SUPER 0x0004 268 269 /* bits for 68040 write back status word */ 270 #define M68K_WBV_040 0x80 271 #define M68K_WBSIZ_040 0x60 272 #define M68K_WBBYT_040 0x20 273 #define M68K_WBWRD_040 0x40 274 #define M68K_WBLNG_040 0x00 275 #define M68K_WBTT_040 0x18 276 #define M68K_WBTM_040 0x07 277 278 /* bus access size codes */ 279 #define M68K_BA_SIZE_MASK 0x60 280 #define M68K_BA_SIZE_BYTE 0x20 281 #define M68K_BA_SIZE_WORD 0x40 282 #define M68K_BA_SIZE_LONG 0x00 283 #define M68K_BA_SIZE_LINE 0x60 284 285 /* bus access transfer type codes */ 286 #define M68K_BA_TT_MOVE16 0x08 287 288 /* bits for 68040 MMU status register (mmusr) */ 289 #define M68K_MMU_B_040 0x0800 290 #define M68K_MMU_G_040 0x0400 291 #define M68K_MMU_U1_040 0x0200 292 #define M68K_MMU_U0_040 0x0100 293 #define M68K_MMU_S_040 0x0080 294 #define M68K_MMU_CM_040 0x0060 295 #define M68K_MMU_M_040 0x0010 296 #define M68K_MMU_WP_040 0x0004 297 #define M68K_MMU_T_040 0x0002 298 #define M68K_MMU_R_040 0x0001 299 300 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 301 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 302 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 303 M68K_MMU_WP_040) 304 305 /* bits for 68040 MMU Translation Control Register */ 306 #define M68K_TCR_ENABLED 0x8000 307 #define M68K_TCR_PAGE_8K 0x4000 308 309 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 310 #define M68K_DESC_WRITEPROT 0x00000004 311 #define M68K_DESC_USED 0x00000008 312 #define M68K_DESC_MODIFIED 0x00000010 313 #define M68K_DESC_CACHEMODE 0x00000060 314 #define M68K_DESC_CM_WRTHRU 0x00000000 315 #define M68K_DESC_CM_COPYBK 0x00000020 316 #define M68K_DESC_CM_SERIAL 0x00000040 317 #define M68K_DESC_CM_NCACHE 0x00000060 318 #define M68K_DESC_SUPERONLY 0x00000080 319 #define M68K_DESC_USERATTR 0x00000300 320 #define M68K_DESC_USERATTR_SHIFT 8 321 #define M68K_DESC_GLOBAL 0x00000400 322 #define M68K_DESC_URESERVED 0x00000800 323 324 #define M68K_ROOT_POINTER_ENTRIES 128 325 #define M68K_4K_PAGE_MASK (~0xff) 326 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 327 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 328 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 329 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 330 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 331 #define M68K_8K_PAGE_MASK (~0x7f) 332 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 333 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 334 #define M68K_UDT_VALID(entry) (entry & 2) 335 #define M68K_PDT_VALID(entry) (entry & 3) 336 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 337 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 338 #define M68K_TTS_POINTER_SHIFT 18 339 #define M68K_TTS_ROOT_SHIFT 25 340 341 /* bits for 68040 MMU Transparent Translation Registers */ 342 #define M68K_TTR_ADDR_BASE 0xff000000 343 #define M68K_TTR_ADDR_MASK 0x00ff0000 344 #define M68K_TTR_ADDR_MASK_SHIFT 8 345 #define M68K_TTR_ENABLED 0x00008000 346 #define M68K_TTR_SFIELD 0x00006000 347 #define M68K_TTR_SFIELD_USER 0x0000 348 #define M68K_TTR_SFIELD_SUPER 0x2000 349 350 /* m68k Control Registers */ 351 352 /* ColdFire */ 353 /* Memory Management Control Registers */ 354 #define M68K_CR_ASID 0x003 355 #define M68K_CR_ACR0 0x004 356 #define M68K_CR_ACR1 0x005 357 #define M68K_CR_ACR2 0x006 358 #define M68K_CR_ACR3 0x007 359 #define M68K_CR_MMUBAR 0x008 360 361 /* Processor Miscellaneous Registers */ 362 #define M68K_CR_PC 0x80F 363 364 /* Local Memory and Module Control Registers */ 365 #define M68K_CR_ROMBAR0 0xC00 366 #define M68K_CR_ROMBAR1 0xC01 367 #define M68K_CR_RAMBAR0 0xC04 368 #define M68K_CR_RAMBAR1 0xC05 369 #define M68K_CR_MPCR 0xC0C 370 #define M68K_CR_EDRAMBAR 0xC0D 371 #define M68K_CR_SECMBAR 0xC0E 372 #define M68K_CR_MBAR 0xC0F 373 374 /* Local Memory Address Permutation Control Registers */ 375 #define M68K_CR_PCR1U0 0xD02 376 #define M68K_CR_PCR1L0 0xD03 377 #define M68K_CR_PCR2U0 0xD04 378 #define M68K_CR_PCR2L0 0xD05 379 #define M68K_CR_PCR3U0 0xD06 380 #define M68K_CR_PCR3L0 0xD07 381 #define M68K_CR_PCR1U1 0xD0A 382 #define M68K_CR_PCR1L1 0xD0B 383 #define M68K_CR_PCR2U1 0xD0C 384 #define M68K_CR_PCR2L1 0xD0D 385 #define M68K_CR_PCR3U1 0xD0E 386 #define M68K_CR_PCR3L1 0xD0F 387 388 /* MC680x0 */ 389 /* MC680[1234]0/CPU32 */ 390 #define M68K_CR_SFC 0x000 391 #define M68K_CR_DFC 0x001 392 #define M68K_CR_USP 0x800 393 #define M68K_CR_VBR 0x801 /* + Coldfire */ 394 395 /* MC680[234]0 */ 396 #define M68K_CR_CACR 0x002 /* + Coldfire */ 397 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 398 #define M68K_CR_MSP 0x803 399 #define M68K_CR_ISP 0x804 400 401 /* MC68040/MC68LC040 */ 402 #define M68K_CR_TC 0x003 403 #define M68K_CR_ITT0 0x004 404 #define M68K_CR_ITT1 0x005 405 #define M68K_CR_DTT0 0x006 406 #define M68K_CR_DTT1 0x007 407 #define M68K_CR_MMUSR 0x805 408 #define M68K_CR_URP 0x806 409 #define M68K_CR_SRP 0x807 410 411 /* MC68EC040 */ 412 #define M68K_CR_IACR0 0x004 413 #define M68K_CR_IACR1 0x005 414 #define M68K_CR_DACR0 0x006 415 #define M68K_CR_DACR1 0x007 416 417 /* MC68060 */ 418 #define M68K_CR_BUSCR 0x008 419 #define M68K_CR_PCR 0x808 420 421 #define M68K_FPIAR_SHIFT 0 422 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 423 #define M68K_FPSR_SHIFT 1 424 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 425 #define M68K_FPCR_SHIFT 2 426 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 427 428 /* Floating-Point Status Register */ 429 430 /* Condition Code */ 431 #define FPSR_CC_MASK 0x0f000000 432 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 433 #define FPSR_CC_I 0x02000000 /* Infinity */ 434 #define FPSR_CC_Z 0x04000000 /* Zero */ 435 #define FPSR_CC_N 0x08000000 /* Negative */ 436 437 /* Quotient */ 438 439 #define FPSR_QT_MASK 0x00ff0000 440 #define FPSR_QT_SHIFT 16 441 442 /* Floating-Point Control Register */ 443 /* Rounding mode */ 444 #define FPCR_RND_MASK 0x0030 445 #define FPCR_RND_N 0x0000 446 #define FPCR_RND_Z 0x0010 447 #define FPCR_RND_M 0x0020 448 #define FPCR_RND_P 0x0030 449 450 /* Rounding precision */ 451 #define FPCR_PREC_MASK 0x00c0 452 #define FPCR_PREC_X 0x0000 453 #define FPCR_PREC_S 0x0040 454 #define FPCR_PREC_D 0x0080 455 #define FPCR_PREC_U 0x00c0 456 457 #define FPCR_EXCP_MASK 0xff00 458 459 /* CACR fields are implementation defined, but some bits are common. */ 460 #define M68K_CACR_EUSP 0x10 461 462 #define MACSR_PAV0 0x100 463 #define MACSR_OMC 0x080 464 #define MACSR_SU 0x040 465 #define MACSR_FI 0x020 466 #define MACSR_RT 0x010 467 #define MACSR_N 0x008 468 #define MACSR_Z 0x004 469 #define MACSR_V 0x002 470 #define MACSR_EV 0x001 471 472 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 473 void m68k_switch_sp(CPUM68KState *env); 474 475 void do_m68k_semihosting(CPUM68KState *env, int nr); 476 477 /* 478 * The 68000 family is defined in six main CPU classes, the 680[012346]0. 479 * Generally each successive CPU adds enhanced data/stack/instructions. 480 * However, some features are only common to one, or a few classes. 481 * The features covers those subsets of instructons. 482 * 483 * CPU32/32+ are basically 680010 compatible with some 68020 class instructons, 484 * and some additional CPU32 instructions. Mostly Supervisor state differences. 485 * 486 * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu. 487 * There are 4 ColdFire core ISA revisions: A, A+, B and C. 488 * Each feature covers the subset of instructions common to the 489 * ISA revisions mentioned. 490 */ 491 492 enum m68k_features { 493 /* Base Motorola CPU set (not set for Coldfire CPUs) */ 494 M68K_FEATURE_M68K, 495 /* Motorola CPU feature sets */ 496 M68K_FEATURE_M68010, 497 M68K_FEATURE_M68020, 498 M68K_FEATURE_M68030, 499 M68K_FEATURE_M68040, 500 M68K_FEATURE_M68060, 501 /* Base Coldfire set Rev A. */ 502 M68K_FEATURE_CF_ISA_A, 503 /* (ISA B or C). */ 504 M68K_FEATURE_CF_ISA_B, 505 /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 506 M68K_FEATURE_CF_ISA_APLUSC, 507 /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ 508 M68K_FEATURE_BRAL, 509 M68K_FEATURE_CF_FPU, 510 M68K_FEATURE_CF_MAC, 511 M68K_FEATURE_CF_EMAC, 512 /* Revision B EMAC (dual accumulate). */ 513 M68K_FEATURE_CF_EMAC_B, 514 /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ 515 M68K_FEATURE_USP, 516 /* Master Stack Pointer. (680[234]0) */ 517 M68K_FEATURE_MSP, 518 /* 68020+ full extension word. */ 519 M68K_FEATURE_EXT_FULL, 520 /* word sized address index registers. */ 521 M68K_FEATURE_WORD_INDEX, 522 /* scaled address index registers. */ 523 M68K_FEATURE_SCALED_INDEX, 524 /* 32 bit mul/div. (680[2346]0, and CPU32) */ 525 M68K_FEATURE_LONG_MULDIV, 526 /* 64 bit mul/div. (680[2346]0, and CPU32) */ 527 M68K_FEATURE_QUAD_MULDIV, 528 /* Bcc with Long branches. (680[2346]0, and CPU32) */ 529 M68K_FEATURE_BCCL, 530 /* BFxxx Bit field insns. (680[2346]0) */ 531 M68K_FEATURE_BITFIELD, 532 /* fpu insn. (680[46]0) */ 533 M68K_FEATURE_FPU, 534 /* CAS/CAS2[WL] insns. (680[2346]0) */ 535 M68K_FEATURE_CAS, 536 /* BKPT insn. (680[12346]0, and CPU32) */ 537 M68K_FEATURE_BKPT, 538 /* RTD insn. (680[12346]0, and CPU32) */ 539 M68K_FEATURE_RTD, 540 /* CHK2 insn. (680[2346]0, and CPU32) */ 541 M68K_FEATURE_CHK2, 542 /* MOVEP insn. (680[01234]0, and CPU32) */ 543 M68K_FEATURE_MOVEP, 544 /* MOVEC insn. (from 68010) */ 545 M68K_FEATURE_MOVEC, 546 /* Unaligned data accesses (680[2346]0) */ 547 M68K_FEATURE_UNALIGNED_DATA, 548 /* TRAPcc insn. (680[2346]0, and CPU32) */ 549 M68K_FEATURE_TRAPCC, 550 /* MOVE from SR privileged (from 68010) */ 551 M68K_FEATURE_MOVEFROMSR_PRIV, 552 }; 553 554 static inline bool m68k_feature(CPUM68KState *env, int feature) 555 { 556 return (env->features & BIT_ULL(feature)) != 0; 557 } 558 559 void m68k_cpu_list(void); 560 561 void register_m68k_insns (CPUM68KState *env); 562 563 enum { 564 /* 1 bit to define user level / supervisor access */ 565 ACCESS_SUPER = 0x01, 566 /* 1 bit to indicate direction */ 567 ACCESS_STORE = 0x02, 568 /* 1 bit to indicate debug access */ 569 ACCESS_DEBUG = 0x04, 570 /* PTEST instruction */ 571 ACCESS_PTEST = 0x08, 572 /* Type of instruction that generated the access */ 573 ACCESS_CODE = 0x10, /* Code fetch access */ 574 ACCESS_DATA = 0x20, /* Data load/store access */ 575 }; 576 577 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 578 579 #define cpu_list m68k_cpu_list 580 581 /* MMU modes definitions */ 582 #define MMU_KERNEL_IDX 0 583 #define MMU_USER_IDX 1 584 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 585 { 586 return (env->sr & SR_S) == 0 ? 1 : 0; 587 } 588 589 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 590 MMUAccessType access_type, int mmu_idx, 591 bool probe, uintptr_t retaddr); 592 #ifndef CONFIG_USER_ONLY 593 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 594 unsigned size, MMUAccessType access_type, 595 int mmu_idx, MemTxAttrs attrs, 596 MemTxResult response, uintptr_t retaddr); 597 #endif 598 599 #include "exec/cpu-all.h" 600 601 /* TB flags */ 602 #define TB_FLAGS_MACSR 0x0f 603 #define TB_FLAGS_MSR_S_BIT 13 604 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 605 #define TB_FLAGS_SFC_S_BIT 14 606 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 607 #define TB_FLAGS_DFC_S_BIT 15 608 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 609 #define TB_FLAGS_TRACE 16 610 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) 611 612 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, 613 uint64_t *cs_base, uint32_t *flags) 614 { 615 *pc = env->pc; 616 *cs_base = 0; 617 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 618 if (env->sr & SR_S) { 619 *flags |= TB_FLAGS_MSR_S; 620 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 621 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 622 } 623 if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { 624 *flags |= TB_FLAGS_TRACE; 625 } 626 } 627 628 void dump_mmu(CPUM68KState *env); 629 630 #endif 631