1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #define TARGET_LONG_BITS 32 25 26 #define CPUArchState struct CPUM68KState 27 28 #include "qemu-common.h" 29 #include "exec/cpu-defs.h" 30 #include "cpu-qom.h" 31 32 #define OS_BYTE 0 33 #define OS_WORD 1 34 #define OS_LONG 2 35 #define OS_SINGLE 3 36 #define OS_DOUBLE 4 37 #define OS_EXTENDED 5 38 #define OS_PACKED 6 39 #define OS_UNSIZED 7 40 41 #define MAX_QREGS 32 42 43 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 44 #define EXCP_ADDRESS 3 /* Address error. */ 45 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 46 #define EXCP_DIV0 5 /* Divide by zero */ 47 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 48 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 49 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 50 #define EXCP_TRACE 9 51 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 52 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 53 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 54 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 55 #define EXCP_FORMAT 14 /* RTE format error. */ 56 #define EXCP_UNINITIALIZED 15 57 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 58 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 59 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 60 #define EXCP_TRAP0 32 /* User trap #0. */ 61 #define EXCP_TRAP15 47 /* User trap #15. */ 62 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 63 #define EXCP_FP_INEX 49 /* Inexact result */ 64 #define EXCP_FP_DZ 50 /* Divide by Zero */ 65 #define EXCP_FP_UNFL 51 /* Underflow */ 66 #define EXCP_FP_OPERR 52 /* Operand Error */ 67 #define EXCP_FP_OVFL 53 /* Overflow */ 68 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 69 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 70 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 71 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 72 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 73 #define EXCP_UNSUPPORTED 61 74 75 #define EXCP_RTE 0x100 76 #define EXCP_HALT_INSN 0x101 77 78 #define M68K_DTTR0 0 79 #define M68K_DTTR1 1 80 #define M68K_ITTR0 2 81 #define M68K_ITTR1 3 82 83 #define M68K_MAX_TTR 2 84 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 85 86 #define NB_MMU_MODES 2 87 #define TARGET_INSN_START_EXTRA_WORDS 1 88 89 typedef CPU_LDoubleU FPReg; 90 91 typedef struct CPUM68KState { 92 uint32_t dregs[8]; 93 uint32_t aregs[8]; 94 uint32_t pc; 95 uint32_t sr; 96 97 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 98 int current_sp; 99 uint32_t sp[3]; 100 101 /* Condition flags. */ 102 uint32_t cc_op; 103 uint32_t cc_x; /* always 0/1 */ 104 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 105 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 106 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 107 uint32_t cc_z; /* == 0 or unused */ 108 109 FPReg fregs[8]; 110 FPReg fp_result; 111 uint32_t fpcr; 112 uint32_t fpsr; 113 float_status fp_status; 114 115 uint64_t mactmp; 116 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 117 two 8-bit parts. We store a single 64-bit value and 118 rearrange/extend this when changing modes. */ 119 uint64_t macc[4]; 120 uint32_t macsr; 121 uint32_t mac_mask; 122 123 /* MMU status. */ 124 struct { 125 uint32_t ar; 126 uint32_t ssw; 127 /* 68040 */ 128 uint16_t tcr; 129 uint32_t urp; 130 uint32_t srp; 131 bool fault; 132 uint32_t ttr[4]; 133 uint32_t mmusr; 134 } mmu; 135 136 /* Control registers. */ 137 uint32_t vbr; 138 uint32_t mbar; 139 uint32_t rambar0; 140 uint32_t cacr; 141 uint32_t sfc; 142 uint32_t dfc; 143 144 int pending_vector; 145 int pending_level; 146 147 uint32_t qregs[MAX_QREGS]; 148 149 /* Fields up to this point are cleared by a CPU reset */ 150 struct {} end_reset_fields; 151 152 CPU_COMMON 153 154 /* Fields from here on are preserved across CPU reset. */ 155 uint32_t features; 156 } CPUM68KState; 157 158 /** 159 * M68kCPU: 160 * @env: #CPUM68KState 161 * 162 * A Motorola 68k CPU. 163 */ 164 struct M68kCPU { 165 /*< private >*/ 166 CPUState parent_obj; 167 /*< public >*/ 168 169 CPUM68KState env; 170 }; 171 172 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) 173 { 174 return container_of(env, M68kCPU, env); 175 } 176 177 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) 178 179 #define ENV_OFFSET offsetof(M68kCPU, env) 180 181 void m68k_cpu_do_interrupt(CPUState *cpu); 182 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 183 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 184 int flags); 185 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 186 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 187 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 188 189 void m68k_tcg_init(void); 190 void m68k_cpu_init_gdb(M68kCPU *cpu); 191 /* you can call this signal handler from your SIGBUS and SIGSEGV 192 signal handlers to inform the virtual CPU of exceptions. non zero 193 is returned if the signal was handled by the virtual CPU. */ 194 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 195 void *puc); 196 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 197 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 198 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 199 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 200 201 202 /* Instead of computing the condition codes after each m68k instruction, 203 * QEMU just stores one operand (called CC_SRC), the result 204 * (called CC_DEST) and the type of operation (called CC_OP). When the 205 * condition codes are needed, the condition codes can be calculated 206 * using this information. Condition codes are not generated if they 207 * are only needed for conditional branches. 208 */ 209 typedef enum { 210 /* Translator only -- use env->cc_op. */ 211 CC_OP_DYNAMIC, 212 213 /* Each flag bit computed into cc_[xcnvz]. */ 214 CC_OP_FLAGS, 215 216 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 217 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 218 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 219 220 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 221 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 222 223 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 224 CC_OP_LOGIC, 225 226 CC_OP_NB 227 } CCOp; 228 229 #define CCF_C 0x01 230 #define CCF_V 0x02 231 #define CCF_Z 0x04 232 #define CCF_N 0x08 233 #define CCF_X 0x10 234 235 #define SR_I_SHIFT 8 236 #define SR_I 0x0700 237 #define SR_M 0x1000 238 #define SR_S 0x2000 239 #define SR_T_SHIFT 14 240 #define SR_T 0xc000 241 242 #define M68K_SSP 0 243 #define M68K_USP 1 244 #define M68K_ISP 2 245 246 /* bits for 68040 special status word */ 247 #define M68K_CP_040 0x8000 248 #define M68K_CU_040 0x4000 249 #define M68K_CT_040 0x2000 250 #define M68K_CM_040 0x1000 251 #define M68K_MA_040 0x0800 252 #define M68K_ATC_040 0x0400 253 #define M68K_LK_040 0x0200 254 #define M68K_RW_040 0x0100 255 #define M68K_SIZ_040 0x0060 256 #define M68K_TT_040 0x0018 257 #define M68K_TM_040 0x0007 258 259 #define M68K_TM_040_DATA 0x0001 260 #define M68K_TM_040_CODE 0x0002 261 #define M68K_TM_040_SUPER 0x0004 262 263 /* bits for 68040 write back status word */ 264 #define M68K_WBV_040 0x80 265 #define M68K_WBSIZ_040 0x60 266 #define M68K_WBBYT_040 0x20 267 #define M68K_WBWRD_040 0x40 268 #define M68K_WBLNG_040 0x00 269 #define M68K_WBTT_040 0x18 270 #define M68K_WBTM_040 0x07 271 272 /* bus access size codes */ 273 #define M68K_BA_SIZE_MASK 0x60 274 #define M68K_BA_SIZE_BYTE 0x20 275 #define M68K_BA_SIZE_WORD 0x40 276 #define M68K_BA_SIZE_LONG 0x00 277 #define M68K_BA_SIZE_LINE 0x60 278 279 /* bus access transfer type codes */ 280 #define M68K_BA_TT_MOVE16 0x08 281 282 /* bits for 68040 MMU status register (mmusr) */ 283 #define M68K_MMU_B_040 0x0800 284 #define M68K_MMU_G_040 0x0400 285 #define M68K_MMU_U1_040 0x0200 286 #define M68K_MMU_U0_040 0x0100 287 #define M68K_MMU_S_040 0x0080 288 #define M68K_MMU_CM_040 0x0060 289 #define M68K_MMU_M_040 0x0010 290 #define M68K_MMU_WP_040 0x0004 291 #define M68K_MMU_T_040 0x0002 292 #define M68K_MMU_R_040 0x0001 293 294 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 295 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 296 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 297 M68K_MMU_WP_040) 298 299 /* bits for 68040 MMU Translation Control Register */ 300 #define M68K_TCR_ENABLED 0x8000 301 #define M68K_TCR_PAGE_8K 0x4000 302 303 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 304 #define M68K_DESC_WRITEPROT 0x00000004 305 #define M68K_DESC_USED 0x00000008 306 #define M68K_DESC_MODIFIED 0x00000010 307 #define M68K_DESC_CACHEMODE 0x00000060 308 #define M68K_DESC_CM_WRTHRU 0x00000000 309 #define M68K_DESC_CM_COPYBK 0x00000020 310 #define M68K_DESC_CM_SERIAL 0x00000040 311 #define M68K_DESC_CM_NCACHE 0x00000060 312 #define M68K_DESC_SUPERONLY 0x00000080 313 #define M68K_DESC_USERATTR 0x00000300 314 #define M68K_DESC_USERATTR_SHIFT 8 315 #define M68K_DESC_GLOBAL 0x00000400 316 #define M68K_DESC_URESERVED 0x00000800 317 318 #define M68K_ROOT_POINTER_ENTRIES 128 319 #define M68K_4K_PAGE_MASK (~0xff) 320 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 321 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 322 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 323 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 324 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 325 #define M68K_8K_PAGE_MASK (~0x7f) 326 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 327 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 328 #define M68K_UDT_VALID(entry) (entry & 2) 329 #define M68K_PDT_VALID(entry) (entry & 3) 330 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 331 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 332 #define M68K_TTS_POINTER_SHIFT 18 333 #define M68K_TTS_ROOT_SHIFT 25 334 335 /* bits for 68040 MMU Transparent Translation Registers */ 336 #define M68K_TTR_ADDR_BASE 0xff000000 337 #define M68K_TTR_ADDR_MASK 0x00ff0000 338 #define M68K_TTR_ADDR_MASK_SHIFT 8 339 #define M68K_TTR_ENABLED 0x00008000 340 #define M68K_TTR_SFIELD 0x00006000 341 #define M68K_TTR_SFIELD_USER 0x0000 342 #define M68K_TTR_SFIELD_SUPER 0x2000 343 344 /* m68k Control Registers */ 345 346 /* ColdFire */ 347 /* Memory Management Control Registers */ 348 #define M68K_CR_ASID 0x003 349 #define M68K_CR_ACR0 0x004 350 #define M68K_CR_ACR1 0x005 351 #define M68K_CR_ACR2 0x006 352 #define M68K_CR_ACR3 0x007 353 #define M68K_CR_MMUBAR 0x008 354 355 /* Processor Miscellaneous Registers */ 356 #define M68K_CR_PC 0x80F 357 358 /* Local Memory and Module Control Registers */ 359 #define M68K_CR_ROMBAR0 0xC00 360 #define M68K_CR_ROMBAR1 0xC01 361 #define M68K_CR_RAMBAR0 0xC04 362 #define M68K_CR_RAMBAR1 0xC05 363 #define M68K_CR_MPCR 0xC0C 364 #define M68K_CR_EDRAMBAR 0xC0D 365 #define M68K_CR_SECMBAR 0xC0E 366 #define M68K_CR_MBAR 0xC0F 367 368 /* Local Memory Address Permutation Control Registers */ 369 #define M68K_CR_PCR1U0 0xD02 370 #define M68K_CR_PCR1L0 0xD03 371 #define M68K_CR_PCR2U0 0xD04 372 #define M68K_CR_PCR2L0 0xD05 373 #define M68K_CR_PCR3U0 0xD06 374 #define M68K_CR_PCR3L0 0xD07 375 #define M68K_CR_PCR1U1 0xD0A 376 #define M68K_CR_PCR1L1 0xD0B 377 #define M68K_CR_PCR2U1 0xD0C 378 #define M68K_CR_PCR2L1 0xD0D 379 #define M68K_CR_PCR3U1 0xD0E 380 #define M68K_CR_PCR3L1 0xD0F 381 382 /* MC680x0 */ 383 /* MC680[1234]0/CPU32 */ 384 #define M68K_CR_SFC 0x000 385 #define M68K_CR_DFC 0x001 386 #define M68K_CR_USP 0x800 387 #define M68K_CR_VBR 0x801 /* + Coldfire */ 388 389 /* MC680[234]0 */ 390 #define M68K_CR_CACR 0x002 /* + Coldfire */ 391 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 392 #define M68K_CR_MSP 0x803 393 #define M68K_CR_ISP 0x804 394 395 /* MC68040/MC68LC040 */ 396 #define M68K_CR_TC 0x003 397 #define M68K_CR_ITT0 0x004 398 #define M68K_CR_ITT1 0x005 399 #define M68K_CR_DTT0 0x006 400 #define M68K_CR_DTT1 0x007 401 #define M68K_CR_MMUSR 0x805 402 #define M68K_CR_URP 0x806 403 #define M68K_CR_SRP 0x807 404 405 /* MC68EC040 */ 406 #define M68K_CR_IACR0 0x004 407 #define M68K_CR_IACR1 0x005 408 #define M68K_CR_DACR0 0x006 409 #define M68K_CR_DACR1 0x007 410 411 #define M68K_FPIAR_SHIFT 0 412 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 413 #define M68K_FPSR_SHIFT 1 414 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 415 #define M68K_FPCR_SHIFT 2 416 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 417 418 /* Floating-Point Status Register */ 419 420 /* Condition Code */ 421 #define FPSR_CC_MASK 0x0f000000 422 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 423 #define FPSR_CC_I 0x02000000 /* Infinity */ 424 #define FPSR_CC_Z 0x04000000 /* Zero */ 425 #define FPSR_CC_N 0x08000000 /* Negative */ 426 427 /* Quotient */ 428 429 #define FPSR_QT_MASK 0x00ff0000 430 #define FPSR_QT_SHIFT 16 431 432 /* Floating-Point Control Register */ 433 /* Rounding mode */ 434 #define FPCR_RND_MASK 0x0030 435 #define FPCR_RND_N 0x0000 436 #define FPCR_RND_Z 0x0010 437 #define FPCR_RND_M 0x0020 438 #define FPCR_RND_P 0x0030 439 440 /* Rounding precision */ 441 #define FPCR_PREC_MASK 0x00c0 442 #define FPCR_PREC_X 0x0000 443 #define FPCR_PREC_S 0x0040 444 #define FPCR_PREC_D 0x0080 445 #define FPCR_PREC_U 0x00c0 446 447 #define FPCR_EXCP_MASK 0xff00 448 449 /* CACR fields are implementation defined, but some bits are common. */ 450 #define M68K_CACR_EUSP 0x10 451 452 #define MACSR_PAV0 0x100 453 #define MACSR_OMC 0x080 454 #define MACSR_SU 0x040 455 #define MACSR_FI 0x020 456 #define MACSR_RT 0x010 457 #define MACSR_N 0x008 458 #define MACSR_Z 0x004 459 #define MACSR_V 0x002 460 #define MACSR_EV 0x001 461 462 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 463 void m68k_switch_sp(CPUM68KState *env); 464 465 void do_m68k_semihosting(CPUM68KState *env, int nr); 466 467 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 468 Each feature covers the subset of instructions common to the 469 ISA revisions mentioned. */ 470 471 enum m68k_features { 472 M68K_FEATURE_M68000, 473 M68K_FEATURE_CF_ISA_A, 474 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 475 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 476 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 477 M68K_FEATURE_CF_FPU, 478 M68K_FEATURE_CF_MAC, 479 M68K_FEATURE_CF_EMAC, 480 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 481 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 482 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 483 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 484 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 485 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 486 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 487 M68K_FEATURE_BCCL, /* Long conditional branches. */ 488 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 489 M68K_FEATURE_FPU, 490 M68K_FEATURE_CAS, 491 M68K_FEATURE_BKPT, 492 M68K_FEATURE_RTD, 493 M68K_FEATURE_CHK2, 494 M68K_FEATURE_M68040, /* instructions specific to MC68040 */ 495 M68K_FEATURE_MOVEP, 496 }; 497 498 static inline int m68k_feature(CPUM68KState *env, int feature) 499 { 500 return (env->features & (1u << feature)) != 0; 501 } 502 503 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf); 504 505 void register_m68k_insns (CPUM68KState *env); 506 507 /* Coldfire Linux uses 8k pages 508 * and m68k linux uses 4k pages 509 * use the smallest one 510 */ 511 #define TARGET_PAGE_BITS 12 512 513 enum { 514 /* 1 bit to define user level / supervisor access */ 515 ACCESS_SUPER = 0x01, 516 /* 1 bit to indicate direction */ 517 ACCESS_STORE = 0x02, 518 /* 1 bit to indicate debug access */ 519 ACCESS_DEBUG = 0x04, 520 /* PTEST instruction */ 521 ACCESS_PTEST = 0x08, 522 /* Type of instruction that generated the access */ 523 ACCESS_CODE = 0x10, /* Code fetch access */ 524 ACCESS_DATA = 0x20, /* Data load/store access */ 525 }; 526 527 #define TARGET_PHYS_ADDR_SPACE_BITS 32 528 #define TARGET_VIRT_ADDR_SPACE_BITS 32 529 530 #define cpu_init(cpu_model) cpu_generic_init(TYPE_M68K_CPU, cpu_model) 531 532 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 533 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 534 535 #define cpu_signal_handler cpu_m68k_signal_handler 536 #define cpu_list m68k_cpu_list 537 538 /* MMU modes definitions */ 539 #define MMU_MODE0_SUFFIX _kernel 540 #define MMU_MODE1_SUFFIX _user 541 #define MMU_KERNEL_IDX 0 542 #define MMU_USER_IDX 1 543 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 544 { 545 return (env->sr & SR_S) == 0 ? 1 : 0; 546 } 547 548 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, 549 int mmu_idx); 550 void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, 551 bool is_write, bool is_exec, int is_asi, 552 unsigned size); 553 554 #include "exec/cpu-all.h" 555 556 /* TB flags */ 557 #define TB_FLAGS_MACSR 0x0f 558 #define TB_FLAGS_MSR_S_BIT 13 559 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 560 #define TB_FLAGS_SFC_S_BIT 14 561 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 562 #define TB_FLAGS_DFC_S_BIT 15 563 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 564 565 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 566 target_ulong *cs_base, uint32_t *flags) 567 { 568 *pc = env->pc; 569 *cs_base = 0; 570 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 571 if (env->sr & SR_S) { 572 *flags |= TB_FLAGS_MSR_S; 573 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 574 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 575 } 576 } 577 578 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env); 579 #endif 580