1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #define TARGET_LONG_BITS 32 25 26 #define CPUArchState struct CPUM68KState 27 28 #include "qemu-common.h" 29 #include "exec/cpu-defs.h" 30 #include "cpu-qom.h" 31 #include "fpu/softfloat.h" 32 33 #define OS_BYTE 0 34 #define OS_WORD 1 35 #define OS_LONG 2 36 #define OS_SINGLE 3 37 #define OS_DOUBLE 4 38 #define OS_EXTENDED 5 39 #define OS_PACKED 6 40 #define OS_UNSIZED 7 41 42 #define MAX_QREGS 32 43 44 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 45 #define EXCP_ADDRESS 3 /* Address error. */ 46 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 47 #define EXCP_DIV0 5 /* Divide by zero */ 48 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 49 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 50 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 51 #define EXCP_TRACE 9 52 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 53 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 54 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 55 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 56 #define EXCP_FORMAT 14 /* RTE format error. */ 57 #define EXCP_UNINITIALIZED 15 58 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 59 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 60 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 61 #define EXCP_TRAP0 32 /* User trap #0. */ 62 #define EXCP_TRAP15 47 /* User trap #15. */ 63 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 64 #define EXCP_FP_INEX 49 /* Inexact result */ 65 #define EXCP_FP_DZ 50 /* Divide by Zero */ 66 #define EXCP_FP_UNFL 51 /* Underflow */ 67 #define EXCP_FP_OPERR 52 /* Operand Error */ 68 #define EXCP_FP_OVFL 53 /* Overflow */ 69 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 70 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 71 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 72 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 73 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 74 #define EXCP_UNSUPPORTED 61 75 76 #define EXCP_RTE 0x100 77 #define EXCP_HALT_INSN 0x101 78 79 #define NB_MMU_MODES 2 80 #define TARGET_INSN_START_EXTRA_WORDS 1 81 82 typedef CPU_LDoubleU FPReg; 83 84 typedef struct CPUM68KState { 85 uint32_t dregs[8]; 86 uint32_t aregs[8]; 87 uint32_t pc; 88 uint32_t sr; 89 90 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 91 int current_sp; 92 uint32_t sp[3]; 93 94 /* Condition flags. */ 95 uint32_t cc_op; 96 uint32_t cc_x; /* always 0/1 */ 97 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 98 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 99 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 100 uint32_t cc_z; /* == 0 or unused */ 101 102 FPReg fregs[8]; 103 FPReg fp_result; 104 uint32_t fpcr; 105 uint32_t fpsr; 106 float_status fp_status; 107 108 uint64_t mactmp; 109 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 110 two 8-bit parts. We store a single 64-bit value and 111 rearrange/extend this when changing modes. */ 112 uint64_t macc[4]; 113 uint32_t macsr; 114 uint32_t mac_mask; 115 116 /* MMU status. */ 117 struct { 118 uint32_t ar; 119 } mmu; 120 121 /* Control registers. */ 122 uint32_t vbr; 123 uint32_t mbar; 124 uint32_t rambar0; 125 uint32_t cacr; 126 127 int pending_vector; 128 int pending_level; 129 130 uint32_t qregs[MAX_QREGS]; 131 132 /* Fields up to this point are cleared by a CPU reset */ 133 struct {} end_reset_fields; 134 135 CPU_COMMON 136 137 /* Fields from here on are preserved across CPU reset. */ 138 uint32_t features; 139 } CPUM68KState; 140 141 /** 142 * M68kCPU: 143 * @env: #CPUM68KState 144 * 145 * A Motorola 68k CPU. 146 */ 147 struct M68kCPU { 148 /*< private >*/ 149 CPUState parent_obj; 150 /*< public >*/ 151 152 CPUM68KState env; 153 }; 154 155 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) 156 { 157 return container_of(env, M68kCPU, env); 158 } 159 160 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) 161 162 #define ENV_OFFSET offsetof(M68kCPU, env) 163 164 void m68k_cpu_do_interrupt(CPUState *cpu); 165 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 166 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 167 int flags); 168 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 169 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 170 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 171 172 void m68k_tcg_init(void); 173 void m68k_cpu_init_gdb(M68kCPU *cpu); 174 /* you can call this signal handler from your SIGBUS and SIGSEGV 175 signal handlers to inform the virtual CPU of exceptions. non zero 176 is returned if the signal was handled by the virtual CPU. */ 177 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 178 void *puc); 179 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 180 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 181 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 182 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 183 184 185 /* Instead of computing the condition codes after each m68k instruction, 186 * QEMU just stores one operand (called CC_SRC), the result 187 * (called CC_DEST) and the type of operation (called CC_OP). When the 188 * condition codes are needed, the condition codes can be calculated 189 * using this information. Condition codes are not generated if they 190 * are only needed for conditional branches. 191 */ 192 typedef enum { 193 /* Translator only -- use env->cc_op. */ 194 CC_OP_DYNAMIC, 195 196 /* Each flag bit computed into cc_[xcnvz]. */ 197 CC_OP_FLAGS, 198 199 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 200 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 201 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 202 203 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 204 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 205 206 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 207 CC_OP_LOGIC, 208 209 CC_OP_NB 210 } CCOp; 211 212 #define CCF_C 0x01 213 #define CCF_V 0x02 214 #define CCF_Z 0x04 215 #define CCF_N 0x08 216 #define CCF_X 0x10 217 218 #define SR_I_SHIFT 8 219 #define SR_I 0x0700 220 #define SR_M 0x1000 221 #define SR_S 0x2000 222 #define SR_T_SHIFT 14 223 #define SR_T 0xc000 224 225 #define M68K_SSP 0 226 #define M68K_USP 1 227 #define M68K_ISP 2 228 229 /* m68k Control Registers */ 230 231 /* ColdFire */ 232 /* Memory Management Control Registers */ 233 #define M68K_CR_ASID 0x003 234 #define M68K_CR_ACR0 0x004 235 #define M68K_CR_ACR1 0x005 236 #define M68K_CR_ACR2 0x006 237 #define M68K_CR_ACR3 0x007 238 #define M68K_CR_MMUBAR 0x008 239 240 /* Processor Miscellaneous Registers */ 241 #define M68K_CR_PC 0x80F 242 243 /* Local Memory and Module Control Registers */ 244 #define M68K_CR_ROMBAR0 0xC00 245 #define M68K_CR_ROMBAR1 0xC01 246 #define M68K_CR_RAMBAR0 0xC04 247 #define M68K_CR_RAMBAR1 0xC05 248 #define M68K_CR_MPCR 0xC0C 249 #define M68K_CR_EDRAMBAR 0xC0D 250 #define M68K_CR_SECMBAR 0xC0E 251 #define M68K_CR_MBAR 0xC0F 252 253 /* Local Memory Address Permutation Control Registers */ 254 #define M68K_CR_PCR1U0 0xD02 255 #define M68K_CR_PCR1L0 0xD03 256 #define M68K_CR_PCR2U0 0xD04 257 #define M68K_CR_PCR2L0 0xD05 258 #define M68K_CR_PCR3U0 0xD06 259 #define M68K_CR_PCR3L0 0xD07 260 #define M68K_CR_PCR1U1 0xD0A 261 #define M68K_CR_PCR1L1 0xD0B 262 #define M68K_CR_PCR2U1 0xD0C 263 #define M68K_CR_PCR2L1 0xD0D 264 #define M68K_CR_PCR3U1 0xD0E 265 #define M68K_CR_PCR3L1 0xD0F 266 267 /* MC680x0 */ 268 /* MC680[1234]0/CPU32 */ 269 #define M68K_CR_SFC 0x000 270 #define M68K_CR_DFC 0x001 271 #define M68K_CR_USP 0x800 272 #define M68K_CR_VBR 0x801 /* + Coldfire */ 273 274 /* MC680[234]0 */ 275 #define M68K_CR_CACR 0x002 /* + Coldfire */ 276 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 277 #define M68K_CR_MSP 0x803 278 #define M68K_CR_ISP 0x804 279 280 /* MC68040/MC68LC040 */ 281 #define M68K_CR_TC 0x003 282 #define M68K_CR_ITT0 0x004 283 #define M68K_CR_ITT1 0x005 284 #define M68K_CR_DTT0 0x006 285 #define M68K_CR_DTT1 0x007 286 #define M68K_CR_MMUSR 0x805 287 #define M68K_CR_URP 0x806 288 #define M68K_CR_SRP 0x807 289 290 /* MC68EC040 */ 291 #define M68K_CR_IACR0 0x004 292 #define M68K_CR_IACR1 0x005 293 #define M68K_CR_DACR0 0x006 294 #define M68K_CR_DACR1 0x007 295 296 #define M68K_FPIAR_SHIFT 0 297 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 298 #define M68K_FPSR_SHIFT 1 299 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 300 #define M68K_FPCR_SHIFT 2 301 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 302 303 /* Floating-Point Status Register */ 304 305 /* Condition Code */ 306 #define FPSR_CC_MASK 0x0f000000 307 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 308 #define FPSR_CC_I 0x02000000 /* Infinity */ 309 #define FPSR_CC_Z 0x04000000 /* Zero */ 310 #define FPSR_CC_N 0x08000000 /* Negative */ 311 312 /* Quotient */ 313 314 #define FPSR_QT_MASK 0x00ff0000 315 316 /* Floating-Point Control Register */ 317 /* Rounding mode */ 318 #define FPCR_RND_MASK 0x0030 319 #define FPCR_RND_N 0x0000 320 #define FPCR_RND_Z 0x0010 321 #define FPCR_RND_M 0x0020 322 #define FPCR_RND_P 0x0030 323 324 /* Rounding precision */ 325 #define FPCR_PREC_MASK 0x00c0 326 #define FPCR_PREC_X 0x0000 327 #define FPCR_PREC_S 0x0040 328 #define FPCR_PREC_D 0x0080 329 #define FPCR_PREC_U 0x00c0 330 331 #define FPCR_EXCP_MASK 0xff00 332 333 /* CACR fields are implementation defined, but some bits are common. */ 334 #define M68K_CACR_EUSP 0x10 335 336 #define MACSR_PAV0 0x100 337 #define MACSR_OMC 0x080 338 #define MACSR_SU 0x040 339 #define MACSR_FI 0x020 340 #define MACSR_RT 0x010 341 #define MACSR_N 0x008 342 #define MACSR_Z 0x004 343 #define MACSR_V 0x002 344 #define MACSR_EV 0x001 345 346 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 347 void m68k_switch_sp(CPUM68KState *env); 348 349 void do_m68k_semihosting(CPUM68KState *env, int nr); 350 351 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 352 Each feature covers the subset of instructions common to the 353 ISA revisions mentioned. */ 354 355 enum m68k_features { 356 M68K_FEATURE_M68000, 357 M68K_FEATURE_CF_ISA_A, 358 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 359 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 360 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 361 M68K_FEATURE_CF_FPU, 362 M68K_FEATURE_CF_MAC, 363 M68K_FEATURE_CF_EMAC, 364 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 365 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 366 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 367 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 368 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 369 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 370 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 371 M68K_FEATURE_BCCL, /* Long conditional branches. */ 372 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 373 M68K_FEATURE_FPU, 374 M68K_FEATURE_CAS, 375 M68K_FEATURE_BKPT, 376 M68K_FEATURE_RTD, 377 M68K_FEATURE_CHK2, 378 M68K_FEATURE_M68040, /* instructions specific to MC68040 */ 379 }; 380 381 static inline int m68k_feature(CPUM68KState *env, int feature) 382 { 383 return (env->features & (1u << feature)) != 0; 384 } 385 386 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf); 387 388 void register_m68k_insns (CPUM68KState *env); 389 390 #ifdef CONFIG_USER_ONLY 391 /* Coldfire Linux uses 8k pages 392 * and m68k linux uses 4k pages 393 * use the smaller one 394 */ 395 #define TARGET_PAGE_BITS 12 396 #else 397 /* Smallest TLB entry size is 1k. */ 398 #define TARGET_PAGE_BITS 10 399 #endif 400 401 #define TARGET_PHYS_ADDR_SPACE_BITS 32 402 #define TARGET_VIRT_ADDR_SPACE_BITS 32 403 404 #define cpu_init(cpu_model) cpu_generic_init(TYPE_M68K_CPU, cpu_model) 405 406 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 407 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 408 409 #define cpu_signal_handler cpu_m68k_signal_handler 410 #define cpu_list m68k_cpu_list 411 412 /* MMU modes definitions */ 413 #define MMU_MODE0_SUFFIX _kernel 414 #define MMU_MODE1_SUFFIX _user 415 #define MMU_USER_IDX 1 416 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 417 { 418 return (env->sr & SR_S) == 0 ? 1 : 0; 419 } 420 421 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 422 int mmu_idx); 423 424 #include "exec/cpu-all.h" 425 426 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 427 target_ulong *cs_base, uint32_t *flags) 428 { 429 *pc = env->pc; 430 *cs_base = 0; 431 *flags = (env->sr & SR_S) /* Bit 13 */ 432 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ 433 } 434 435 #endif 436