1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "exec/cpu-defs.h" 25 #include "exec/cpu-interrupt.h" 26 #include "qemu/cpu-float.h" 27 #include "cpu-qom.h" 28 29 #define OS_BYTE 0 30 #define OS_WORD 1 31 #define OS_LONG 2 32 #define OS_SINGLE 3 33 #define OS_DOUBLE 4 34 #define OS_EXTENDED 5 35 #define OS_PACKED 6 36 #define OS_UNSIZED 7 37 38 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 39 #define EXCP_ADDRESS 3 /* Address error. */ 40 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 41 #define EXCP_DIV0 5 /* Divide by zero */ 42 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 43 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 44 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 45 #define EXCP_TRACE 9 46 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 47 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 48 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 49 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 50 #define EXCP_FORMAT 14 /* RTE format error. */ 51 #define EXCP_UNINITIALIZED 15 52 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 53 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 54 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 55 #define EXCP_TRAP0 32 /* User trap #0. */ 56 #define EXCP_TRAP15 47 /* User trap #15. */ 57 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 58 #define EXCP_FP_INEX 49 /* Inexact result */ 59 #define EXCP_FP_DZ 50 /* Divide by Zero */ 60 #define EXCP_FP_UNFL 51 /* Underflow */ 61 #define EXCP_FP_OPERR 52 /* Operand Error */ 62 #define EXCP_FP_OVFL 53 /* Overflow */ 63 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 64 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 65 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 66 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 67 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 68 69 #define EXCP_RTE 0x100 70 #define EXCP_SEMIHOSTING 0x101 71 72 #define M68K_DTTR0 0 73 #define M68K_DTTR1 1 74 #define M68K_ITTR0 2 75 #define M68K_ITTR1 3 76 77 #define M68K_MAX_TTR 2 78 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 79 80 #define TARGET_INSN_START_EXTRA_WORDS 1 81 82 typedef CPU_LDoubleU FPReg; 83 84 typedef struct CPUArchState { 85 uint32_t dregs[8]; 86 uint32_t aregs[8]; 87 uint32_t pc; 88 uint32_t sr; 89 90 /* 91 * The 68020/30/40 support two supervisor stacks, ISP and MSP. 92 * The 68000/10, Coldfire, and CPU32 only have USP/SSP. 93 * 94 * The current_sp is stored in aregs[7], the other here. 95 * The USP, SSP, and if used the additional ISP for 68020/30/40. 96 */ 97 int current_sp; 98 uint32_t sp[3]; 99 100 /* Condition flags. */ 101 uint32_t cc_op; 102 uint32_t cc_x; /* always 0/1 */ 103 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 104 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 105 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 106 uint32_t cc_z; /* == 0 or unused */ 107 108 FPReg fregs[8]; 109 FPReg fp_result; 110 uint32_t fpcr; 111 uint32_t fpsr; 112 float_status fp_status; 113 114 uint64_t mactmp; 115 /* 116 * EMAC Hardware deals with 48-bit values composed of one 32-bit and 117 * two 8-bit parts. We store a single 64-bit value and 118 * rearrange/extend this when changing modes. 119 */ 120 uint64_t macc[4]; 121 uint32_t macsr; 122 uint32_t mac_mask; 123 124 /* MMU status. */ 125 struct { 126 /* 127 * Holds the "address" value in between raising an exception 128 * and creation of the exception stack frame. 129 * Used for both Format 7 exceptions (Access, i.e. mmu) 130 * and Format 2 exceptions (chk, div0, trapcc, etc). 131 */ 132 uint32_t ar; 133 uint32_t ssw; 134 /* 68040 */ 135 uint16_t tcr; 136 uint32_t urp; 137 uint32_t srp; 138 bool fault; 139 uint32_t ttr[4]; 140 uint32_t mmusr; 141 } mmu; 142 143 /* Control registers. */ 144 uint32_t vbr; 145 uint32_t mbar; 146 uint32_t rambar0; 147 uint32_t cacr; 148 uint32_t sfc; 149 uint32_t dfc; 150 151 int pending_vector; 152 int pending_level; 153 154 /* Fields up to this point are cleared by a CPU reset */ 155 struct {} end_reset_fields; 156 157 /* Fields from here on are preserved across CPU reset. */ 158 uint64_t features; 159 } CPUM68KState; 160 161 /* 162 * M68kCPU: 163 * @env: #CPUM68KState 164 * 165 * A Motorola 68k CPU. 166 */ 167 struct ArchCPU { 168 CPUState parent_obj; 169 170 CPUM68KState env; 171 }; 172 173 /* 174 * M68kCPUClass: 175 * @parent_realize: The parent class' realize handler. 176 * @parent_phases: The parent class' reset phase handlers. 177 * 178 * A Motorola 68k CPU model. 179 */ 180 struct M68kCPUClass { 181 CPUClass parent_class; 182 183 DeviceRealize parent_realize; 184 ResettablePhases parent_phases; 185 }; 186 187 #ifndef CONFIG_USER_ONLY 188 void m68k_cpu_do_interrupt(CPUState *cpu); 189 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 190 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 191 #endif /* !CONFIG_USER_ONLY */ 192 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 193 int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 194 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 195 196 void m68k_tcg_init(void); 197 void m68k_translate_code(CPUState *cs, TranslationBlock *tb, 198 int *max_insns, vaddr pc, void *host_pc); 199 void m68k_cpu_init_gdb(M68kCPU *cpu); 200 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 201 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 202 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 203 void cpu_m68k_restore_fp_status(CPUM68KState *env); 204 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 205 uint32_t cpu_m68k_get_fpsr(CPUM68KState *env); 206 void cpu_m68k_set_fpsr(CPUM68KState *env, uint32_t val); 207 208 /* 209 * Instead of computing the condition codes after each m68k instruction, 210 * QEMU just stores one operand (called CC_SRC), the result 211 * (called CC_DEST) and the type of operation (called CC_OP). When the 212 * condition codes are needed, the condition codes can be calculated 213 * using this information. Condition codes are not generated if they 214 * are only needed for conditional branches. 215 */ 216 typedef enum { 217 /* Translator only -- use env->cc_op. */ 218 CC_OP_DYNAMIC, 219 220 /* Each flag bit computed into cc_[xcnvz]. */ 221 CC_OP_FLAGS, 222 223 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 224 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 225 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 226 227 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 228 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 229 230 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 231 CC_OP_LOGIC, 232 233 CC_OP_NB 234 } CCOp; 235 236 #define CCF_C 0x01 237 #define CCF_V 0x02 238 #define CCF_Z 0x04 239 #define CCF_N 0x08 240 #define CCF_X 0x10 241 242 #define SR_I_SHIFT 8 243 #define SR_I 0x0700 244 #define SR_M 0x1000 245 #define SR_S 0x2000 246 #define SR_T_SHIFT 14 247 #define SR_T 0xc000 248 249 #define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT) 250 #define M68K_SR_TRACE_ANY_INS 0x2 251 252 #define M68K_SSP 0 253 #define M68K_USP 1 254 #define M68K_ISP 2 255 256 /* bits for 68040 special status word */ 257 #define M68K_CP_040 0x8000 258 #define M68K_CU_040 0x4000 259 #define M68K_CT_040 0x2000 260 #define M68K_CM_040 0x1000 261 #define M68K_MA_040 0x0800 262 #define M68K_ATC_040 0x0400 263 #define M68K_LK_040 0x0200 264 #define M68K_RW_040 0x0100 265 #define M68K_SIZ_040 0x0060 266 #define M68K_TT_040 0x0018 267 #define M68K_TM_040 0x0007 268 269 #define M68K_TM_040_DATA 0x0001 270 #define M68K_TM_040_CODE 0x0002 271 #define M68K_TM_040_SUPER 0x0004 272 273 /* bits for 68040 write back status word */ 274 #define M68K_WBV_040 0x80 275 #define M68K_WBSIZ_040 0x60 276 #define M68K_WBBYT_040 0x20 277 #define M68K_WBWRD_040 0x40 278 #define M68K_WBLNG_040 0x00 279 #define M68K_WBTT_040 0x18 280 #define M68K_WBTM_040 0x07 281 282 /* bus access size codes */ 283 #define M68K_BA_SIZE_MASK 0x60 284 #define M68K_BA_SIZE_BYTE 0x20 285 #define M68K_BA_SIZE_WORD 0x40 286 #define M68K_BA_SIZE_LONG 0x00 287 #define M68K_BA_SIZE_LINE 0x60 288 289 /* bus access transfer type codes */ 290 #define M68K_BA_TT_MOVE16 0x08 291 292 /* bits for 68040 MMU status register (mmusr) */ 293 #define M68K_MMU_B_040 0x0800 294 #define M68K_MMU_G_040 0x0400 295 #define M68K_MMU_U1_040 0x0200 296 #define M68K_MMU_U0_040 0x0100 297 #define M68K_MMU_S_040 0x0080 298 #define M68K_MMU_CM_040 0x0060 299 #define M68K_MMU_M_040 0x0010 300 #define M68K_MMU_WP_040 0x0004 301 #define M68K_MMU_T_040 0x0002 302 #define M68K_MMU_R_040 0x0001 303 304 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 305 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 306 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 307 M68K_MMU_WP_040) 308 309 /* bits for 68040 MMU Translation Control Register */ 310 #define M68K_TCR_ENABLED 0x8000 311 #define M68K_TCR_PAGE_8K 0x4000 312 313 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 314 #define M68K_DESC_WRITEPROT 0x00000004 315 #define M68K_DESC_USED 0x00000008 316 #define M68K_DESC_MODIFIED 0x00000010 317 #define M68K_DESC_CACHEMODE 0x00000060 318 #define M68K_DESC_CM_WRTHRU 0x00000000 319 #define M68K_DESC_CM_COPYBK 0x00000020 320 #define M68K_DESC_CM_SERIAL 0x00000040 321 #define M68K_DESC_CM_NCACHE 0x00000060 322 #define M68K_DESC_SUPERONLY 0x00000080 323 #define M68K_DESC_USERATTR 0x00000300 324 #define M68K_DESC_USERATTR_SHIFT 8 325 #define M68K_DESC_GLOBAL 0x00000400 326 #define M68K_DESC_URESERVED 0x00000800 327 328 #define M68K_ROOT_POINTER_ENTRIES 128 329 #define M68K_4K_PAGE_MASK (~0xff) 330 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 331 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 332 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 333 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 334 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 335 #define M68K_8K_PAGE_MASK (~0x7f) 336 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 337 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 338 #define M68K_UDT_VALID(entry) (entry & 2) 339 #define M68K_PDT_VALID(entry) (entry & 3) 340 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 341 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 342 #define M68K_TTS_POINTER_SHIFT 18 343 #define M68K_TTS_ROOT_SHIFT 25 344 345 /* bits for 68040 MMU Transparent Translation Registers */ 346 #define M68K_TTR_ADDR_BASE 0xff000000 347 #define M68K_TTR_ADDR_MASK 0x00ff0000 348 #define M68K_TTR_ADDR_MASK_SHIFT 8 349 #define M68K_TTR_ENABLED 0x00008000 350 #define M68K_TTR_SFIELD 0x00006000 351 #define M68K_TTR_SFIELD_USER 0x0000 352 #define M68K_TTR_SFIELD_SUPER 0x2000 353 354 /* m68k Control Registers */ 355 356 /* ColdFire */ 357 /* Memory Management Control Registers */ 358 #define M68K_CR_ASID 0x003 359 #define M68K_CR_ACR0 0x004 360 #define M68K_CR_ACR1 0x005 361 #define M68K_CR_ACR2 0x006 362 #define M68K_CR_ACR3 0x007 363 #define M68K_CR_MMUBAR 0x008 364 365 /* Processor Miscellaneous Registers */ 366 #define M68K_CR_PC 0x80F 367 368 /* Local Memory and Module Control Registers */ 369 #define M68K_CR_ROMBAR0 0xC00 370 #define M68K_CR_ROMBAR1 0xC01 371 #define M68K_CR_RAMBAR0 0xC04 372 #define M68K_CR_RAMBAR1 0xC05 373 #define M68K_CR_MPCR 0xC0C 374 #define M68K_CR_EDRAMBAR 0xC0D 375 #define M68K_CR_SECMBAR 0xC0E 376 #define M68K_CR_MBAR 0xC0F 377 378 /* Local Memory Address Permutation Control Registers */ 379 #define M68K_CR_PCR1U0 0xD02 380 #define M68K_CR_PCR1L0 0xD03 381 #define M68K_CR_PCR2U0 0xD04 382 #define M68K_CR_PCR2L0 0xD05 383 #define M68K_CR_PCR3U0 0xD06 384 #define M68K_CR_PCR3L0 0xD07 385 #define M68K_CR_PCR1U1 0xD0A 386 #define M68K_CR_PCR1L1 0xD0B 387 #define M68K_CR_PCR2U1 0xD0C 388 #define M68K_CR_PCR2L1 0xD0D 389 #define M68K_CR_PCR3U1 0xD0E 390 #define M68K_CR_PCR3L1 0xD0F 391 392 /* MC680x0 */ 393 /* MC680[1234]0/CPU32 */ 394 #define M68K_CR_SFC 0x000 395 #define M68K_CR_DFC 0x001 396 #define M68K_CR_USP 0x800 397 #define M68K_CR_VBR 0x801 /* + Coldfire */ 398 399 /* MC680[234]0 */ 400 #define M68K_CR_CACR 0x002 /* + Coldfire */ 401 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 402 #define M68K_CR_MSP 0x803 403 #define M68K_CR_ISP 0x804 404 405 /* MC68040/MC68LC040 */ 406 #define M68K_CR_TC 0x003 407 #define M68K_CR_ITT0 0x004 408 #define M68K_CR_ITT1 0x005 409 #define M68K_CR_DTT0 0x006 410 #define M68K_CR_DTT1 0x007 411 #define M68K_CR_MMUSR 0x805 412 #define M68K_CR_URP 0x806 413 #define M68K_CR_SRP 0x807 414 415 /* MC68EC040 */ 416 #define M68K_CR_IACR0 0x004 417 #define M68K_CR_IACR1 0x005 418 #define M68K_CR_DACR0 0x006 419 #define M68K_CR_DACR1 0x007 420 421 /* MC68060 */ 422 #define M68K_CR_BUSCR 0x008 423 #define M68K_CR_PCR 0x808 424 425 #define M68K_FPIAR_SHIFT 0 426 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 427 #define M68K_FPSR_SHIFT 1 428 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 429 #define M68K_FPCR_SHIFT 2 430 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 431 432 /* Floating-Point Status Register */ 433 434 /* Condition Code */ 435 #define FPSR_CC_MASK 0x0f000000 436 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 437 #define FPSR_CC_I 0x02000000 /* Infinity */ 438 #define FPSR_CC_Z 0x04000000 /* Zero */ 439 #define FPSR_CC_N 0x08000000 /* Negative */ 440 441 /* Quotient */ 442 443 #define FPSR_QT_MASK 0x00ff0000 444 #define FPSR_QT_SHIFT 16 445 446 /* Floating-Point Control Register */ 447 /* Rounding mode */ 448 #define FPCR_RND_MASK 0x0030 449 #define FPCR_RND_N 0x0000 450 #define FPCR_RND_Z 0x0010 451 #define FPCR_RND_M 0x0020 452 #define FPCR_RND_P 0x0030 453 454 /* Rounding precision */ 455 #define FPCR_PREC_MASK 0x00c0 456 #define FPCR_PREC_X 0x0000 457 #define FPCR_PREC_S 0x0040 458 #define FPCR_PREC_D 0x0080 459 #define FPCR_PREC_U 0x00c0 460 461 #define FPCR_EXCP_MASK 0xff00 462 463 /* CACR fields are implementation defined, but some bits are common. */ 464 #define M68K_CACR_EUSP 0x10 465 466 #define MACSR_PAV0 0x100 467 #define MACSR_OMC 0x080 468 #define MACSR_SU 0x040 469 #define MACSR_FI 0x020 470 #define MACSR_RT 0x010 471 #define MACSR_N 0x008 472 #define MACSR_Z 0x004 473 #define MACSR_V 0x002 474 #define MACSR_EV 0x001 475 476 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 477 void m68k_switch_sp(CPUM68KState *env); 478 479 void do_m68k_semihosting(CPUM68KState *env, int nr); 480 481 /* 482 * The 68000 family is defined in six main CPU classes, the 680[012346]0. 483 * Generally each successive CPU adds enhanced data/stack/instructions. 484 * However, some features are only common to one, or a few classes. 485 * The features cover those subsets of instructions. 486 * 487 * CPU32/32+ are basically 680010 compatible with some 68020 class 488 * instructions, and some additional CPU32 instructions. Mostly Supervisor 489 * state differences. 490 * 491 * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu. 492 * There are 4 ColdFire core ISA revisions: A, A+, B and C. 493 * Each feature covers the subset of instructions common to the 494 * ISA revisions mentioned. 495 */ 496 497 enum m68k_features { 498 /* Base Motorola CPU set (not set for Coldfire CPUs) */ 499 M68K_FEATURE_M68K, 500 /* Motorola CPU feature sets */ 501 M68K_FEATURE_M68010, 502 M68K_FEATURE_M68020, 503 M68K_FEATURE_M68030, 504 M68K_FEATURE_M68040, 505 M68K_FEATURE_M68060, 506 /* Base Coldfire set Rev A. */ 507 M68K_FEATURE_CF_ISA_A, 508 /* (ISA B or C). */ 509 M68K_FEATURE_CF_ISA_B, 510 /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 511 M68K_FEATURE_CF_ISA_APLUSC, 512 /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ 513 M68K_FEATURE_BRAL, 514 M68K_FEATURE_CF_FPU, 515 M68K_FEATURE_CF_MAC, 516 M68K_FEATURE_CF_EMAC, 517 /* Revision B EMAC (dual accumulate). */ 518 M68K_FEATURE_CF_EMAC_B, 519 /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ 520 M68K_FEATURE_USP, 521 /* Master Stack Pointer. (680[234]0) */ 522 M68K_FEATURE_MSP, 523 /* 68020+ full extension word. */ 524 M68K_FEATURE_EXT_FULL, 525 /* word sized address index registers. */ 526 M68K_FEATURE_WORD_INDEX, 527 /* scaled address index registers. */ 528 M68K_FEATURE_SCALED_INDEX, 529 /* 32 bit mul/div. (680[2346]0, and CPU32) */ 530 M68K_FEATURE_LONG_MULDIV, 531 /* 64 bit mul/div. (680[2346]0, and CPU32) */ 532 M68K_FEATURE_QUAD_MULDIV, 533 /* Bcc with Long branches. (680[2346]0, and CPU32) */ 534 M68K_FEATURE_BCCL, 535 /* BFxxx Bit field insns. (680[2346]0) */ 536 M68K_FEATURE_BITFIELD, 537 /* fpu insn. (680[46]0) */ 538 M68K_FEATURE_FPU, 539 /* CAS/CAS2[WL] insns. (680[2346]0) */ 540 M68K_FEATURE_CAS, 541 /* BKPT insn. (680[12346]0, and CPU32) */ 542 M68K_FEATURE_BKPT, 543 /* RTD insn. (680[12346]0, and CPU32) */ 544 M68K_FEATURE_RTD, 545 /* CHK2 insn. (680[2346]0, and CPU32) */ 546 M68K_FEATURE_CHK2, 547 /* MOVEP insn. (680[01234]0, and CPU32) */ 548 M68K_FEATURE_MOVEP, 549 /* MOVEC insn. (from 68010) */ 550 M68K_FEATURE_MOVEC, 551 /* Unaligned data accesses (680[2346]0) */ 552 M68K_FEATURE_UNALIGNED_DATA, 553 /* TRAPcc insn. (680[2346]0, and CPU32) */ 554 M68K_FEATURE_TRAPCC, 555 /* MOVE from SR privileged (from 68010) */ 556 M68K_FEATURE_MOVEFROMSR_PRIV, 557 /* Exception frame with format+vector (from 68010) */ 558 M68K_FEATURE_EXCEPTION_FORMAT_VEC, 559 }; 560 561 static inline bool m68k_feature(CPUM68KState *env, int feature) 562 { 563 return (env->features & BIT_ULL(feature)) != 0; 564 } 565 566 void register_m68k_insns (CPUM68KState *env); 567 568 enum { 569 /* 1 bit to define user level / supervisor access */ 570 ACCESS_SUPER = 0x01, 571 /* 1 bit to indicate direction */ 572 ACCESS_STORE = 0x02, 573 /* 1 bit to indicate debug access */ 574 ACCESS_DEBUG = 0x04, 575 /* PTEST instruction */ 576 ACCESS_PTEST = 0x08, 577 /* Type of instruction that generated the access */ 578 ACCESS_CODE = 0x10, /* Code fetch access */ 579 ACCESS_DATA = 0x20, /* Data load/store access */ 580 }; 581 582 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 583 584 /* MMU modes definitions */ 585 #define MMU_KERNEL_IDX 0 586 #define MMU_USER_IDX 1 587 588 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 589 MMUAccessType access_type, int mmu_idx, 590 bool probe, uintptr_t retaddr); 591 #ifndef CONFIG_USER_ONLY 592 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 593 unsigned size, MMUAccessType access_type, 594 int mmu_idx, MemTxAttrs attrs, 595 MemTxResult response, uintptr_t retaddr); 596 #endif 597 598 #include "exec/cpu-all.h" 599 600 /* TB flags */ 601 #define TB_FLAGS_MACSR 0x0f 602 #define TB_FLAGS_MSR_S_BIT 13 603 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 604 #define TB_FLAGS_SFC_S_BIT 14 605 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 606 #define TB_FLAGS_DFC_S_BIT 15 607 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 608 #define TB_FLAGS_TRACE 16 609 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) 610 611 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, 612 uint64_t *cs_base, uint32_t *flags) 613 { 614 *pc = env->pc; 615 *cs_base = 0; 616 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 617 if (env->sr & SR_S) { 618 *flags |= TB_FLAGS_MSR_S; 619 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 620 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 621 } 622 if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { 623 *flags |= TB_FLAGS_TRACE; 624 } 625 } 626 627 void dump_mmu(CPUM68KState *env); 628 629 #endif 630