1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "qemu-common.h" 25 #include "exec/cpu-defs.h" 26 #include "cpu-qom.h" 27 28 #define CPUArchState struct CPUM68KState 29 30 #define OS_BYTE 0 31 #define OS_WORD 1 32 #define OS_LONG 2 33 #define OS_SINGLE 3 34 #define OS_DOUBLE 4 35 #define OS_EXTENDED 5 36 #define OS_PACKED 6 37 #define OS_UNSIZED 7 38 39 #define MAX_QREGS 32 40 41 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 42 #define EXCP_ADDRESS 3 /* Address error. */ 43 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 44 #define EXCP_DIV0 5 /* Divide by zero */ 45 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 46 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 47 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 48 #define EXCP_TRACE 9 49 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 50 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 51 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 52 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 53 #define EXCP_FORMAT 14 /* RTE format error. */ 54 #define EXCP_UNINITIALIZED 15 55 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 56 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 57 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 58 #define EXCP_TRAP0 32 /* User trap #0. */ 59 #define EXCP_TRAP15 47 /* User trap #15. */ 60 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 61 #define EXCP_FP_INEX 49 /* Inexact result */ 62 #define EXCP_FP_DZ 50 /* Divide by Zero */ 63 #define EXCP_FP_UNFL 51 /* Underflow */ 64 #define EXCP_FP_OPERR 52 /* Operand Error */ 65 #define EXCP_FP_OVFL 53 /* Overflow */ 66 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 67 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 68 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 69 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 70 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 71 72 #define EXCP_RTE 0x100 73 #define EXCP_HALT_INSN 0x101 74 75 #define M68K_DTTR0 0 76 #define M68K_DTTR1 1 77 #define M68K_ITTR0 2 78 #define M68K_ITTR1 3 79 80 #define M68K_MAX_TTR 2 81 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 82 83 #define TARGET_INSN_START_EXTRA_WORDS 1 84 85 typedef CPU_LDoubleU FPReg; 86 87 typedef struct CPUM68KState { 88 uint32_t dregs[8]; 89 uint32_t aregs[8]; 90 uint32_t pc; 91 uint32_t sr; 92 93 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 94 int current_sp; 95 uint32_t sp[3]; 96 97 /* Condition flags. */ 98 uint32_t cc_op; 99 uint32_t cc_x; /* always 0/1 */ 100 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 101 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 102 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 103 uint32_t cc_z; /* == 0 or unused */ 104 105 FPReg fregs[8]; 106 FPReg fp_result; 107 uint32_t fpcr; 108 uint32_t fpsr; 109 float_status fp_status; 110 111 uint64_t mactmp; 112 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 113 two 8-bit parts. We store a single 64-bit value and 114 rearrange/extend this when changing modes. */ 115 uint64_t macc[4]; 116 uint32_t macsr; 117 uint32_t mac_mask; 118 119 /* MMU status. */ 120 struct { 121 uint32_t ar; 122 uint32_t ssw; 123 /* 68040 */ 124 uint16_t tcr; 125 uint32_t urp; 126 uint32_t srp; 127 bool fault; 128 uint32_t ttr[4]; 129 uint32_t mmusr; 130 } mmu; 131 132 /* Control registers. */ 133 uint32_t vbr; 134 uint32_t mbar; 135 uint32_t rambar0; 136 uint32_t cacr; 137 uint32_t sfc; 138 uint32_t dfc; 139 140 int pending_vector; 141 int pending_level; 142 143 uint32_t qregs[MAX_QREGS]; 144 145 /* Fields up to this point are cleared by a CPU reset */ 146 struct {} end_reset_fields; 147 148 CPU_COMMON 149 150 /* Fields from here on are preserved across CPU reset. */ 151 uint32_t features; 152 } CPUM68KState; 153 154 /** 155 * M68kCPU: 156 * @env: #CPUM68KState 157 * 158 * A Motorola 68k CPU. 159 */ 160 struct M68kCPU { 161 /*< private >*/ 162 CPUState parent_obj; 163 /*< public >*/ 164 165 CPUM68KState env; 166 }; 167 168 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) 169 { 170 return container_of(env, M68kCPU, env); 171 } 172 173 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) 174 175 #define ENV_OFFSET offsetof(M68kCPU, env) 176 177 void m68k_cpu_do_interrupt(CPUState *cpu); 178 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 179 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 180 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 181 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 182 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 183 184 void m68k_tcg_init(void); 185 void m68k_cpu_init_gdb(M68kCPU *cpu); 186 /* you can call this signal handler from your SIGBUS and SIGSEGV 187 signal handlers to inform the virtual CPU of exceptions. non zero 188 is returned if the signal was handled by the virtual CPU. */ 189 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 190 void *puc); 191 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 192 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 193 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 194 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 195 196 197 /* Instead of computing the condition codes after each m68k instruction, 198 * QEMU just stores one operand (called CC_SRC), the result 199 * (called CC_DEST) and the type of operation (called CC_OP). When the 200 * condition codes are needed, the condition codes can be calculated 201 * using this information. Condition codes are not generated if they 202 * are only needed for conditional branches. 203 */ 204 typedef enum { 205 /* Translator only -- use env->cc_op. */ 206 CC_OP_DYNAMIC, 207 208 /* Each flag bit computed into cc_[xcnvz]. */ 209 CC_OP_FLAGS, 210 211 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 212 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 213 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 214 215 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 216 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 217 218 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 219 CC_OP_LOGIC, 220 221 CC_OP_NB 222 } CCOp; 223 224 #define CCF_C 0x01 225 #define CCF_V 0x02 226 #define CCF_Z 0x04 227 #define CCF_N 0x08 228 #define CCF_X 0x10 229 230 #define SR_I_SHIFT 8 231 #define SR_I 0x0700 232 #define SR_M 0x1000 233 #define SR_S 0x2000 234 #define SR_T_SHIFT 14 235 #define SR_T 0xc000 236 237 #define M68K_SSP 0 238 #define M68K_USP 1 239 #define M68K_ISP 2 240 241 /* bits for 68040 special status word */ 242 #define M68K_CP_040 0x8000 243 #define M68K_CU_040 0x4000 244 #define M68K_CT_040 0x2000 245 #define M68K_CM_040 0x1000 246 #define M68K_MA_040 0x0800 247 #define M68K_ATC_040 0x0400 248 #define M68K_LK_040 0x0200 249 #define M68K_RW_040 0x0100 250 #define M68K_SIZ_040 0x0060 251 #define M68K_TT_040 0x0018 252 #define M68K_TM_040 0x0007 253 254 #define M68K_TM_040_DATA 0x0001 255 #define M68K_TM_040_CODE 0x0002 256 #define M68K_TM_040_SUPER 0x0004 257 258 /* bits for 68040 write back status word */ 259 #define M68K_WBV_040 0x80 260 #define M68K_WBSIZ_040 0x60 261 #define M68K_WBBYT_040 0x20 262 #define M68K_WBWRD_040 0x40 263 #define M68K_WBLNG_040 0x00 264 #define M68K_WBTT_040 0x18 265 #define M68K_WBTM_040 0x07 266 267 /* bus access size codes */ 268 #define M68K_BA_SIZE_MASK 0x60 269 #define M68K_BA_SIZE_BYTE 0x20 270 #define M68K_BA_SIZE_WORD 0x40 271 #define M68K_BA_SIZE_LONG 0x00 272 #define M68K_BA_SIZE_LINE 0x60 273 274 /* bus access transfer type codes */ 275 #define M68K_BA_TT_MOVE16 0x08 276 277 /* bits for 68040 MMU status register (mmusr) */ 278 #define M68K_MMU_B_040 0x0800 279 #define M68K_MMU_G_040 0x0400 280 #define M68K_MMU_U1_040 0x0200 281 #define M68K_MMU_U0_040 0x0100 282 #define M68K_MMU_S_040 0x0080 283 #define M68K_MMU_CM_040 0x0060 284 #define M68K_MMU_M_040 0x0010 285 #define M68K_MMU_WP_040 0x0004 286 #define M68K_MMU_T_040 0x0002 287 #define M68K_MMU_R_040 0x0001 288 289 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 290 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 291 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 292 M68K_MMU_WP_040) 293 294 /* bits for 68040 MMU Translation Control Register */ 295 #define M68K_TCR_ENABLED 0x8000 296 #define M68K_TCR_PAGE_8K 0x4000 297 298 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 299 #define M68K_DESC_WRITEPROT 0x00000004 300 #define M68K_DESC_USED 0x00000008 301 #define M68K_DESC_MODIFIED 0x00000010 302 #define M68K_DESC_CACHEMODE 0x00000060 303 #define M68K_DESC_CM_WRTHRU 0x00000000 304 #define M68K_DESC_CM_COPYBK 0x00000020 305 #define M68K_DESC_CM_SERIAL 0x00000040 306 #define M68K_DESC_CM_NCACHE 0x00000060 307 #define M68K_DESC_SUPERONLY 0x00000080 308 #define M68K_DESC_USERATTR 0x00000300 309 #define M68K_DESC_USERATTR_SHIFT 8 310 #define M68K_DESC_GLOBAL 0x00000400 311 #define M68K_DESC_URESERVED 0x00000800 312 313 #define M68K_ROOT_POINTER_ENTRIES 128 314 #define M68K_4K_PAGE_MASK (~0xff) 315 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 316 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 317 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 318 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 319 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 320 #define M68K_8K_PAGE_MASK (~0x7f) 321 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 322 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 323 #define M68K_UDT_VALID(entry) (entry & 2) 324 #define M68K_PDT_VALID(entry) (entry & 3) 325 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 326 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 327 #define M68K_TTS_POINTER_SHIFT 18 328 #define M68K_TTS_ROOT_SHIFT 25 329 330 /* bits for 68040 MMU Transparent Translation Registers */ 331 #define M68K_TTR_ADDR_BASE 0xff000000 332 #define M68K_TTR_ADDR_MASK 0x00ff0000 333 #define M68K_TTR_ADDR_MASK_SHIFT 8 334 #define M68K_TTR_ENABLED 0x00008000 335 #define M68K_TTR_SFIELD 0x00006000 336 #define M68K_TTR_SFIELD_USER 0x0000 337 #define M68K_TTR_SFIELD_SUPER 0x2000 338 339 /* m68k Control Registers */ 340 341 /* ColdFire */ 342 /* Memory Management Control Registers */ 343 #define M68K_CR_ASID 0x003 344 #define M68K_CR_ACR0 0x004 345 #define M68K_CR_ACR1 0x005 346 #define M68K_CR_ACR2 0x006 347 #define M68K_CR_ACR3 0x007 348 #define M68K_CR_MMUBAR 0x008 349 350 /* Processor Miscellaneous Registers */ 351 #define M68K_CR_PC 0x80F 352 353 /* Local Memory and Module Control Registers */ 354 #define M68K_CR_ROMBAR0 0xC00 355 #define M68K_CR_ROMBAR1 0xC01 356 #define M68K_CR_RAMBAR0 0xC04 357 #define M68K_CR_RAMBAR1 0xC05 358 #define M68K_CR_MPCR 0xC0C 359 #define M68K_CR_EDRAMBAR 0xC0D 360 #define M68K_CR_SECMBAR 0xC0E 361 #define M68K_CR_MBAR 0xC0F 362 363 /* Local Memory Address Permutation Control Registers */ 364 #define M68K_CR_PCR1U0 0xD02 365 #define M68K_CR_PCR1L0 0xD03 366 #define M68K_CR_PCR2U0 0xD04 367 #define M68K_CR_PCR2L0 0xD05 368 #define M68K_CR_PCR3U0 0xD06 369 #define M68K_CR_PCR3L0 0xD07 370 #define M68K_CR_PCR1U1 0xD0A 371 #define M68K_CR_PCR1L1 0xD0B 372 #define M68K_CR_PCR2U1 0xD0C 373 #define M68K_CR_PCR2L1 0xD0D 374 #define M68K_CR_PCR3U1 0xD0E 375 #define M68K_CR_PCR3L1 0xD0F 376 377 /* MC680x0 */ 378 /* MC680[1234]0/CPU32 */ 379 #define M68K_CR_SFC 0x000 380 #define M68K_CR_DFC 0x001 381 #define M68K_CR_USP 0x800 382 #define M68K_CR_VBR 0x801 /* + Coldfire */ 383 384 /* MC680[234]0 */ 385 #define M68K_CR_CACR 0x002 /* + Coldfire */ 386 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 387 #define M68K_CR_MSP 0x803 388 #define M68K_CR_ISP 0x804 389 390 /* MC68040/MC68LC040 */ 391 #define M68K_CR_TC 0x003 392 #define M68K_CR_ITT0 0x004 393 #define M68K_CR_ITT1 0x005 394 #define M68K_CR_DTT0 0x006 395 #define M68K_CR_DTT1 0x007 396 #define M68K_CR_MMUSR 0x805 397 #define M68K_CR_URP 0x806 398 #define M68K_CR_SRP 0x807 399 400 /* MC68EC040 */ 401 #define M68K_CR_IACR0 0x004 402 #define M68K_CR_IACR1 0x005 403 #define M68K_CR_DACR0 0x006 404 #define M68K_CR_DACR1 0x007 405 406 #define M68K_FPIAR_SHIFT 0 407 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 408 #define M68K_FPSR_SHIFT 1 409 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 410 #define M68K_FPCR_SHIFT 2 411 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 412 413 /* Floating-Point Status Register */ 414 415 /* Condition Code */ 416 #define FPSR_CC_MASK 0x0f000000 417 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 418 #define FPSR_CC_I 0x02000000 /* Infinity */ 419 #define FPSR_CC_Z 0x04000000 /* Zero */ 420 #define FPSR_CC_N 0x08000000 /* Negative */ 421 422 /* Quotient */ 423 424 #define FPSR_QT_MASK 0x00ff0000 425 #define FPSR_QT_SHIFT 16 426 427 /* Floating-Point Control Register */ 428 /* Rounding mode */ 429 #define FPCR_RND_MASK 0x0030 430 #define FPCR_RND_N 0x0000 431 #define FPCR_RND_Z 0x0010 432 #define FPCR_RND_M 0x0020 433 #define FPCR_RND_P 0x0030 434 435 /* Rounding precision */ 436 #define FPCR_PREC_MASK 0x00c0 437 #define FPCR_PREC_X 0x0000 438 #define FPCR_PREC_S 0x0040 439 #define FPCR_PREC_D 0x0080 440 #define FPCR_PREC_U 0x00c0 441 442 #define FPCR_EXCP_MASK 0xff00 443 444 /* CACR fields are implementation defined, but some bits are common. */ 445 #define M68K_CACR_EUSP 0x10 446 447 #define MACSR_PAV0 0x100 448 #define MACSR_OMC 0x080 449 #define MACSR_SU 0x040 450 #define MACSR_FI 0x020 451 #define MACSR_RT 0x010 452 #define MACSR_N 0x008 453 #define MACSR_Z 0x004 454 #define MACSR_V 0x002 455 #define MACSR_EV 0x001 456 457 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 458 void m68k_switch_sp(CPUM68KState *env); 459 460 void do_m68k_semihosting(CPUM68KState *env, int nr); 461 462 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 463 Each feature covers the subset of instructions common to the 464 ISA revisions mentioned. */ 465 466 enum m68k_features { 467 M68K_FEATURE_M68000, 468 M68K_FEATURE_CF_ISA_A, 469 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 470 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 471 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 472 M68K_FEATURE_CF_FPU, 473 M68K_FEATURE_CF_MAC, 474 M68K_FEATURE_CF_EMAC, 475 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 476 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 477 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 478 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 479 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 480 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 481 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 482 M68K_FEATURE_BCCL, /* Long conditional branches. */ 483 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 484 M68K_FEATURE_FPU, 485 M68K_FEATURE_CAS, 486 M68K_FEATURE_BKPT, 487 M68K_FEATURE_RTD, 488 M68K_FEATURE_CHK2, 489 M68K_FEATURE_M68040, /* instructions specific to MC68040 */ 490 M68K_FEATURE_MOVEP, 491 }; 492 493 static inline int m68k_feature(CPUM68KState *env, int feature) 494 { 495 return (env->features & (1u << feature)) != 0; 496 } 497 498 void m68k_cpu_list(void); 499 500 void register_m68k_insns (CPUM68KState *env); 501 502 enum { 503 /* 1 bit to define user level / supervisor access */ 504 ACCESS_SUPER = 0x01, 505 /* 1 bit to indicate direction */ 506 ACCESS_STORE = 0x02, 507 /* 1 bit to indicate debug access */ 508 ACCESS_DEBUG = 0x04, 509 /* PTEST instruction */ 510 ACCESS_PTEST = 0x08, 511 /* Type of instruction that generated the access */ 512 ACCESS_CODE = 0x10, /* Code fetch access */ 513 ACCESS_DATA = 0x20, /* Data load/store access */ 514 }; 515 516 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 517 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 518 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 519 520 #define cpu_signal_handler cpu_m68k_signal_handler 521 #define cpu_list m68k_cpu_list 522 523 /* MMU modes definitions */ 524 #define MMU_MODE0_SUFFIX _kernel 525 #define MMU_MODE1_SUFFIX _user 526 #define MMU_KERNEL_IDX 0 527 #define MMU_USER_IDX 1 528 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 529 { 530 return (env->sr & SR_S) == 0 ? 1 : 0; 531 } 532 533 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 534 MMUAccessType access_type, int mmu_idx, 535 bool probe, uintptr_t retaddr); 536 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 537 unsigned size, MMUAccessType access_type, 538 int mmu_idx, MemTxAttrs attrs, 539 MemTxResult response, uintptr_t retaddr); 540 541 #include "exec/cpu-all.h" 542 543 /* TB flags */ 544 #define TB_FLAGS_MACSR 0x0f 545 #define TB_FLAGS_MSR_S_BIT 13 546 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 547 #define TB_FLAGS_SFC_S_BIT 14 548 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 549 #define TB_FLAGS_DFC_S_BIT 15 550 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 551 552 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 553 target_ulong *cs_base, uint32_t *flags) 554 { 555 *pc = env->pc; 556 *cs_base = 0; 557 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 558 if (env->sr & SR_S) { 559 *flags |= TB_FLAGS_MSR_S; 560 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 561 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 562 } 563 } 564 565 void dump_mmu(CPUM68KState *env); 566 567 #endif 568