1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "qemu-common.h" 25 #include "exec/cpu-defs.h" 26 #include "cpu-qom.h" 27 28 #define OS_BYTE 0 29 #define OS_WORD 1 30 #define OS_LONG 2 31 #define OS_SINGLE 3 32 #define OS_DOUBLE 4 33 #define OS_EXTENDED 5 34 #define OS_PACKED 6 35 #define OS_UNSIZED 7 36 37 #define MAX_QREGS 32 38 39 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 40 #define EXCP_ADDRESS 3 /* Address error. */ 41 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 42 #define EXCP_DIV0 5 /* Divide by zero */ 43 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 44 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 45 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 46 #define EXCP_TRACE 9 47 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 48 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 49 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 50 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 51 #define EXCP_FORMAT 14 /* RTE format error. */ 52 #define EXCP_UNINITIALIZED 15 53 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 54 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 55 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 56 #define EXCP_TRAP0 32 /* User trap #0. */ 57 #define EXCP_TRAP15 47 /* User trap #15. */ 58 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 59 #define EXCP_FP_INEX 49 /* Inexact result */ 60 #define EXCP_FP_DZ 50 /* Divide by Zero */ 61 #define EXCP_FP_UNFL 51 /* Underflow */ 62 #define EXCP_FP_OPERR 52 /* Operand Error */ 63 #define EXCP_FP_OVFL 53 /* Overflow */ 64 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 65 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 66 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 67 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 68 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 69 70 #define EXCP_RTE 0x100 71 #define EXCP_HALT_INSN 0x101 72 73 #define M68K_DTTR0 0 74 #define M68K_DTTR1 1 75 #define M68K_ITTR0 2 76 #define M68K_ITTR1 3 77 78 #define M68K_MAX_TTR 2 79 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 80 81 #define TARGET_INSN_START_EXTRA_WORDS 1 82 83 typedef CPU_LDoubleU FPReg; 84 85 typedef struct CPUM68KState { 86 uint32_t dregs[8]; 87 uint32_t aregs[8]; 88 uint32_t pc; 89 uint32_t sr; 90 91 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 92 int current_sp; 93 uint32_t sp[3]; 94 95 /* Condition flags. */ 96 uint32_t cc_op; 97 uint32_t cc_x; /* always 0/1 */ 98 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 99 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 100 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 101 uint32_t cc_z; /* == 0 or unused */ 102 103 FPReg fregs[8]; 104 FPReg fp_result; 105 uint32_t fpcr; 106 uint32_t fpsr; 107 float_status fp_status; 108 109 uint64_t mactmp; 110 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 111 two 8-bit parts. We store a single 64-bit value and 112 rearrange/extend this when changing modes. */ 113 uint64_t macc[4]; 114 uint32_t macsr; 115 uint32_t mac_mask; 116 117 /* MMU status. */ 118 struct { 119 uint32_t ar; 120 uint32_t ssw; 121 /* 68040 */ 122 uint16_t tcr; 123 uint32_t urp; 124 uint32_t srp; 125 bool fault; 126 uint32_t ttr[4]; 127 uint32_t mmusr; 128 } mmu; 129 130 /* Control registers. */ 131 uint32_t vbr; 132 uint32_t mbar; 133 uint32_t rambar0; 134 uint32_t cacr; 135 uint32_t sfc; 136 uint32_t dfc; 137 138 int pending_vector; 139 int pending_level; 140 141 uint32_t qregs[MAX_QREGS]; 142 143 /* Fields up to this point are cleared by a CPU reset */ 144 struct {} end_reset_fields; 145 146 CPU_COMMON 147 148 /* Fields from here on are preserved across CPU reset. */ 149 uint32_t features; 150 } CPUM68KState; 151 152 /** 153 * M68kCPU: 154 * @env: #CPUM68KState 155 * 156 * A Motorola 68k CPU. 157 */ 158 struct M68kCPU { 159 /*< private >*/ 160 CPUState parent_obj; 161 /*< public >*/ 162 163 CPUNegativeOffsetState neg; 164 CPUM68KState env; 165 }; 166 167 168 void m68k_cpu_do_interrupt(CPUState *cpu); 169 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 170 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 171 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 172 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 173 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 174 175 void m68k_tcg_init(void); 176 void m68k_cpu_init_gdb(M68kCPU *cpu); 177 /* you can call this signal handler from your SIGBUS and SIGSEGV 178 signal handlers to inform the virtual CPU of exceptions. non zero 179 is returned if the signal was handled by the virtual CPU. */ 180 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 181 void *puc); 182 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 183 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 184 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 185 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 186 187 188 /* Instead of computing the condition codes after each m68k instruction, 189 * QEMU just stores one operand (called CC_SRC), the result 190 * (called CC_DEST) and the type of operation (called CC_OP). When the 191 * condition codes are needed, the condition codes can be calculated 192 * using this information. Condition codes are not generated if they 193 * are only needed for conditional branches. 194 */ 195 typedef enum { 196 /* Translator only -- use env->cc_op. */ 197 CC_OP_DYNAMIC, 198 199 /* Each flag bit computed into cc_[xcnvz]. */ 200 CC_OP_FLAGS, 201 202 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 203 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 204 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 205 206 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 207 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 208 209 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 210 CC_OP_LOGIC, 211 212 CC_OP_NB 213 } CCOp; 214 215 #define CCF_C 0x01 216 #define CCF_V 0x02 217 #define CCF_Z 0x04 218 #define CCF_N 0x08 219 #define CCF_X 0x10 220 221 #define SR_I_SHIFT 8 222 #define SR_I 0x0700 223 #define SR_M 0x1000 224 #define SR_S 0x2000 225 #define SR_T_SHIFT 14 226 #define SR_T 0xc000 227 228 #define M68K_SSP 0 229 #define M68K_USP 1 230 #define M68K_ISP 2 231 232 /* bits for 68040 special status word */ 233 #define M68K_CP_040 0x8000 234 #define M68K_CU_040 0x4000 235 #define M68K_CT_040 0x2000 236 #define M68K_CM_040 0x1000 237 #define M68K_MA_040 0x0800 238 #define M68K_ATC_040 0x0400 239 #define M68K_LK_040 0x0200 240 #define M68K_RW_040 0x0100 241 #define M68K_SIZ_040 0x0060 242 #define M68K_TT_040 0x0018 243 #define M68K_TM_040 0x0007 244 245 #define M68K_TM_040_DATA 0x0001 246 #define M68K_TM_040_CODE 0x0002 247 #define M68K_TM_040_SUPER 0x0004 248 249 /* bits for 68040 write back status word */ 250 #define M68K_WBV_040 0x80 251 #define M68K_WBSIZ_040 0x60 252 #define M68K_WBBYT_040 0x20 253 #define M68K_WBWRD_040 0x40 254 #define M68K_WBLNG_040 0x00 255 #define M68K_WBTT_040 0x18 256 #define M68K_WBTM_040 0x07 257 258 /* bus access size codes */ 259 #define M68K_BA_SIZE_MASK 0x60 260 #define M68K_BA_SIZE_BYTE 0x20 261 #define M68K_BA_SIZE_WORD 0x40 262 #define M68K_BA_SIZE_LONG 0x00 263 #define M68K_BA_SIZE_LINE 0x60 264 265 /* bus access transfer type codes */ 266 #define M68K_BA_TT_MOVE16 0x08 267 268 /* bits for 68040 MMU status register (mmusr) */ 269 #define M68K_MMU_B_040 0x0800 270 #define M68K_MMU_G_040 0x0400 271 #define M68K_MMU_U1_040 0x0200 272 #define M68K_MMU_U0_040 0x0100 273 #define M68K_MMU_S_040 0x0080 274 #define M68K_MMU_CM_040 0x0060 275 #define M68K_MMU_M_040 0x0010 276 #define M68K_MMU_WP_040 0x0004 277 #define M68K_MMU_T_040 0x0002 278 #define M68K_MMU_R_040 0x0001 279 280 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 281 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 282 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 283 M68K_MMU_WP_040) 284 285 /* bits for 68040 MMU Translation Control Register */ 286 #define M68K_TCR_ENABLED 0x8000 287 #define M68K_TCR_PAGE_8K 0x4000 288 289 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 290 #define M68K_DESC_WRITEPROT 0x00000004 291 #define M68K_DESC_USED 0x00000008 292 #define M68K_DESC_MODIFIED 0x00000010 293 #define M68K_DESC_CACHEMODE 0x00000060 294 #define M68K_DESC_CM_WRTHRU 0x00000000 295 #define M68K_DESC_CM_COPYBK 0x00000020 296 #define M68K_DESC_CM_SERIAL 0x00000040 297 #define M68K_DESC_CM_NCACHE 0x00000060 298 #define M68K_DESC_SUPERONLY 0x00000080 299 #define M68K_DESC_USERATTR 0x00000300 300 #define M68K_DESC_USERATTR_SHIFT 8 301 #define M68K_DESC_GLOBAL 0x00000400 302 #define M68K_DESC_URESERVED 0x00000800 303 304 #define M68K_ROOT_POINTER_ENTRIES 128 305 #define M68K_4K_PAGE_MASK (~0xff) 306 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 307 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 308 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 309 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 310 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 311 #define M68K_8K_PAGE_MASK (~0x7f) 312 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 313 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 314 #define M68K_UDT_VALID(entry) (entry & 2) 315 #define M68K_PDT_VALID(entry) (entry & 3) 316 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 317 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 318 #define M68K_TTS_POINTER_SHIFT 18 319 #define M68K_TTS_ROOT_SHIFT 25 320 321 /* bits for 68040 MMU Transparent Translation Registers */ 322 #define M68K_TTR_ADDR_BASE 0xff000000 323 #define M68K_TTR_ADDR_MASK 0x00ff0000 324 #define M68K_TTR_ADDR_MASK_SHIFT 8 325 #define M68K_TTR_ENABLED 0x00008000 326 #define M68K_TTR_SFIELD 0x00006000 327 #define M68K_TTR_SFIELD_USER 0x0000 328 #define M68K_TTR_SFIELD_SUPER 0x2000 329 330 /* m68k Control Registers */ 331 332 /* ColdFire */ 333 /* Memory Management Control Registers */ 334 #define M68K_CR_ASID 0x003 335 #define M68K_CR_ACR0 0x004 336 #define M68K_CR_ACR1 0x005 337 #define M68K_CR_ACR2 0x006 338 #define M68K_CR_ACR3 0x007 339 #define M68K_CR_MMUBAR 0x008 340 341 /* Processor Miscellaneous Registers */ 342 #define M68K_CR_PC 0x80F 343 344 /* Local Memory and Module Control Registers */ 345 #define M68K_CR_ROMBAR0 0xC00 346 #define M68K_CR_ROMBAR1 0xC01 347 #define M68K_CR_RAMBAR0 0xC04 348 #define M68K_CR_RAMBAR1 0xC05 349 #define M68K_CR_MPCR 0xC0C 350 #define M68K_CR_EDRAMBAR 0xC0D 351 #define M68K_CR_SECMBAR 0xC0E 352 #define M68K_CR_MBAR 0xC0F 353 354 /* Local Memory Address Permutation Control Registers */ 355 #define M68K_CR_PCR1U0 0xD02 356 #define M68K_CR_PCR1L0 0xD03 357 #define M68K_CR_PCR2U0 0xD04 358 #define M68K_CR_PCR2L0 0xD05 359 #define M68K_CR_PCR3U0 0xD06 360 #define M68K_CR_PCR3L0 0xD07 361 #define M68K_CR_PCR1U1 0xD0A 362 #define M68K_CR_PCR1L1 0xD0B 363 #define M68K_CR_PCR2U1 0xD0C 364 #define M68K_CR_PCR2L1 0xD0D 365 #define M68K_CR_PCR3U1 0xD0E 366 #define M68K_CR_PCR3L1 0xD0F 367 368 /* MC680x0 */ 369 /* MC680[1234]0/CPU32 */ 370 #define M68K_CR_SFC 0x000 371 #define M68K_CR_DFC 0x001 372 #define M68K_CR_USP 0x800 373 #define M68K_CR_VBR 0x801 /* + Coldfire */ 374 375 /* MC680[234]0 */ 376 #define M68K_CR_CACR 0x002 /* + Coldfire */ 377 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 378 #define M68K_CR_MSP 0x803 379 #define M68K_CR_ISP 0x804 380 381 /* MC68040/MC68LC040 */ 382 #define M68K_CR_TC 0x003 383 #define M68K_CR_ITT0 0x004 384 #define M68K_CR_ITT1 0x005 385 #define M68K_CR_DTT0 0x006 386 #define M68K_CR_DTT1 0x007 387 #define M68K_CR_MMUSR 0x805 388 #define M68K_CR_URP 0x806 389 #define M68K_CR_SRP 0x807 390 391 /* MC68EC040 */ 392 #define M68K_CR_IACR0 0x004 393 #define M68K_CR_IACR1 0x005 394 #define M68K_CR_DACR0 0x006 395 #define M68K_CR_DACR1 0x007 396 397 #define M68K_FPIAR_SHIFT 0 398 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 399 #define M68K_FPSR_SHIFT 1 400 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 401 #define M68K_FPCR_SHIFT 2 402 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 403 404 /* Floating-Point Status Register */ 405 406 /* Condition Code */ 407 #define FPSR_CC_MASK 0x0f000000 408 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 409 #define FPSR_CC_I 0x02000000 /* Infinity */ 410 #define FPSR_CC_Z 0x04000000 /* Zero */ 411 #define FPSR_CC_N 0x08000000 /* Negative */ 412 413 /* Quotient */ 414 415 #define FPSR_QT_MASK 0x00ff0000 416 #define FPSR_QT_SHIFT 16 417 418 /* Floating-Point Control Register */ 419 /* Rounding mode */ 420 #define FPCR_RND_MASK 0x0030 421 #define FPCR_RND_N 0x0000 422 #define FPCR_RND_Z 0x0010 423 #define FPCR_RND_M 0x0020 424 #define FPCR_RND_P 0x0030 425 426 /* Rounding precision */ 427 #define FPCR_PREC_MASK 0x00c0 428 #define FPCR_PREC_X 0x0000 429 #define FPCR_PREC_S 0x0040 430 #define FPCR_PREC_D 0x0080 431 #define FPCR_PREC_U 0x00c0 432 433 #define FPCR_EXCP_MASK 0xff00 434 435 /* CACR fields are implementation defined, but some bits are common. */ 436 #define M68K_CACR_EUSP 0x10 437 438 #define MACSR_PAV0 0x100 439 #define MACSR_OMC 0x080 440 #define MACSR_SU 0x040 441 #define MACSR_FI 0x020 442 #define MACSR_RT 0x010 443 #define MACSR_N 0x008 444 #define MACSR_Z 0x004 445 #define MACSR_V 0x002 446 #define MACSR_EV 0x001 447 448 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 449 void m68k_switch_sp(CPUM68KState *env); 450 451 void do_m68k_semihosting(CPUM68KState *env, int nr); 452 453 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 454 Each feature covers the subset of instructions common to the 455 ISA revisions mentioned. */ 456 457 enum m68k_features { 458 M68K_FEATURE_M68000, 459 M68K_FEATURE_CF_ISA_A, 460 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 461 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 462 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 463 M68K_FEATURE_CF_FPU, 464 M68K_FEATURE_CF_MAC, 465 M68K_FEATURE_CF_EMAC, 466 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 467 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 468 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 469 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 470 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 471 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 472 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 473 M68K_FEATURE_BCCL, /* Long conditional branches. */ 474 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 475 M68K_FEATURE_FPU, 476 M68K_FEATURE_CAS, 477 M68K_FEATURE_BKPT, 478 M68K_FEATURE_RTD, 479 M68K_FEATURE_CHK2, 480 M68K_FEATURE_M68040, /* instructions specific to MC68040 */ 481 M68K_FEATURE_MOVEP, 482 }; 483 484 static inline int m68k_feature(CPUM68KState *env, int feature) 485 { 486 return (env->features & (1u << feature)) != 0; 487 } 488 489 void m68k_cpu_list(void); 490 491 void register_m68k_insns (CPUM68KState *env); 492 493 enum { 494 /* 1 bit to define user level / supervisor access */ 495 ACCESS_SUPER = 0x01, 496 /* 1 bit to indicate direction */ 497 ACCESS_STORE = 0x02, 498 /* 1 bit to indicate debug access */ 499 ACCESS_DEBUG = 0x04, 500 /* PTEST instruction */ 501 ACCESS_PTEST = 0x08, 502 /* Type of instruction that generated the access */ 503 ACCESS_CODE = 0x10, /* Code fetch access */ 504 ACCESS_DATA = 0x20, /* Data load/store access */ 505 }; 506 507 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 508 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 509 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 510 511 #define cpu_signal_handler cpu_m68k_signal_handler 512 #define cpu_list m68k_cpu_list 513 514 /* MMU modes definitions */ 515 #define MMU_MODE0_SUFFIX _kernel 516 #define MMU_MODE1_SUFFIX _user 517 #define MMU_KERNEL_IDX 0 518 #define MMU_USER_IDX 1 519 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 520 { 521 return (env->sr & SR_S) == 0 ? 1 : 0; 522 } 523 524 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 525 MMUAccessType access_type, int mmu_idx, 526 bool probe, uintptr_t retaddr); 527 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 528 unsigned size, MMUAccessType access_type, 529 int mmu_idx, MemTxAttrs attrs, 530 MemTxResult response, uintptr_t retaddr); 531 532 typedef CPUM68KState CPUArchState; 533 typedef M68kCPU ArchCPU; 534 535 #include "exec/cpu-all.h" 536 537 /* TB flags */ 538 #define TB_FLAGS_MACSR 0x0f 539 #define TB_FLAGS_MSR_S_BIT 13 540 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 541 #define TB_FLAGS_SFC_S_BIT 14 542 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 543 #define TB_FLAGS_DFC_S_BIT 15 544 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 545 546 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 547 target_ulong *cs_base, uint32_t *flags) 548 { 549 *pc = env->pc; 550 *cs_base = 0; 551 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 552 if (env->sr & SR_S) { 553 *flags |= TB_FLAGS_MSR_S; 554 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 555 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 556 } 557 } 558 559 void dump_mmu(CPUM68KState *env); 560 561 #endif 562