1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "exec/cpu-defs.h" 25 #include "cpu-qom.h" 26 27 #define OS_BYTE 0 28 #define OS_WORD 1 29 #define OS_LONG 2 30 #define OS_SINGLE 3 31 #define OS_DOUBLE 4 32 #define OS_EXTENDED 5 33 #define OS_PACKED 6 34 #define OS_UNSIZED 7 35 36 #define MAX_QREGS 32 37 38 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 39 #define EXCP_ADDRESS 3 /* Address error. */ 40 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 41 #define EXCP_DIV0 5 /* Divide by zero */ 42 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 43 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 44 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 45 #define EXCP_TRACE 9 46 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 47 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 48 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 49 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 50 #define EXCP_FORMAT 14 /* RTE format error. */ 51 #define EXCP_UNINITIALIZED 15 52 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 53 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 54 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 55 #define EXCP_TRAP0 32 /* User trap #0. */ 56 #define EXCP_TRAP15 47 /* User trap #15. */ 57 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 58 #define EXCP_FP_INEX 49 /* Inexact result */ 59 #define EXCP_FP_DZ 50 /* Divide by Zero */ 60 #define EXCP_FP_UNFL 51 /* Underflow */ 61 #define EXCP_FP_OPERR 52 /* Operand Error */ 62 #define EXCP_FP_OVFL 53 /* Overflow */ 63 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 64 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 65 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 66 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 67 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 68 69 #define EXCP_RTE 0x100 70 #define EXCP_HALT_INSN 0x101 71 72 #define M68K_DTTR0 0 73 #define M68K_DTTR1 1 74 #define M68K_ITTR0 2 75 #define M68K_ITTR1 3 76 77 #define M68K_MAX_TTR 2 78 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 79 80 #define TARGET_INSN_START_EXTRA_WORDS 1 81 82 typedef CPU_LDoubleU FPReg; 83 84 typedef struct CPUM68KState { 85 uint32_t dregs[8]; 86 uint32_t aregs[8]; 87 uint32_t pc; 88 uint32_t sr; 89 90 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 91 int current_sp; 92 uint32_t sp[3]; 93 94 /* Condition flags. */ 95 uint32_t cc_op; 96 uint32_t cc_x; /* always 0/1 */ 97 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 98 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 99 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 100 uint32_t cc_z; /* == 0 or unused */ 101 102 FPReg fregs[8]; 103 FPReg fp_result; 104 uint32_t fpcr; 105 uint32_t fpsr; 106 float_status fp_status; 107 108 uint64_t mactmp; 109 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 110 two 8-bit parts. We store a single 64-bit value and 111 rearrange/extend this when changing modes. */ 112 uint64_t macc[4]; 113 uint32_t macsr; 114 uint32_t mac_mask; 115 116 /* MMU status. */ 117 struct { 118 uint32_t ar; 119 uint32_t ssw; 120 /* 68040 */ 121 uint16_t tcr; 122 uint32_t urp; 123 uint32_t srp; 124 bool fault; 125 uint32_t ttr[4]; 126 uint32_t mmusr; 127 } mmu; 128 129 /* Control registers. */ 130 uint32_t vbr; 131 uint32_t mbar; 132 uint32_t rambar0; 133 uint32_t cacr; 134 uint32_t sfc; 135 uint32_t dfc; 136 137 int pending_vector; 138 int pending_level; 139 140 uint32_t qregs[MAX_QREGS]; 141 142 /* Fields up to this point are cleared by a CPU reset */ 143 struct {} end_reset_fields; 144 145 /* Fields from here on are preserved across CPU reset. */ 146 uint32_t features; 147 } CPUM68KState; 148 149 /** 150 * M68kCPU: 151 * @env: #CPUM68KState 152 * 153 * A Motorola 68k CPU. 154 */ 155 struct M68kCPU { 156 /*< private >*/ 157 CPUState parent_obj; 158 /*< public >*/ 159 160 CPUNegativeOffsetState neg; 161 CPUM68KState env; 162 }; 163 164 165 void m68k_cpu_do_interrupt(CPUState *cpu); 166 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 167 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 168 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 169 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 170 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 171 172 void m68k_tcg_init(void); 173 void m68k_cpu_init_gdb(M68kCPU *cpu); 174 /* you can call this signal handler from your SIGBUS and SIGSEGV 175 signal handlers to inform the virtual CPU of exceptions. non zero 176 is returned if the signal was handled by the virtual CPU. */ 177 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 178 void *puc); 179 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 180 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 181 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 182 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 183 184 185 /* Instead of computing the condition codes after each m68k instruction, 186 * QEMU just stores one operand (called CC_SRC), the result 187 * (called CC_DEST) and the type of operation (called CC_OP). When the 188 * condition codes are needed, the condition codes can be calculated 189 * using this information. Condition codes are not generated if they 190 * are only needed for conditional branches. 191 */ 192 typedef enum { 193 /* Translator only -- use env->cc_op. */ 194 CC_OP_DYNAMIC, 195 196 /* Each flag bit computed into cc_[xcnvz]. */ 197 CC_OP_FLAGS, 198 199 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 200 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 201 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 202 203 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 204 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 205 206 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 207 CC_OP_LOGIC, 208 209 CC_OP_NB 210 } CCOp; 211 212 #define CCF_C 0x01 213 #define CCF_V 0x02 214 #define CCF_Z 0x04 215 #define CCF_N 0x08 216 #define CCF_X 0x10 217 218 #define SR_I_SHIFT 8 219 #define SR_I 0x0700 220 #define SR_M 0x1000 221 #define SR_S 0x2000 222 #define SR_T_SHIFT 14 223 #define SR_T 0xc000 224 225 #define M68K_SSP 0 226 #define M68K_USP 1 227 #define M68K_ISP 2 228 229 /* bits for 68040 special status word */ 230 #define M68K_CP_040 0x8000 231 #define M68K_CU_040 0x4000 232 #define M68K_CT_040 0x2000 233 #define M68K_CM_040 0x1000 234 #define M68K_MA_040 0x0800 235 #define M68K_ATC_040 0x0400 236 #define M68K_LK_040 0x0200 237 #define M68K_RW_040 0x0100 238 #define M68K_SIZ_040 0x0060 239 #define M68K_TT_040 0x0018 240 #define M68K_TM_040 0x0007 241 242 #define M68K_TM_040_DATA 0x0001 243 #define M68K_TM_040_CODE 0x0002 244 #define M68K_TM_040_SUPER 0x0004 245 246 /* bits for 68040 write back status word */ 247 #define M68K_WBV_040 0x80 248 #define M68K_WBSIZ_040 0x60 249 #define M68K_WBBYT_040 0x20 250 #define M68K_WBWRD_040 0x40 251 #define M68K_WBLNG_040 0x00 252 #define M68K_WBTT_040 0x18 253 #define M68K_WBTM_040 0x07 254 255 /* bus access size codes */ 256 #define M68K_BA_SIZE_MASK 0x60 257 #define M68K_BA_SIZE_BYTE 0x20 258 #define M68K_BA_SIZE_WORD 0x40 259 #define M68K_BA_SIZE_LONG 0x00 260 #define M68K_BA_SIZE_LINE 0x60 261 262 /* bus access transfer type codes */ 263 #define M68K_BA_TT_MOVE16 0x08 264 265 /* bits for 68040 MMU status register (mmusr) */ 266 #define M68K_MMU_B_040 0x0800 267 #define M68K_MMU_G_040 0x0400 268 #define M68K_MMU_U1_040 0x0200 269 #define M68K_MMU_U0_040 0x0100 270 #define M68K_MMU_S_040 0x0080 271 #define M68K_MMU_CM_040 0x0060 272 #define M68K_MMU_M_040 0x0010 273 #define M68K_MMU_WP_040 0x0004 274 #define M68K_MMU_T_040 0x0002 275 #define M68K_MMU_R_040 0x0001 276 277 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 278 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 279 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 280 M68K_MMU_WP_040) 281 282 /* bits for 68040 MMU Translation Control Register */ 283 #define M68K_TCR_ENABLED 0x8000 284 #define M68K_TCR_PAGE_8K 0x4000 285 286 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 287 #define M68K_DESC_WRITEPROT 0x00000004 288 #define M68K_DESC_USED 0x00000008 289 #define M68K_DESC_MODIFIED 0x00000010 290 #define M68K_DESC_CACHEMODE 0x00000060 291 #define M68K_DESC_CM_WRTHRU 0x00000000 292 #define M68K_DESC_CM_COPYBK 0x00000020 293 #define M68K_DESC_CM_SERIAL 0x00000040 294 #define M68K_DESC_CM_NCACHE 0x00000060 295 #define M68K_DESC_SUPERONLY 0x00000080 296 #define M68K_DESC_USERATTR 0x00000300 297 #define M68K_DESC_USERATTR_SHIFT 8 298 #define M68K_DESC_GLOBAL 0x00000400 299 #define M68K_DESC_URESERVED 0x00000800 300 301 #define M68K_ROOT_POINTER_ENTRIES 128 302 #define M68K_4K_PAGE_MASK (~0xff) 303 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 304 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 305 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 306 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 307 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 308 #define M68K_8K_PAGE_MASK (~0x7f) 309 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 310 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 311 #define M68K_UDT_VALID(entry) (entry & 2) 312 #define M68K_PDT_VALID(entry) (entry & 3) 313 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 314 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 315 #define M68K_TTS_POINTER_SHIFT 18 316 #define M68K_TTS_ROOT_SHIFT 25 317 318 /* bits for 68040 MMU Transparent Translation Registers */ 319 #define M68K_TTR_ADDR_BASE 0xff000000 320 #define M68K_TTR_ADDR_MASK 0x00ff0000 321 #define M68K_TTR_ADDR_MASK_SHIFT 8 322 #define M68K_TTR_ENABLED 0x00008000 323 #define M68K_TTR_SFIELD 0x00006000 324 #define M68K_TTR_SFIELD_USER 0x0000 325 #define M68K_TTR_SFIELD_SUPER 0x2000 326 327 /* m68k Control Registers */ 328 329 /* ColdFire */ 330 /* Memory Management Control Registers */ 331 #define M68K_CR_ASID 0x003 332 #define M68K_CR_ACR0 0x004 333 #define M68K_CR_ACR1 0x005 334 #define M68K_CR_ACR2 0x006 335 #define M68K_CR_ACR3 0x007 336 #define M68K_CR_MMUBAR 0x008 337 338 /* Processor Miscellaneous Registers */ 339 #define M68K_CR_PC 0x80F 340 341 /* Local Memory and Module Control Registers */ 342 #define M68K_CR_ROMBAR0 0xC00 343 #define M68K_CR_ROMBAR1 0xC01 344 #define M68K_CR_RAMBAR0 0xC04 345 #define M68K_CR_RAMBAR1 0xC05 346 #define M68K_CR_MPCR 0xC0C 347 #define M68K_CR_EDRAMBAR 0xC0D 348 #define M68K_CR_SECMBAR 0xC0E 349 #define M68K_CR_MBAR 0xC0F 350 351 /* Local Memory Address Permutation Control Registers */ 352 #define M68K_CR_PCR1U0 0xD02 353 #define M68K_CR_PCR1L0 0xD03 354 #define M68K_CR_PCR2U0 0xD04 355 #define M68K_CR_PCR2L0 0xD05 356 #define M68K_CR_PCR3U0 0xD06 357 #define M68K_CR_PCR3L0 0xD07 358 #define M68K_CR_PCR1U1 0xD0A 359 #define M68K_CR_PCR1L1 0xD0B 360 #define M68K_CR_PCR2U1 0xD0C 361 #define M68K_CR_PCR2L1 0xD0D 362 #define M68K_CR_PCR3U1 0xD0E 363 #define M68K_CR_PCR3L1 0xD0F 364 365 /* MC680x0 */ 366 /* MC680[1234]0/CPU32 */ 367 #define M68K_CR_SFC 0x000 368 #define M68K_CR_DFC 0x001 369 #define M68K_CR_USP 0x800 370 #define M68K_CR_VBR 0x801 /* + Coldfire */ 371 372 /* MC680[234]0 */ 373 #define M68K_CR_CACR 0x002 /* + Coldfire */ 374 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 375 #define M68K_CR_MSP 0x803 376 #define M68K_CR_ISP 0x804 377 378 /* MC68040/MC68LC040 */ 379 #define M68K_CR_TC 0x003 380 #define M68K_CR_ITT0 0x004 381 #define M68K_CR_ITT1 0x005 382 #define M68K_CR_DTT0 0x006 383 #define M68K_CR_DTT1 0x007 384 #define M68K_CR_MMUSR 0x805 385 #define M68K_CR_URP 0x806 386 #define M68K_CR_SRP 0x807 387 388 /* MC68EC040 */ 389 #define M68K_CR_IACR0 0x004 390 #define M68K_CR_IACR1 0x005 391 #define M68K_CR_DACR0 0x006 392 #define M68K_CR_DACR1 0x007 393 394 #define M68K_FPIAR_SHIFT 0 395 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 396 #define M68K_FPSR_SHIFT 1 397 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 398 #define M68K_FPCR_SHIFT 2 399 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 400 401 /* Floating-Point Status Register */ 402 403 /* Condition Code */ 404 #define FPSR_CC_MASK 0x0f000000 405 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 406 #define FPSR_CC_I 0x02000000 /* Infinity */ 407 #define FPSR_CC_Z 0x04000000 /* Zero */ 408 #define FPSR_CC_N 0x08000000 /* Negative */ 409 410 /* Quotient */ 411 412 #define FPSR_QT_MASK 0x00ff0000 413 #define FPSR_QT_SHIFT 16 414 415 /* Floating-Point Control Register */ 416 /* Rounding mode */ 417 #define FPCR_RND_MASK 0x0030 418 #define FPCR_RND_N 0x0000 419 #define FPCR_RND_Z 0x0010 420 #define FPCR_RND_M 0x0020 421 #define FPCR_RND_P 0x0030 422 423 /* Rounding precision */ 424 #define FPCR_PREC_MASK 0x00c0 425 #define FPCR_PREC_X 0x0000 426 #define FPCR_PREC_S 0x0040 427 #define FPCR_PREC_D 0x0080 428 #define FPCR_PREC_U 0x00c0 429 430 #define FPCR_EXCP_MASK 0xff00 431 432 /* CACR fields are implementation defined, but some bits are common. */ 433 #define M68K_CACR_EUSP 0x10 434 435 #define MACSR_PAV0 0x100 436 #define MACSR_OMC 0x080 437 #define MACSR_SU 0x040 438 #define MACSR_FI 0x020 439 #define MACSR_RT 0x010 440 #define MACSR_N 0x008 441 #define MACSR_Z 0x004 442 #define MACSR_V 0x002 443 #define MACSR_EV 0x001 444 445 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 446 void m68k_switch_sp(CPUM68KState *env); 447 448 void do_m68k_semihosting(CPUM68KState *env, int nr); 449 450 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 451 Each feature covers the subset of instructions common to the 452 ISA revisions mentioned. */ 453 454 enum m68k_features { 455 M68K_FEATURE_M68000, 456 M68K_FEATURE_CF_ISA_A, 457 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 458 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 459 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 460 M68K_FEATURE_CF_FPU, 461 M68K_FEATURE_CF_MAC, 462 M68K_FEATURE_CF_EMAC, 463 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 464 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 465 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 466 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 467 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 468 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 469 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 470 M68K_FEATURE_BCCL, /* Long conditional branches. */ 471 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 472 M68K_FEATURE_FPU, 473 M68K_FEATURE_CAS, 474 M68K_FEATURE_BKPT, 475 M68K_FEATURE_RTD, 476 M68K_FEATURE_CHK2, 477 M68K_FEATURE_M68040, /* instructions specific to MC68040 */ 478 M68K_FEATURE_MOVEP, 479 }; 480 481 static inline int m68k_feature(CPUM68KState *env, int feature) 482 { 483 return (env->features & (1u << feature)) != 0; 484 } 485 486 void m68k_cpu_list(void); 487 488 void register_m68k_insns (CPUM68KState *env); 489 490 enum { 491 /* 1 bit to define user level / supervisor access */ 492 ACCESS_SUPER = 0x01, 493 /* 1 bit to indicate direction */ 494 ACCESS_STORE = 0x02, 495 /* 1 bit to indicate debug access */ 496 ACCESS_DEBUG = 0x04, 497 /* PTEST instruction */ 498 ACCESS_PTEST = 0x08, 499 /* Type of instruction that generated the access */ 500 ACCESS_CODE = 0x10, /* Code fetch access */ 501 ACCESS_DATA = 0x20, /* Data load/store access */ 502 }; 503 504 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 505 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 506 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 507 508 #define cpu_signal_handler cpu_m68k_signal_handler 509 #define cpu_list m68k_cpu_list 510 511 /* MMU modes definitions */ 512 #define MMU_MODE0_SUFFIX _kernel 513 #define MMU_MODE1_SUFFIX _user 514 #define MMU_KERNEL_IDX 0 515 #define MMU_USER_IDX 1 516 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 517 { 518 return (env->sr & SR_S) == 0 ? 1 : 0; 519 } 520 521 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 522 MMUAccessType access_type, int mmu_idx, 523 bool probe, uintptr_t retaddr); 524 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 525 unsigned size, MMUAccessType access_type, 526 int mmu_idx, MemTxAttrs attrs, 527 MemTxResult response, uintptr_t retaddr); 528 529 typedef CPUM68KState CPUArchState; 530 typedef M68kCPU ArchCPU; 531 532 #include "exec/cpu-all.h" 533 534 /* TB flags */ 535 #define TB_FLAGS_MACSR 0x0f 536 #define TB_FLAGS_MSR_S_BIT 13 537 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 538 #define TB_FLAGS_SFC_S_BIT 14 539 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 540 #define TB_FLAGS_DFC_S_BIT 15 541 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 542 543 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 544 target_ulong *cs_base, uint32_t *flags) 545 { 546 *pc = env->pc; 547 *cs_base = 0; 548 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 549 if (env->sr & SR_S) { 550 *flags |= TB_FLAGS_MSR_S; 551 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 552 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 553 } 554 } 555 556 void dump_mmu(CPUM68KState *env); 557 558 #endif 559