1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "qemu-common.h" 25 #include "exec/cpu-defs.h" 26 #include "cpu-qom.h" 27 28 #define OS_BYTE 0 29 #define OS_WORD 1 30 #define OS_LONG 2 31 #define OS_SINGLE 3 32 #define OS_DOUBLE 4 33 #define OS_EXTENDED 5 34 #define OS_PACKED 6 35 #define OS_UNSIZED 7 36 37 #define MAX_QREGS 32 38 39 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 40 #define EXCP_ADDRESS 3 /* Address error. */ 41 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 42 #define EXCP_DIV0 5 /* Divide by zero */ 43 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 44 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 45 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 46 #define EXCP_TRACE 9 47 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 48 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 49 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 50 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 51 #define EXCP_FORMAT 14 /* RTE format error. */ 52 #define EXCP_UNINITIALIZED 15 53 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 54 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 55 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 56 #define EXCP_TRAP0 32 /* User trap #0. */ 57 #define EXCP_TRAP15 47 /* User trap #15. */ 58 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 59 #define EXCP_FP_INEX 49 /* Inexact result */ 60 #define EXCP_FP_DZ 50 /* Divide by Zero */ 61 #define EXCP_FP_UNFL 51 /* Underflow */ 62 #define EXCP_FP_OPERR 52 /* Operand Error */ 63 #define EXCP_FP_OVFL 53 /* Overflow */ 64 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 65 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 66 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 67 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 68 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 69 70 #define EXCP_RTE 0x100 71 #define EXCP_HALT_INSN 0x101 72 73 #define M68K_DTTR0 0 74 #define M68K_DTTR1 1 75 #define M68K_ITTR0 2 76 #define M68K_ITTR1 3 77 78 #define M68K_MAX_TTR 2 79 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 80 81 #define TARGET_INSN_START_EXTRA_WORDS 1 82 83 typedef CPU_LDoubleU FPReg; 84 85 typedef struct CPUM68KState { 86 uint32_t dregs[8]; 87 uint32_t aregs[8]; 88 uint32_t pc; 89 uint32_t sr; 90 91 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 92 int current_sp; 93 uint32_t sp[3]; 94 95 /* Condition flags. */ 96 uint32_t cc_op; 97 uint32_t cc_x; /* always 0/1 */ 98 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 99 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 100 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 101 uint32_t cc_z; /* == 0 or unused */ 102 103 FPReg fregs[8]; 104 FPReg fp_result; 105 uint32_t fpcr; 106 uint32_t fpsr; 107 float_status fp_status; 108 109 uint64_t mactmp; 110 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 111 two 8-bit parts. We store a single 64-bit value and 112 rearrange/extend this when changing modes. */ 113 uint64_t macc[4]; 114 uint32_t macsr; 115 uint32_t mac_mask; 116 117 /* MMU status. */ 118 struct { 119 uint32_t ar; 120 uint32_t ssw; 121 /* 68040 */ 122 uint16_t tcr; 123 uint32_t urp; 124 uint32_t srp; 125 bool fault; 126 uint32_t ttr[4]; 127 uint32_t mmusr; 128 } mmu; 129 130 /* Control registers. */ 131 uint32_t vbr; 132 uint32_t mbar; 133 uint32_t rambar0; 134 uint32_t cacr; 135 uint32_t sfc; 136 uint32_t dfc; 137 138 int pending_vector; 139 int pending_level; 140 141 uint32_t qregs[MAX_QREGS]; 142 143 /* Fields up to this point are cleared by a CPU reset */ 144 struct {} end_reset_fields; 145 146 CPU_COMMON 147 148 /* Fields from here on are preserved across CPU reset. */ 149 uint32_t features; 150 } CPUM68KState; 151 152 /** 153 * M68kCPU: 154 * @env: #CPUM68KState 155 * 156 * A Motorola 68k CPU. 157 */ 158 struct M68kCPU { 159 /*< private >*/ 160 CPUState parent_obj; 161 /*< public >*/ 162 163 CPUM68KState env; 164 }; 165 166 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) 167 { 168 return container_of(env, M68kCPU, env); 169 } 170 171 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) 172 173 #define ENV_OFFSET offsetof(M68kCPU, env) 174 175 void m68k_cpu_do_interrupt(CPUState *cpu); 176 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 177 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 178 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 179 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 180 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 181 182 void m68k_tcg_init(void); 183 void m68k_cpu_init_gdb(M68kCPU *cpu); 184 /* you can call this signal handler from your SIGBUS and SIGSEGV 185 signal handlers to inform the virtual CPU of exceptions. non zero 186 is returned if the signal was handled by the virtual CPU. */ 187 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 188 void *puc); 189 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 190 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 191 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 192 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 193 194 195 /* Instead of computing the condition codes after each m68k instruction, 196 * QEMU just stores one operand (called CC_SRC), the result 197 * (called CC_DEST) and the type of operation (called CC_OP). When the 198 * condition codes are needed, the condition codes can be calculated 199 * using this information. Condition codes are not generated if they 200 * are only needed for conditional branches. 201 */ 202 typedef enum { 203 /* Translator only -- use env->cc_op. */ 204 CC_OP_DYNAMIC, 205 206 /* Each flag bit computed into cc_[xcnvz]. */ 207 CC_OP_FLAGS, 208 209 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 210 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 211 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 212 213 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 214 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 215 216 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 217 CC_OP_LOGIC, 218 219 CC_OP_NB 220 } CCOp; 221 222 #define CCF_C 0x01 223 #define CCF_V 0x02 224 #define CCF_Z 0x04 225 #define CCF_N 0x08 226 #define CCF_X 0x10 227 228 #define SR_I_SHIFT 8 229 #define SR_I 0x0700 230 #define SR_M 0x1000 231 #define SR_S 0x2000 232 #define SR_T_SHIFT 14 233 #define SR_T 0xc000 234 235 #define M68K_SSP 0 236 #define M68K_USP 1 237 #define M68K_ISP 2 238 239 /* bits for 68040 special status word */ 240 #define M68K_CP_040 0x8000 241 #define M68K_CU_040 0x4000 242 #define M68K_CT_040 0x2000 243 #define M68K_CM_040 0x1000 244 #define M68K_MA_040 0x0800 245 #define M68K_ATC_040 0x0400 246 #define M68K_LK_040 0x0200 247 #define M68K_RW_040 0x0100 248 #define M68K_SIZ_040 0x0060 249 #define M68K_TT_040 0x0018 250 #define M68K_TM_040 0x0007 251 252 #define M68K_TM_040_DATA 0x0001 253 #define M68K_TM_040_CODE 0x0002 254 #define M68K_TM_040_SUPER 0x0004 255 256 /* bits for 68040 write back status word */ 257 #define M68K_WBV_040 0x80 258 #define M68K_WBSIZ_040 0x60 259 #define M68K_WBBYT_040 0x20 260 #define M68K_WBWRD_040 0x40 261 #define M68K_WBLNG_040 0x00 262 #define M68K_WBTT_040 0x18 263 #define M68K_WBTM_040 0x07 264 265 /* bus access size codes */ 266 #define M68K_BA_SIZE_MASK 0x60 267 #define M68K_BA_SIZE_BYTE 0x20 268 #define M68K_BA_SIZE_WORD 0x40 269 #define M68K_BA_SIZE_LONG 0x00 270 #define M68K_BA_SIZE_LINE 0x60 271 272 /* bus access transfer type codes */ 273 #define M68K_BA_TT_MOVE16 0x08 274 275 /* bits for 68040 MMU status register (mmusr) */ 276 #define M68K_MMU_B_040 0x0800 277 #define M68K_MMU_G_040 0x0400 278 #define M68K_MMU_U1_040 0x0200 279 #define M68K_MMU_U0_040 0x0100 280 #define M68K_MMU_S_040 0x0080 281 #define M68K_MMU_CM_040 0x0060 282 #define M68K_MMU_M_040 0x0010 283 #define M68K_MMU_WP_040 0x0004 284 #define M68K_MMU_T_040 0x0002 285 #define M68K_MMU_R_040 0x0001 286 287 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 288 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 289 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 290 M68K_MMU_WP_040) 291 292 /* bits for 68040 MMU Translation Control Register */ 293 #define M68K_TCR_ENABLED 0x8000 294 #define M68K_TCR_PAGE_8K 0x4000 295 296 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 297 #define M68K_DESC_WRITEPROT 0x00000004 298 #define M68K_DESC_USED 0x00000008 299 #define M68K_DESC_MODIFIED 0x00000010 300 #define M68K_DESC_CACHEMODE 0x00000060 301 #define M68K_DESC_CM_WRTHRU 0x00000000 302 #define M68K_DESC_CM_COPYBK 0x00000020 303 #define M68K_DESC_CM_SERIAL 0x00000040 304 #define M68K_DESC_CM_NCACHE 0x00000060 305 #define M68K_DESC_SUPERONLY 0x00000080 306 #define M68K_DESC_USERATTR 0x00000300 307 #define M68K_DESC_USERATTR_SHIFT 8 308 #define M68K_DESC_GLOBAL 0x00000400 309 #define M68K_DESC_URESERVED 0x00000800 310 311 #define M68K_ROOT_POINTER_ENTRIES 128 312 #define M68K_4K_PAGE_MASK (~0xff) 313 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 314 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 315 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 316 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 317 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 318 #define M68K_8K_PAGE_MASK (~0x7f) 319 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 320 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 321 #define M68K_UDT_VALID(entry) (entry & 2) 322 #define M68K_PDT_VALID(entry) (entry & 3) 323 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 324 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 325 #define M68K_TTS_POINTER_SHIFT 18 326 #define M68K_TTS_ROOT_SHIFT 25 327 328 /* bits for 68040 MMU Transparent Translation Registers */ 329 #define M68K_TTR_ADDR_BASE 0xff000000 330 #define M68K_TTR_ADDR_MASK 0x00ff0000 331 #define M68K_TTR_ADDR_MASK_SHIFT 8 332 #define M68K_TTR_ENABLED 0x00008000 333 #define M68K_TTR_SFIELD 0x00006000 334 #define M68K_TTR_SFIELD_USER 0x0000 335 #define M68K_TTR_SFIELD_SUPER 0x2000 336 337 /* m68k Control Registers */ 338 339 /* ColdFire */ 340 /* Memory Management Control Registers */ 341 #define M68K_CR_ASID 0x003 342 #define M68K_CR_ACR0 0x004 343 #define M68K_CR_ACR1 0x005 344 #define M68K_CR_ACR2 0x006 345 #define M68K_CR_ACR3 0x007 346 #define M68K_CR_MMUBAR 0x008 347 348 /* Processor Miscellaneous Registers */ 349 #define M68K_CR_PC 0x80F 350 351 /* Local Memory and Module Control Registers */ 352 #define M68K_CR_ROMBAR0 0xC00 353 #define M68K_CR_ROMBAR1 0xC01 354 #define M68K_CR_RAMBAR0 0xC04 355 #define M68K_CR_RAMBAR1 0xC05 356 #define M68K_CR_MPCR 0xC0C 357 #define M68K_CR_EDRAMBAR 0xC0D 358 #define M68K_CR_SECMBAR 0xC0E 359 #define M68K_CR_MBAR 0xC0F 360 361 /* Local Memory Address Permutation Control Registers */ 362 #define M68K_CR_PCR1U0 0xD02 363 #define M68K_CR_PCR1L0 0xD03 364 #define M68K_CR_PCR2U0 0xD04 365 #define M68K_CR_PCR2L0 0xD05 366 #define M68K_CR_PCR3U0 0xD06 367 #define M68K_CR_PCR3L0 0xD07 368 #define M68K_CR_PCR1U1 0xD0A 369 #define M68K_CR_PCR1L1 0xD0B 370 #define M68K_CR_PCR2U1 0xD0C 371 #define M68K_CR_PCR2L1 0xD0D 372 #define M68K_CR_PCR3U1 0xD0E 373 #define M68K_CR_PCR3L1 0xD0F 374 375 /* MC680x0 */ 376 /* MC680[1234]0/CPU32 */ 377 #define M68K_CR_SFC 0x000 378 #define M68K_CR_DFC 0x001 379 #define M68K_CR_USP 0x800 380 #define M68K_CR_VBR 0x801 /* + Coldfire */ 381 382 /* MC680[234]0 */ 383 #define M68K_CR_CACR 0x002 /* + Coldfire */ 384 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 385 #define M68K_CR_MSP 0x803 386 #define M68K_CR_ISP 0x804 387 388 /* MC68040/MC68LC040 */ 389 #define M68K_CR_TC 0x003 390 #define M68K_CR_ITT0 0x004 391 #define M68K_CR_ITT1 0x005 392 #define M68K_CR_DTT0 0x006 393 #define M68K_CR_DTT1 0x007 394 #define M68K_CR_MMUSR 0x805 395 #define M68K_CR_URP 0x806 396 #define M68K_CR_SRP 0x807 397 398 /* MC68EC040 */ 399 #define M68K_CR_IACR0 0x004 400 #define M68K_CR_IACR1 0x005 401 #define M68K_CR_DACR0 0x006 402 #define M68K_CR_DACR1 0x007 403 404 #define M68K_FPIAR_SHIFT 0 405 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 406 #define M68K_FPSR_SHIFT 1 407 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 408 #define M68K_FPCR_SHIFT 2 409 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 410 411 /* Floating-Point Status Register */ 412 413 /* Condition Code */ 414 #define FPSR_CC_MASK 0x0f000000 415 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 416 #define FPSR_CC_I 0x02000000 /* Infinity */ 417 #define FPSR_CC_Z 0x04000000 /* Zero */ 418 #define FPSR_CC_N 0x08000000 /* Negative */ 419 420 /* Quotient */ 421 422 #define FPSR_QT_MASK 0x00ff0000 423 #define FPSR_QT_SHIFT 16 424 425 /* Floating-Point Control Register */ 426 /* Rounding mode */ 427 #define FPCR_RND_MASK 0x0030 428 #define FPCR_RND_N 0x0000 429 #define FPCR_RND_Z 0x0010 430 #define FPCR_RND_M 0x0020 431 #define FPCR_RND_P 0x0030 432 433 /* Rounding precision */ 434 #define FPCR_PREC_MASK 0x00c0 435 #define FPCR_PREC_X 0x0000 436 #define FPCR_PREC_S 0x0040 437 #define FPCR_PREC_D 0x0080 438 #define FPCR_PREC_U 0x00c0 439 440 #define FPCR_EXCP_MASK 0xff00 441 442 /* CACR fields are implementation defined, but some bits are common. */ 443 #define M68K_CACR_EUSP 0x10 444 445 #define MACSR_PAV0 0x100 446 #define MACSR_OMC 0x080 447 #define MACSR_SU 0x040 448 #define MACSR_FI 0x020 449 #define MACSR_RT 0x010 450 #define MACSR_N 0x008 451 #define MACSR_Z 0x004 452 #define MACSR_V 0x002 453 #define MACSR_EV 0x001 454 455 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 456 void m68k_switch_sp(CPUM68KState *env); 457 458 void do_m68k_semihosting(CPUM68KState *env, int nr); 459 460 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 461 Each feature covers the subset of instructions common to the 462 ISA revisions mentioned. */ 463 464 enum m68k_features { 465 M68K_FEATURE_M68000, 466 M68K_FEATURE_CF_ISA_A, 467 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 468 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 469 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 470 M68K_FEATURE_CF_FPU, 471 M68K_FEATURE_CF_MAC, 472 M68K_FEATURE_CF_EMAC, 473 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 474 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 475 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 476 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 477 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 478 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 479 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 480 M68K_FEATURE_BCCL, /* Long conditional branches. */ 481 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 482 M68K_FEATURE_FPU, 483 M68K_FEATURE_CAS, 484 M68K_FEATURE_BKPT, 485 M68K_FEATURE_RTD, 486 M68K_FEATURE_CHK2, 487 M68K_FEATURE_M68040, /* instructions specific to MC68040 */ 488 M68K_FEATURE_MOVEP, 489 }; 490 491 static inline int m68k_feature(CPUM68KState *env, int feature) 492 { 493 return (env->features & (1u << feature)) != 0; 494 } 495 496 void m68k_cpu_list(void); 497 498 void register_m68k_insns (CPUM68KState *env); 499 500 enum { 501 /* 1 bit to define user level / supervisor access */ 502 ACCESS_SUPER = 0x01, 503 /* 1 bit to indicate direction */ 504 ACCESS_STORE = 0x02, 505 /* 1 bit to indicate debug access */ 506 ACCESS_DEBUG = 0x04, 507 /* PTEST instruction */ 508 ACCESS_PTEST = 0x08, 509 /* Type of instruction that generated the access */ 510 ACCESS_CODE = 0x10, /* Code fetch access */ 511 ACCESS_DATA = 0x20, /* Data load/store access */ 512 }; 513 514 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 515 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 516 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 517 518 #define cpu_signal_handler cpu_m68k_signal_handler 519 #define cpu_list m68k_cpu_list 520 521 /* MMU modes definitions */ 522 #define MMU_MODE0_SUFFIX _kernel 523 #define MMU_MODE1_SUFFIX _user 524 #define MMU_KERNEL_IDX 0 525 #define MMU_USER_IDX 1 526 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 527 { 528 return (env->sr & SR_S) == 0 ? 1 : 0; 529 } 530 531 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 532 MMUAccessType access_type, int mmu_idx, 533 bool probe, uintptr_t retaddr); 534 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 535 unsigned size, MMUAccessType access_type, 536 int mmu_idx, MemTxAttrs attrs, 537 MemTxResult response, uintptr_t retaddr); 538 539 typedef CPUM68KState CPUArchState; 540 541 #include "exec/cpu-all.h" 542 543 /* TB flags */ 544 #define TB_FLAGS_MACSR 0x0f 545 #define TB_FLAGS_MSR_S_BIT 13 546 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 547 #define TB_FLAGS_SFC_S_BIT 14 548 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 549 #define TB_FLAGS_DFC_S_BIT 15 550 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 551 552 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 553 target_ulong *cs_base, uint32_t *flags) 554 { 555 *pc = env->pc; 556 *cs_base = 0; 557 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 558 if (env->sr & SR_S) { 559 *flags |= TB_FLAGS_MSR_S; 560 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 561 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 562 } 563 } 564 565 void dump_mmu(CPUM68KState *env); 566 567 #endif 568