1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "exec/cpu-defs.h" 25 #include "cpu-qom.h" 26 27 #define OS_BYTE 0 28 #define OS_WORD 1 29 #define OS_LONG 2 30 #define OS_SINGLE 3 31 #define OS_DOUBLE 4 32 #define OS_EXTENDED 5 33 #define OS_PACKED 6 34 #define OS_UNSIZED 7 35 36 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 37 #define EXCP_ADDRESS 3 /* Address error. */ 38 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 39 #define EXCP_DIV0 5 /* Divide by zero */ 40 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 41 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 42 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 43 #define EXCP_TRACE 9 44 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 45 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 46 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 47 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 48 #define EXCP_FORMAT 14 /* RTE format error. */ 49 #define EXCP_UNINITIALIZED 15 50 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 51 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 52 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 53 #define EXCP_TRAP0 32 /* User trap #0. */ 54 #define EXCP_TRAP15 47 /* User trap #15. */ 55 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 56 #define EXCP_FP_INEX 49 /* Inexact result */ 57 #define EXCP_FP_DZ 50 /* Divide by Zero */ 58 #define EXCP_FP_UNFL 51 /* Underflow */ 59 #define EXCP_FP_OPERR 52 /* Operand Error */ 60 #define EXCP_FP_OVFL 53 /* Overflow */ 61 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 62 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 63 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 64 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 65 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 66 67 #define EXCP_RTE 0x100 68 #define EXCP_HALT_INSN 0x101 69 70 #define M68K_DTTR0 0 71 #define M68K_DTTR1 1 72 #define M68K_ITTR0 2 73 #define M68K_ITTR1 3 74 75 #define M68K_MAX_TTR 2 76 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 77 78 #define TARGET_INSN_START_EXTRA_WORDS 1 79 80 typedef CPU_LDoubleU FPReg; 81 82 typedef struct CPUM68KState { 83 uint32_t dregs[8]; 84 uint32_t aregs[8]; 85 uint32_t pc; 86 uint32_t sr; 87 88 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 89 int current_sp; 90 uint32_t sp[3]; 91 92 /* Condition flags. */ 93 uint32_t cc_op; 94 uint32_t cc_x; /* always 0/1 */ 95 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 96 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 97 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 98 uint32_t cc_z; /* == 0 or unused */ 99 100 FPReg fregs[8]; 101 FPReg fp_result; 102 uint32_t fpcr; 103 uint32_t fpsr; 104 float_status fp_status; 105 106 uint64_t mactmp; 107 /* 108 * EMAC Hardware deals with 48-bit values composed of one 32-bit and 109 * two 8-bit parts. We store a single 64-bit value and 110 * rearrange/extend this when changing modes. 111 */ 112 uint64_t macc[4]; 113 uint32_t macsr; 114 uint32_t mac_mask; 115 116 /* MMU status. */ 117 struct { 118 uint32_t ar; 119 uint32_t ssw; 120 /* 68040 */ 121 uint16_t tcr; 122 uint32_t urp; 123 uint32_t srp; 124 bool fault; 125 uint32_t ttr[4]; 126 uint32_t mmusr; 127 } mmu; 128 129 /* Control registers. */ 130 uint32_t vbr; 131 uint32_t mbar; 132 uint32_t rambar0; 133 uint32_t cacr; 134 uint32_t sfc; 135 uint32_t dfc; 136 137 int pending_vector; 138 int pending_level; 139 140 /* Fields up to this point are cleared by a CPU reset */ 141 struct {} end_reset_fields; 142 143 /* Fields from here on are preserved across CPU reset. */ 144 uint32_t features; 145 } CPUM68KState; 146 147 /* 148 * M68kCPU: 149 * @env: #CPUM68KState 150 * 151 * A Motorola 68k CPU. 152 */ 153 struct M68kCPU { 154 /*< private >*/ 155 CPUState parent_obj; 156 /*< public >*/ 157 158 CPUNegativeOffsetState neg; 159 CPUM68KState env; 160 }; 161 162 163 void m68k_cpu_do_interrupt(CPUState *cpu); 164 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 165 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 166 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 167 int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 168 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 169 170 void m68k_tcg_init(void); 171 void m68k_cpu_init_gdb(M68kCPU *cpu); 172 /* 173 * you can call this signal handler from your SIGBUS and SIGSEGV 174 * signal handlers to inform the virtual CPU of exceptions. non zero 175 * is returned if the signal was handled by the virtual CPU. 176 */ 177 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 178 void *puc); 179 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 180 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 181 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 182 void cpu_m68k_restore_fp_status(CPUM68KState *env); 183 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 184 185 186 /* 187 * Instead of computing the condition codes after each m68k instruction, 188 * QEMU just stores one operand (called CC_SRC), the result 189 * (called CC_DEST) and the type of operation (called CC_OP). When the 190 * condition codes are needed, the condition codes can be calculated 191 * using this information. Condition codes are not generated if they 192 * are only needed for conditional branches. 193 */ 194 typedef enum { 195 /* Translator only -- use env->cc_op. */ 196 CC_OP_DYNAMIC, 197 198 /* Each flag bit computed into cc_[xcnvz]. */ 199 CC_OP_FLAGS, 200 201 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 202 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 203 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 204 205 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 206 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 207 208 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 209 CC_OP_LOGIC, 210 211 CC_OP_NB 212 } CCOp; 213 214 #define CCF_C 0x01 215 #define CCF_V 0x02 216 #define CCF_Z 0x04 217 #define CCF_N 0x08 218 #define CCF_X 0x10 219 220 #define SR_I_SHIFT 8 221 #define SR_I 0x0700 222 #define SR_M 0x1000 223 #define SR_S 0x2000 224 #define SR_T_SHIFT 14 225 #define SR_T 0xc000 226 227 #define M68K_SSP 0 228 #define M68K_USP 1 229 #define M68K_ISP 2 230 231 /* bits for 68040 special status word */ 232 #define M68K_CP_040 0x8000 233 #define M68K_CU_040 0x4000 234 #define M68K_CT_040 0x2000 235 #define M68K_CM_040 0x1000 236 #define M68K_MA_040 0x0800 237 #define M68K_ATC_040 0x0400 238 #define M68K_LK_040 0x0200 239 #define M68K_RW_040 0x0100 240 #define M68K_SIZ_040 0x0060 241 #define M68K_TT_040 0x0018 242 #define M68K_TM_040 0x0007 243 244 #define M68K_TM_040_DATA 0x0001 245 #define M68K_TM_040_CODE 0x0002 246 #define M68K_TM_040_SUPER 0x0004 247 248 /* bits for 68040 write back status word */ 249 #define M68K_WBV_040 0x80 250 #define M68K_WBSIZ_040 0x60 251 #define M68K_WBBYT_040 0x20 252 #define M68K_WBWRD_040 0x40 253 #define M68K_WBLNG_040 0x00 254 #define M68K_WBTT_040 0x18 255 #define M68K_WBTM_040 0x07 256 257 /* bus access size codes */ 258 #define M68K_BA_SIZE_MASK 0x60 259 #define M68K_BA_SIZE_BYTE 0x20 260 #define M68K_BA_SIZE_WORD 0x40 261 #define M68K_BA_SIZE_LONG 0x00 262 #define M68K_BA_SIZE_LINE 0x60 263 264 /* bus access transfer type codes */ 265 #define M68K_BA_TT_MOVE16 0x08 266 267 /* bits for 68040 MMU status register (mmusr) */ 268 #define M68K_MMU_B_040 0x0800 269 #define M68K_MMU_G_040 0x0400 270 #define M68K_MMU_U1_040 0x0200 271 #define M68K_MMU_U0_040 0x0100 272 #define M68K_MMU_S_040 0x0080 273 #define M68K_MMU_CM_040 0x0060 274 #define M68K_MMU_M_040 0x0010 275 #define M68K_MMU_WP_040 0x0004 276 #define M68K_MMU_T_040 0x0002 277 #define M68K_MMU_R_040 0x0001 278 279 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 280 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 281 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 282 M68K_MMU_WP_040) 283 284 /* bits for 68040 MMU Translation Control Register */ 285 #define M68K_TCR_ENABLED 0x8000 286 #define M68K_TCR_PAGE_8K 0x4000 287 288 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 289 #define M68K_DESC_WRITEPROT 0x00000004 290 #define M68K_DESC_USED 0x00000008 291 #define M68K_DESC_MODIFIED 0x00000010 292 #define M68K_DESC_CACHEMODE 0x00000060 293 #define M68K_DESC_CM_WRTHRU 0x00000000 294 #define M68K_DESC_CM_COPYBK 0x00000020 295 #define M68K_DESC_CM_SERIAL 0x00000040 296 #define M68K_DESC_CM_NCACHE 0x00000060 297 #define M68K_DESC_SUPERONLY 0x00000080 298 #define M68K_DESC_USERATTR 0x00000300 299 #define M68K_DESC_USERATTR_SHIFT 8 300 #define M68K_DESC_GLOBAL 0x00000400 301 #define M68K_DESC_URESERVED 0x00000800 302 303 #define M68K_ROOT_POINTER_ENTRIES 128 304 #define M68K_4K_PAGE_MASK (~0xff) 305 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 306 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 307 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 308 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 309 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 310 #define M68K_8K_PAGE_MASK (~0x7f) 311 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 312 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 313 #define M68K_UDT_VALID(entry) (entry & 2) 314 #define M68K_PDT_VALID(entry) (entry & 3) 315 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 316 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 317 #define M68K_TTS_POINTER_SHIFT 18 318 #define M68K_TTS_ROOT_SHIFT 25 319 320 /* bits for 68040 MMU Transparent Translation Registers */ 321 #define M68K_TTR_ADDR_BASE 0xff000000 322 #define M68K_TTR_ADDR_MASK 0x00ff0000 323 #define M68K_TTR_ADDR_MASK_SHIFT 8 324 #define M68K_TTR_ENABLED 0x00008000 325 #define M68K_TTR_SFIELD 0x00006000 326 #define M68K_TTR_SFIELD_USER 0x0000 327 #define M68K_TTR_SFIELD_SUPER 0x2000 328 329 /* m68k Control Registers */ 330 331 /* ColdFire */ 332 /* Memory Management Control Registers */ 333 #define M68K_CR_ASID 0x003 334 #define M68K_CR_ACR0 0x004 335 #define M68K_CR_ACR1 0x005 336 #define M68K_CR_ACR2 0x006 337 #define M68K_CR_ACR3 0x007 338 #define M68K_CR_MMUBAR 0x008 339 340 /* Processor Miscellaneous Registers */ 341 #define M68K_CR_PC 0x80F 342 343 /* Local Memory and Module Control Registers */ 344 #define M68K_CR_ROMBAR0 0xC00 345 #define M68K_CR_ROMBAR1 0xC01 346 #define M68K_CR_RAMBAR0 0xC04 347 #define M68K_CR_RAMBAR1 0xC05 348 #define M68K_CR_MPCR 0xC0C 349 #define M68K_CR_EDRAMBAR 0xC0D 350 #define M68K_CR_SECMBAR 0xC0E 351 #define M68K_CR_MBAR 0xC0F 352 353 /* Local Memory Address Permutation Control Registers */ 354 #define M68K_CR_PCR1U0 0xD02 355 #define M68K_CR_PCR1L0 0xD03 356 #define M68K_CR_PCR2U0 0xD04 357 #define M68K_CR_PCR2L0 0xD05 358 #define M68K_CR_PCR3U0 0xD06 359 #define M68K_CR_PCR3L0 0xD07 360 #define M68K_CR_PCR1U1 0xD0A 361 #define M68K_CR_PCR1L1 0xD0B 362 #define M68K_CR_PCR2U1 0xD0C 363 #define M68K_CR_PCR2L1 0xD0D 364 #define M68K_CR_PCR3U1 0xD0E 365 #define M68K_CR_PCR3L1 0xD0F 366 367 /* MC680x0 */ 368 /* MC680[1234]0/CPU32 */ 369 #define M68K_CR_SFC 0x000 370 #define M68K_CR_DFC 0x001 371 #define M68K_CR_USP 0x800 372 #define M68K_CR_VBR 0x801 /* + Coldfire */ 373 374 /* MC680[234]0 */ 375 #define M68K_CR_CACR 0x002 /* + Coldfire */ 376 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 377 #define M68K_CR_MSP 0x803 378 #define M68K_CR_ISP 0x804 379 380 /* MC68040/MC68LC040 */ 381 #define M68K_CR_TC 0x003 382 #define M68K_CR_ITT0 0x004 383 #define M68K_CR_ITT1 0x005 384 #define M68K_CR_DTT0 0x006 385 #define M68K_CR_DTT1 0x007 386 #define M68K_CR_MMUSR 0x805 387 #define M68K_CR_URP 0x806 388 #define M68K_CR_SRP 0x807 389 390 /* MC68EC040 */ 391 #define M68K_CR_IACR0 0x004 392 #define M68K_CR_IACR1 0x005 393 #define M68K_CR_DACR0 0x006 394 #define M68K_CR_DACR1 0x007 395 396 #define M68K_FPIAR_SHIFT 0 397 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 398 #define M68K_FPSR_SHIFT 1 399 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 400 #define M68K_FPCR_SHIFT 2 401 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 402 403 /* Floating-Point Status Register */ 404 405 /* Condition Code */ 406 #define FPSR_CC_MASK 0x0f000000 407 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 408 #define FPSR_CC_I 0x02000000 /* Infinity */ 409 #define FPSR_CC_Z 0x04000000 /* Zero */ 410 #define FPSR_CC_N 0x08000000 /* Negative */ 411 412 /* Quotient */ 413 414 #define FPSR_QT_MASK 0x00ff0000 415 #define FPSR_QT_SHIFT 16 416 417 /* Floating-Point Control Register */ 418 /* Rounding mode */ 419 #define FPCR_RND_MASK 0x0030 420 #define FPCR_RND_N 0x0000 421 #define FPCR_RND_Z 0x0010 422 #define FPCR_RND_M 0x0020 423 #define FPCR_RND_P 0x0030 424 425 /* Rounding precision */ 426 #define FPCR_PREC_MASK 0x00c0 427 #define FPCR_PREC_X 0x0000 428 #define FPCR_PREC_S 0x0040 429 #define FPCR_PREC_D 0x0080 430 #define FPCR_PREC_U 0x00c0 431 432 #define FPCR_EXCP_MASK 0xff00 433 434 /* CACR fields are implementation defined, but some bits are common. */ 435 #define M68K_CACR_EUSP 0x10 436 437 #define MACSR_PAV0 0x100 438 #define MACSR_OMC 0x080 439 #define MACSR_SU 0x040 440 #define MACSR_FI 0x020 441 #define MACSR_RT 0x010 442 #define MACSR_N 0x008 443 #define MACSR_Z 0x004 444 #define MACSR_V 0x002 445 #define MACSR_EV 0x001 446 447 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 448 void m68k_switch_sp(CPUM68KState *env); 449 450 void do_m68k_semihosting(CPUM68KState *env, int nr); 451 452 /* 453 * There are 4 ColdFire core ISA revisions: A, A+, B and C. 454 * Each feature covers the subset of instructions common to the 455 * ISA revisions mentioned. 456 */ 457 458 enum m68k_features { 459 M68K_FEATURE_M68000, 460 M68K_FEATURE_M68020, 461 M68K_FEATURE_M68030, 462 M68K_FEATURE_M68040, 463 M68K_FEATURE_M68060, 464 M68K_FEATURE_CF_ISA_A, 465 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 466 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 467 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 468 M68K_FEATURE_CF_FPU, 469 M68K_FEATURE_CF_MAC, 470 M68K_FEATURE_CF_EMAC, 471 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 472 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 473 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 474 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 475 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 476 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 477 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 478 M68K_FEATURE_BCCL, /* Long conditional branches. */ 479 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 480 M68K_FEATURE_FPU, 481 M68K_FEATURE_CAS, 482 M68K_FEATURE_BKPT, 483 M68K_FEATURE_RTD, 484 M68K_FEATURE_CHK2, 485 M68K_FEATURE_MOVEP, 486 }; 487 488 static inline int m68k_feature(CPUM68KState *env, int feature) 489 { 490 return (env->features & (1u << feature)) != 0; 491 } 492 493 void m68k_cpu_list(void); 494 495 void register_m68k_insns (CPUM68KState *env); 496 497 enum { 498 /* 1 bit to define user level / supervisor access */ 499 ACCESS_SUPER = 0x01, 500 /* 1 bit to indicate direction */ 501 ACCESS_STORE = 0x02, 502 /* 1 bit to indicate debug access */ 503 ACCESS_DEBUG = 0x04, 504 /* PTEST instruction */ 505 ACCESS_PTEST = 0x08, 506 /* Type of instruction that generated the access */ 507 ACCESS_CODE = 0x10, /* Code fetch access */ 508 ACCESS_DATA = 0x20, /* Data load/store access */ 509 }; 510 511 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 512 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 513 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 514 515 #define cpu_signal_handler cpu_m68k_signal_handler 516 #define cpu_list m68k_cpu_list 517 518 /* MMU modes definitions */ 519 #define MMU_KERNEL_IDX 0 520 #define MMU_USER_IDX 1 521 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 522 { 523 return (env->sr & SR_S) == 0 ? 1 : 0; 524 } 525 526 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 527 MMUAccessType access_type, int mmu_idx, 528 bool probe, uintptr_t retaddr); 529 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 530 unsigned size, MMUAccessType access_type, 531 int mmu_idx, MemTxAttrs attrs, 532 MemTxResult response, uintptr_t retaddr); 533 534 typedef CPUM68KState CPUArchState; 535 typedef M68kCPU ArchCPU; 536 537 #include "exec/cpu-all.h" 538 539 /* TB flags */ 540 #define TB_FLAGS_MACSR 0x0f 541 #define TB_FLAGS_MSR_S_BIT 13 542 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 543 #define TB_FLAGS_SFC_S_BIT 14 544 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 545 #define TB_FLAGS_DFC_S_BIT 15 546 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 547 548 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 549 target_ulong *cs_base, uint32_t *flags) 550 { 551 *pc = env->pc; 552 *cs_base = 0; 553 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 554 if (env->sr & SR_S) { 555 *flags |= TB_FLAGS_MSR_S; 556 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 557 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 558 } 559 } 560 561 void dump_mmu(CPUM68KState *env); 562 563 #endif 564