1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #define TARGET_LONG_BITS 32 25 26 #define CPUArchState struct CPUM68KState 27 28 #include "qemu-common.h" 29 #include "exec/cpu-defs.h" 30 #include "cpu-qom.h" 31 32 #define OS_BYTE 0 33 #define OS_WORD 1 34 #define OS_LONG 2 35 #define OS_SINGLE 3 36 #define OS_DOUBLE 4 37 #define OS_EXTENDED 5 38 #define OS_PACKED 6 39 #define OS_UNSIZED 7 40 41 #define MAX_QREGS 32 42 43 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 44 #define EXCP_ADDRESS 3 /* Address error. */ 45 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 46 #define EXCP_DIV0 5 /* Divide by zero */ 47 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 48 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 49 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 50 #define EXCP_TRACE 9 51 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 52 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 53 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 54 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 55 #define EXCP_FORMAT 14 /* RTE format error. */ 56 #define EXCP_UNINITIALIZED 15 57 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 58 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 59 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 60 #define EXCP_TRAP0 32 /* User trap #0. */ 61 #define EXCP_TRAP15 47 /* User trap #15. */ 62 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 63 #define EXCP_FP_INEX 49 /* Inexact result */ 64 #define EXCP_FP_DZ 50 /* Divide by Zero */ 65 #define EXCP_FP_UNFL 51 /* Underflow */ 66 #define EXCP_FP_OPERR 52 /* Operand Error */ 67 #define EXCP_FP_OVFL 53 /* Overflow */ 68 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 69 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 70 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 71 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 72 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 73 74 #define EXCP_RTE 0x100 75 #define EXCP_HALT_INSN 0x101 76 77 #define M68K_DTTR0 0 78 #define M68K_DTTR1 1 79 #define M68K_ITTR0 2 80 #define M68K_ITTR1 3 81 82 #define M68K_MAX_TTR 2 83 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 84 85 #define NB_MMU_MODES 2 86 #define TARGET_INSN_START_EXTRA_WORDS 1 87 88 typedef CPU_LDoubleU FPReg; 89 90 typedef struct CPUM68KState { 91 uint32_t dregs[8]; 92 uint32_t aregs[8]; 93 uint32_t pc; 94 uint32_t sr; 95 96 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 97 int current_sp; 98 uint32_t sp[3]; 99 100 /* Condition flags. */ 101 uint32_t cc_op; 102 uint32_t cc_x; /* always 0/1 */ 103 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 104 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 105 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 106 uint32_t cc_z; /* == 0 or unused */ 107 108 FPReg fregs[8]; 109 FPReg fp_result; 110 uint32_t fpcr; 111 uint32_t fpsr; 112 float_status fp_status; 113 114 uint64_t mactmp; 115 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 116 two 8-bit parts. We store a single 64-bit value and 117 rearrange/extend this when changing modes. */ 118 uint64_t macc[4]; 119 uint32_t macsr; 120 uint32_t mac_mask; 121 122 /* MMU status. */ 123 struct { 124 uint32_t ar; 125 uint32_t ssw; 126 /* 68040 */ 127 uint16_t tcr; 128 uint32_t urp; 129 uint32_t srp; 130 bool fault; 131 uint32_t ttr[4]; 132 uint32_t mmusr; 133 } mmu; 134 135 /* Control registers. */ 136 uint32_t vbr; 137 uint32_t mbar; 138 uint32_t rambar0; 139 uint32_t cacr; 140 uint32_t sfc; 141 uint32_t dfc; 142 143 int pending_vector; 144 int pending_level; 145 146 uint32_t qregs[MAX_QREGS]; 147 148 /* Fields up to this point are cleared by a CPU reset */ 149 struct {} end_reset_fields; 150 151 CPU_COMMON 152 153 /* Fields from here on are preserved across CPU reset. */ 154 uint32_t features; 155 } CPUM68KState; 156 157 /** 158 * M68kCPU: 159 * @env: #CPUM68KState 160 * 161 * A Motorola 68k CPU. 162 */ 163 struct M68kCPU { 164 /*< private >*/ 165 CPUState parent_obj; 166 /*< public >*/ 167 168 CPUM68KState env; 169 }; 170 171 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) 172 { 173 return container_of(env, M68kCPU, env); 174 } 175 176 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) 177 178 #define ENV_OFFSET offsetof(M68kCPU, env) 179 180 void m68k_cpu_do_interrupt(CPUState *cpu); 181 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 182 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 183 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 184 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 185 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 186 187 void m68k_tcg_init(void); 188 void m68k_cpu_init_gdb(M68kCPU *cpu); 189 /* you can call this signal handler from your SIGBUS and SIGSEGV 190 signal handlers to inform the virtual CPU of exceptions. non zero 191 is returned if the signal was handled by the virtual CPU. */ 192 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 193 void *puc); 194 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 195 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 196 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 197 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 198 199 200 /* Instead of computing the condition codes after each m68k instruction, 201 * QEMU just stores one operand (called CC_SRC), the result 202 * (called CC_DEST) and the type of operation (called CC_OP). When the 203 * condition codes are needed, the condition codes can be calculated 204 * using this information. Condition codes are not generated if they 205 * are only needed for conditional branches. 206 */ 207 typedef enum { 208 /* Translator only -- use env->cc_op. */ 209 CC_OP_DYNAMIC, 210 211 /* Each flag bit computed into cc_[xcnvz]. */ 212 CC_OP_FLAGS, 213 214 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 215 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 216 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 217 218 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 219 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 220 221 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 222 CC_OP_LOGIC, 223 224 CC_OP_NB 225 } CCOp; 226 227 #define CCF_C 0x01 228 #define CCF_V 0x02 229 #define CCF_Z 0x04 230 #define CCF_N 0x08 231 #define CCF_X 0x10 232 233 #define SR_I_SHIFT 8 234 #define SR_I 0x0700 235 #define SR_M 0x1000 236 #define SR_S 0x2000 237 #define SR_T_SHIFT 14 238 #define SR_T 0xc000 239 240 #define M68K_SSP 0 241 #define M68K_USP 1 242 #define M68K_ISP 2 243 244 /* bits for 68040 special status word */ 245 #define M68K_CP_040 0x8000 246 #define M68K_CU_040 0x4000 247 #define M68K_CT_040 0x2000 248 #define M68K_CM_040 0x1000 249 #define M68K_MA_040 0x0800 250 #define M68K_ATC_040 0x0400 251 #define M68K_LK_040 0x0200 252 #define M68K_RW_040 0x0100 253 #define M68K_SIZ_040 0x0060 254 #define M68K_TT_040 0x0018 255 #define M68K_TM_040 0x0007 256 257 #define M68K_TM_040_DATA 0x0001 258 #define M68K_TM_040_CODE 0x0002 259 #define M68K_TM_040_SUPER 0x0004 260 261 /* bits for 68040 write back status word */ 262 #define M68K_WBV_040 0x80 263 #define M68K_WBSIZ_040 0x60 264 #define M68K_WBBYT_040 0x20 265 #define M68K_WBWRD_040 0x40 266 #define M68K_WBLNG_040 0x00 267 #define M68K_WBTT_040 0x18 268 #define M68K_WBTM_040 0x07 269 270 /* bus access size codes */ 271 #define M68K_BA_SIZE_MASK 0x60 272 #define M68K_BA_SIZE_BYTE 0x20 273 #define M68K_BA_SIZE_WORD 0x40 274 #define M68K_BA_SIZE_LONG 0x00 275 #define M68K_BA_SIZE_LINE 0x60 276 277 /* bus access transfer type codes */ 278 #define M68K_BA_TT_MOVE16 0x08 279 280 /* bits for 68040 MMU status register (mmusr) */ 281 #define M68K_MMU_B_040 0x0800 282 #define M68K_MMU_G_040 0x0400 283 #define M68K_MMU_U1_040 0x0200 284 #define M68K_MMU_U0_040 0x0100 285 #define M68K_MMU_S_040 0x0080 286 #define M68K_MMU_CM_040 0x0060 287 #define M68K_MMU_M_040 0x0010 288 #define M68K_MMU_WP_040 0x0004 289 #define M68K_MMU_T_040 0x0002 290 #define M68K_MMU_R_040 0x0001 291 292 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 293 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 294 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 295 M68K_MMU_WP_040) 296 297 /* bits for 68040 MMU Translation Control Register */ 298 #define M68K_TCR_ENABLED 0x8000 299 #define M68K_TCR_PAGE_8K 0x4000 300 301 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 302 #define M68K_DESC_WRITEPROT 0x00000004 303 #define M68K_DESC_USED 0x00000008 304 #define M68K_DESC_MODIFIED 0x00000010 305 #define M68K_DESC_CACHEMODE 0x00000060 306 #define M68K_DESC_CM_WRTHRU 0x00000000 307 #define M68K_DESC_CM_COPYBK 0x00000020 308 #define M68K_DESC_CM_SERIAL 0x00000040 309 #define M68K_DESC_CM_NCACHE 0x00000060 310 #define M68K_DESC_SUPERONLY 0x00000080 311 #define M68K_DESC_USERATTR 0x00000300 312 #define M68K_DESC_USERATTR_SHIFT 8 313 #define M68K_DESC_GLOBAL 0x00000400 314 #define M68K_DESC_URESERVED 0x00000800 315 316 #define M68K_ROOT_POINTER_ENTRIES 128 317 #define M68K_4K_PAGE_MASK (~0xff) 318 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 319 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 320 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 321 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 322 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 323 #define M68K_8K_PAGE_MASK (~0x7f) 324 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 325 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 326 #define M68K_UDT_VALID(entry) (entry & 2) 327 #define M68K_PDT_VALID(entry) (entry & 3) 328 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 329 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 330 #define M68K_TTS_POINTER_SHIFT 18 331 #define M68K_TTS_ROOT_SHIFT 25 332 333 /* bits for 68040 MMU Transparent Translation Registers */ 334 #define M68K_TTR_ADDR_BASE 0xff000000 335 #define M68K_TTR_ADDR_MASK 0x00ff0000 336 #define M68K_TTR_ADDR_MASK_SHIFT 8 337 #define M68K_TTR_ENABLED 0x00008000 338 #define M68K_TTR_SFIELD 0x00006000 339 #define M68K_TTR_SFIELD_USER 0x0000 340 #define M68K_TTR_SFIELD_SUPER 0x2000 341 342 /* m68k Control Registers */ 343 344 /* ColdFire */ 345 /* Memory Management Control Registers */ 346 #define M68K_CR_ASID 0x003 347 #define M68K_CR_ACR0 0x004 348 #define M68K_CR_ACR1 0x005 349 #define M68K_CR_ACR2 0x006 350 #define M68K_CR_ACR3 0x007 351 #define M68K_CR_MMUBAR 0x008 352 353 /* Processor Miscellaneous Registers */ 354 #define M68K_CR_PC 0x80F 355 356 /* Local Memory and Module Control Registers */ 357 #define M68K_CR_ROMBAR0 0xC00 358 #define M68K_CR_ROMBAR1 0xC01 359 #define M68K_CR_RAMBAR0 0xC04 360 #define M68K_CR_RAMBAR1 0xC05 361 #define M68K_CR_MPCR 0xC0C 362 #define M68K_CR_EDRAMBAR 0xC0D 363 #define M68K_CR_SECMBAR 0xC0E 364 #define M68K_CR_MBAR 0xC0F 365 366 /* Local Memory Address Permutation Control Registers */ 367 #define M68K_CR_PCR1U0 0xD02 368 #define M68K_CR_PCR1L0 0xD03 369 #define M68K_CR_PCR2U0 0xD04 370 #define M68K_CR_PCR2L0 0xD05 371 #define M68K_CR_PCR3U0 0xD06 372 #define M68K_CR_PCR3L0 0xD07 373 #define M68K_CR_PCR1U1 0xD0A 374 #define M68K_CR_PCR1L1 0xD0B 375 #define M68K_CR_PCR2U1 0xD0C 376 #define M68K_CR_PCR2L1 0xD0D 377 #define M68K_CR_PCR3U1 0xD0E 378 #define M68K_CR_PCR3L1 0xD0F 379 380 /* MC680x0 */ 381 /* MC680[1234]0/CPU32 */ 382 #define M68K_CR_SFC 0x000 383 #define M68K_CR_DFC 0x001 384 #define M68K_CR_USP 0x800 385 #define M68K_CR_VBR 0x801 /* + Coldfire */ 386 387 /* MC680[234]0 */ 388 #define M68K_CR_CACR 0x002 /* + Coldfire */ 389 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 390 #define M68K_CR_MSP 0x803 391 #define M68K_CR_ISP 0x804 392 393 /* MC68040/MC68LC040 */ 394 #define M68K_CR_TC 0x003 395 #define M68K_CR_ITT0 0x004 396 #define M68K_CR_ITT1 0x005 397 #define M68K_CR_DTT0 0x006 398 #define M68K_CR_DTT1 0x007 399 #define M68K_CR_MMUSR 0x805 400 #define M68K_CR_URP 0x806 401 #define M68K_CR_SRP 0x807 402 403 /* MC68EC040 */ 404 #define M68K_CR_IACR0 0x004 405 #define M68K_CR_IACR1 0x005 406 #define M68K_CR_DACR0 0x006 407 #define M68K_CR_DACR1 0x007 408 409 #define M68K_FPIAR_SHIFT 0 410 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 411 #define M68K_FPSR_SHIFT 1 412 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 413 #define M68K_FPCR_SHIFT 2 414 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 415 416 /* Floating-Point Status Register */ 417 418 /* Condition Code */ 419 #define FPSR_CC_MASK 0x0f000000 420 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 421 #define FPSR_CC_I 0x02000000 /* Infinity */ 422 #define FPSR_CC_Z 0x04000000 /* Zero */ 423 #define FPSR_CC_N 0x08000000 /* Negative */ 424 425 /* Quotient */ 426 427 #define FPSR_QT_MASK 0x00ff0000 428 #define FPSR_QT_SHIFT 16 429 430 /* Floating-Point Control Register */ 431 /* Rounding mode */ 432 #define FPCR_RND_MASK 0x0030 433 #define FPCR_RND_N 0x0000 434 #define FPCR_RND_Z 0x0010 435 #define FPCR_RND_M 0x0020 436 #define FPCR_RND_P 0x0030 437 438 /* Rounding precision */ 439 #define FPCR_PREC_MASK 0x00c0 440 #define FPCR_PREC_X 0x0000 441 #define FPCR_PREC_S 0x0040 442 #define FPCR_PREC_D 0x0080 443 #define FPCR_PREC_U 0x00c0 444 445 #define FPCR_EXCP_MASK 0xff00 446 447 /* CACR fields are implementation defined, but some bits are common. */ 448 #define M68K_CACR_EUSP 0x10 449 450 #define MACSR_PAV0 0x100 451 #define MACSR_OMC 0x080 452 #define MACSR_SU 0x040 453 #define MACSR_FI 0x020 454 #define MACSR_RT 0x010 455 #define MACSR_N 0x008 456 #define MACSR_Z 0x004 457 #define MACSR_V 0x002 458 #define MACSR_EV 0x001 459 460 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 461 void m68k_switch_sp(CPUM68KState *env); 462 463 void do_m68k_semihosting(CPUM68KState *env, int nr); 464 465 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 466 Each feature covers the subset of instructions common to the 467 ISA revisions mentioned. */ 468 469 enum m68k_features { 470 M68K_FEATURE_M68000, 471 M68K_FEATURE_CF_ISA_A, 472 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 473 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 474 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 475 M68K_FEATURE_CF_FPU, 476 M68K_FEATURE_CF_MAC, 477 M68K_FEATURE_CF_EMAC, 478 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 479 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 480 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 481 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 482 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 483 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 484 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 485 M68K_FEATURE_BCCL, /* Long conditional branches. */ 486 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 487 M68K_FEATURE_FPU, 488 M68K_FEATURE_CAS, 489 M68K_FEATURE_BKPT, 490 M68K_FEATURE_RTD, 491 M68K_FEATURE_CHK2, 492 M68K_FEATURE_M68040, /* instructions specific to MC68040 */ 493 M68K_FEATURE_MOVEP, 494 }; 495 496 static inline int m68k_feature(CPUM68KState *env, int feature) 497 { 498 return (env->features & (1u << feature)) != 0; 499 } 500 501 void m68k_cpu_list(void); 502 503 void register_m68k_insns (CPUM68KState *env); 504 505 /* Coldfire Linux uses 8k pages 506 * and m68k linux uses 4k pages 507 * use the smallest one 508 */ 509 #define TARGET_PAGE_BITS 12 510 511 enum { 512 /* 1 bit to define user level / supervisor access */ 513 ACCESS_SUPER = 0x01, 514 /* 1 bit to indicate direction */ 515 ACCESS_STORE = 0x02, 516 /* 1 bit to indicate debug access */ 517 ACCESS_DEBUG = 0x04, 518 /* PTEST instruction */ 519 ACCESS_PTEST = 0x08, 520 /* Type of instruction that generated the access */ 521 ACCESS_CODE = 0x10, /* Code fetch access */ 522 ACCESS_DATA = 0x20, /* Data load/store access */ 523 }; 524 525 #define TARGET_PHYS_ADDR_SPACE_BITS 32 526 #define TARGET_VIRT_ADDR_SPACE_BITS 32 527 528 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 529 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 530 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 531 532 #define cpu_signal_handler cpu_m68k_signal_handler 533 #define cpu_list m68k_cpu_list 534 535 /* MMU modes definitions */ 536 #define MMU_MODE0_SUFFIX _kernel 537 #define MMU_MODE1_SUFFIX _user 538 #define MMU_KERNEL_IDX 0 539 #define MMU_USER_IDX 1 540 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 541 { 542 return (env->sr & SR_S) == 0 ? 1 : 0; 543 } 544 545 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, 546 int mmu_idx); 547 void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, 548 bool is_write, bool is_exec, int is_asi, 549 unsigned size); 550 551 #include "exec/cpu-all.h" 552 553 /* TB flags */ 554 #define TB_FLAGS_MACSR 0x0f 555 #define TB_FLAGS_MSR_S_BIT 13 556 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 557 #define TB_FLAGS_SFC_S_BIT 14 558 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 559 #define TB_FLAGS_DFC_S_BIT 15 560 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 561 562 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 563 target_ulong *cs_base, uint32_t *flags) 564 { 565 *pc = env->pc; 566 *cs_base = 0; 567 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 568 if (env->sr & SR_S) { 569 *flags |= TB_FLAGS_MSR_S; 570 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 571 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 572 } 573 } 574 575 void dump_mmu(CPUM68KState *env); 576 577 #endif 578