1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #define TARGET_LONG_BITS 32 25 26 #define CPUArchState struct CPUM68KState 27 28 #include "qemu-common.h" 29 #include "exec/cpu-defs.h" 30 #include "cpu-qom.h" 31 #include "fpu/softfloat.h" 32 33 #define OS_BYTE 0 34 #define OS_WORD 1 35 #define OS_LONG 2 36 #define OS_SINGLE 3 37 #define OS_DOUBLE 4 38 #define OS_EXTENDED 5 39 #define OS_PACKED 6 40 #define OS_UNSIZED 7 41 42 #define MAX_QREGS 32 43 44 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 45 #define EXCP_ADDRESS 3 /* Address error. */ 46 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 47 #define EXCP_DIV0 5 /* Divide by zero */ 48 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 49 #define EXCP_TRACE 9 50 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 51 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 52 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 53 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 54 #define EXCP_FORMAT 14 /* RTE format error. */ 55 #define EXCP_UNINITIALIZED 15 56 #define EXCP_TRAP0 32 /* User trap #0. */ 57 #define EXCP_TRAP15 47 /* User trap #15. */ 58 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 59 #define EXCP_FP_INEX 49 /* Inexact result */ 60 #define EXCP_FP_DZ 50 /* Divide by Zero */ 61 #define EXCP_FP_UNFL 51 /* Underflow */ 62 #define EXCP_FP_OPERR 52 /* Operand Error */ 63 #define EXCP_FP_OVFL 53 /* Overflow */ 64 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 65 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 66 #define EXCP_UNSUPPORTED 61 67 68 #define EXCP_RTE 0x100 69 #define EXCP_HALT_INSN 0x101 70 71 #define NB_MMU_MODES 2 72 #define TARGET_INSN_START_EXTRA_WORDS 1 73 74 typedef CPU_LDoubleU FPReg; 75 76 typedef struct CPUM68KState { 77 uint32_t dregs[8]; 78 uint32_t aregs[8]; 79 uint32_t pc; 80 uint32_t sr; 81 82 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 83 int current_sp; 84 uint32_t sp[2]; 85 86 /* Condition flags. */ 87 uint32_t cc_op; 88 uint32_t cc_x; /* always 0/1 */ 89 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 90 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 91 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 92 uint32_t cc_z; /* == 0 or unused */ 93 94 FPReg fregs[8]; 95 FPReg fp_result; 96 uint32_t fpcr; 97 uint32_t fpsr; 98 float_status fp_status; 99 100 uint64_t mactmp; 101 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 102 two 8-bit parts. We store a single 64-bit value and 103 rearrange/extend this when changing modes. */ 104 uint64_t macc[4]; 105 uint32_t macsr; 106 uint32_t mac_mask; 107 108 /* MMU status. */ 109 struct { 110 uint32_t ar; 111 } mmu; 112 113 /* Control registers. */ 114 uint32_t vbr; 115 uint32_t mbar; 116 uint32_t rambar0; 117 uint32_t cacr; 118 119 int pending_vector; 120 int pending_level; 121 122 uint32_t qregs[MAX_QREGS]; 123 124 /* Fields up to this point are cleared by a CPU reset */ 125 struct {} end_reset_fields; 126 127 CPU_COMMON 128 129 /* Fields from here on are preserved across CPU reset. */ 130 uint32_t features; 131 } CPUM68KState; 132 133 /** 134 * M68kCPU: 135 * @env: #CPUM68KState 136 * 137 * A Motorola 68k CPU. 138 */ 139 struct M68kCPU { 140 /*< private >*/ 141 CPUState parent_obj; 142 /*< public >*/ 143 144 CPUM68KState env; 145 }; 146 147 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) 148 { 149 return container_of(env, M68kCPU, env); 150 } 151 152 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) 153 154 #define ENV_OFFSET offsetof(M68kCPU, env) 155 156 void m68k_cpu_do_interrupt(CPUState *cpu); 157 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 158 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 159 int flags); 160 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 161 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 162 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 163 164 void m68k_tcg_init(void); 165 void m68k_cpu_init_gdb(M68kCPU *cpu); 166 /* you can call this signal handler from your SIGBUS and SIGSEGV 167 signal handlers to inform the virtual CPU of exceptions. non zero 168 is returned if the signal was handled by the virtual CPU. */ 169 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 170 void *puc); 171 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 172 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 173 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 174 175 176 /* Instead of computing the condition codes after each m68k instruction, 177 * QEMU just stores one operand (called CC_SRC), the result 178 * (called CC_DEST) and the type of operation (called CC_OP). When the 179 * condition codes are needed, the condition codes can be calculated 180 * using this information. Condition codes are not generated if they 181 * are only needed for conditional branches. 182 */ 183 typedef enum { 184 /* Translator only -- use env->cc_op. */ 185 CC_OP_DYNAMIC = -1, 186 187 /* Each flag bit computed into cc_[xcnvz]. */ 188 CC_OP_FLAGS, 189 190 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 191 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 192 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 193 194 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 195 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 196 197 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 198 CC_OP_LOGIC, 199 200 CC_OP_NB 201 } CCOp; 202 203 #define CCF_C 0x01 204 #define CCF_V 0x02 205 #define CCF_Z 0x04 206 #define CCF_N 0x08 207 #define CCF_X 0x10 208 209 #define SR_I_SHIFT 8 210 #define SR_I 0x0700 211 #define SR_M 0x1000 212 #define SR_S 0x2000 213 #define SR_T 0x8000 214 215 #define M68K_SSP 0 216 #define M68K_USP 1 217 218 #define M68K_FPIAR_SHIFT 0 219 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 220 #define M68K_FPSR_SHIFT 1 221 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 222 #define M68K_FPCR_SHIFT 2 223 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 224 225 /* Floating-Point Status Register */ 226 227 /* Condition Code */ 228 #define FPSR_CC_MASK 0x0f000000 229 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 230 #define FPSR_CC_I 0x02000000 /* Infinity */ 231 #define FPSR_CC_Z 0x04000000 /* Zero */ 232 #define FPSR_CC_N 0x08000000 /* Negative */ 233 234 /* Quotient */ 235 236 #define FPSR_QT_MASK 0x00ff0000 237 238 /* Floating-Point Control Register */ 239 /* Rounding mode */ 240 #define FPCR_RND_MASK 0x0030 241 #define FPCR_RND_N 0x0000 242 #define FPCR_RND_Z 0x0010 243 #define FPCR_RND_M 0x0020 244 #define FPCR_RND_P 0x0030 245 246 /* Rounding precision */ 247 #define FPCR_PREC_MASK 0x00c0 248 #define FPCR_PREC_X 0x0000 249 #define FPCR_PREC_S 0x0040 250 #define FPCR_PREC_D 0x0080 251 #define FPCR_PREC_U 0x00c0 252 253 #define FPCR_EXCP_MASK 0xff00 254 255 /* CACR fields are implementation defined, but some bits are common. */ 256 #define M68K_CACR_EUSP 0x10 257 258 #define MACSR_PAV0 0x100 259 #define MACSR_OMC 0x080 260 #define MACSR_SU 0x040 261 #define MACSR_FI 0x020 262 #define MACSR_RT 0x010 263 #define MACSR_N 0x008 264 #define MACSR_Z 0x004 265 #define MACSR_V 0x002 266 #define MACSR_EV 0x001 267 268 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 269 void m68k_switch_sp(CPUM68KState *env); 270 271 void do_m68k_semihosting(CPUM68KState *env, int nr); 272 273 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 274 Each feature covers the subset of instructions common to the 275 ISA revisions mentioned. */ 276 277 enum m68k_features { 278 M68K_FEATURE_M68000, 279 M68K_FEATURE_CF_ISA_A, 280 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 281 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 282 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 283 M68K_FEATURE_CF_FPU, 284 M68K_FEATURE_CF_MAC, 285 M68K_FEATURE_CF_EMAC, 286 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 287 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 288 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 289 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 290 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 291 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 292 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 293 M68K_FEATURE_BCCL, /* Long conditional branches. */ 294 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 295 M68K_FEATURE_FPU, 296 M68K_FEATURE_CAS, 297 M68K_FEATURE_BKPT, 298 M68K_FEATURE_RTD, 299 }; 300 301 static inline int m68k_feature(CPUM68KState *env, int feature) 302 { 303 return (env->features & (1u << feature)) != 0; 304 } 305 306 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf); 307 308 void register_m68k_insns (CPUM68KState *env); 309 310 #ifdef CONFIG_USER_ONLY 311 /* Coldfire Linux uses 8k pages 312 * and m68k linux uses 4k pages 313 * use the smaller one 314 */ 315 #define TARGET_PAGE_BITS 12 316 #else 317 /* Smallest TLB entry size is 1k. */ 318 #define TARGET_PAGE_BITS 10 319 #endif 320 321 #define TARGET_PHYS_ADDR_SPACE_BITS 32 322 #define TARGET_VIRT_ADDR_SPACE_BITS 32 323 324 #define cpu_init(cpu_model) cpu_generic_init(TYPE_M68K_CPU, cpu_model) 325 326 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 327 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 328 329 #define cpu_signal_handler cpu_m68k_signal_handler 330 #define cpu_list m68k_cpu_list 331 332 /* MMU modes definitions */ 333 #define MMU_MODE0_SUFFIX _kernel 334 #define MMU_MODE1_SUFFIX _user 335 #define MMU_USER_IDX 1 336 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 337 { 338 return (env->sr & SR_S) == 0 ? 1 : 0; 339 } 340 341 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 342 int mmu_idx); 343 344 #include "exec/cpu-all.h" 345 346 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 347 target_ulong *cs_base, uint32_t *flags) 348 { 349 *pc = env->pc; 350 *cs_base = 0; 351 *flags = (env->sr & SR_S) /* Bit 13 */ 352 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ 353 } 354 355 #endif 356