1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "exec/cpu-common.h" 25 #include "exec/cpu-defs.h" 26 #include "exec/cpu-interrupt.h" 27 #include "qemu/cpu-float.h" 28 #include "cpu-qom.h" 29 30 #define OS_BYTE 0 31 #define OS_WORD 1 32 #define OS_LONG 2 33 #define OS_SINGLE 3 34 #define OS_DOUBLE 4 35 #define OS_EXTENDED 5 36 #define OS_PACKED 6 37 #define OS_UNSIZED 7 38 39 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 40 #define EXCP_ADDRESS 3 /* Address error. */ 41 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 42 #define EXCP_DIV0 5 /* Divide by zero */ 43 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 44 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 45 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 46 #define EXCP_TRACE 9 47 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 48 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 49 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 50 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 51 #define EXCP_FORMAT 14 /* RTE format error. */ 52 #define EXCP_UNINITIALIZED 15 53 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 54 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 55 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 56 #define EXCP_TRAP0 32 /* User trap #0. */ 57 #define EXCP_TRAP15 47 /* User trap #15. */ 58 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 59 #define EXCP_FP_INEX 49 /* Inexact result */ 60 #define EXCP_FP_DZ 50 /* Divide by Zero */ 61 #define EXCP_FP_UNFL 51 /* Underflow */ 62 #define EXCP_FP_OPERR 52 /* Operand Error */ 63 #define EXCP_FP_OVFL 53 /* Overflow */ 64 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 65 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 66 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 67 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 68 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 69 70 #define EXCP_RTE 0x100 71 #define EXCP_SEMIHOSTING 0x101 72 73 #define M68K_DTTR0 0 74 #define M68K_DTTR1 1 75 #define M68K_ITTR0 2 76 #define M68K_ITTR1 3 77 78 #define M68K_MAX_TTR 2 79 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 80 81 #define TARGET_INSN_START_EXTRA_WORDS 1 82 83 typedef CPU_LDoubleU FPReg; 84 85 typedef struct CPUArchState { 86 uint32_t dregs[8]; 87 uint32_t aregs[8]; 88 uint32_t pc; 89 uint32_t sr; 90 91 /* 92 * The 68020/30/40 support two supervisor stacks, ISP and MSP. 93 * The 68000/10, Coldfire, and CPU32 only have USP/SSP. 94 * 95 * The current_sp is stored in aregs[7], the other here. 96 * The USP, SSP, and if used the additional ISP for 68020/30/40. 97 */ 98 int current_sp; 99 uint32_t sp[3]; 100 101 /* Condition flags. */ 102 uint32_t cc_op; 103 uint32_t cc_x; /* always 0/1 */ 104 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 105 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 106 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 107 uint32_t cc_z; /* == 0 or unused */ 108 109 FPReg fregs[8]; 110 FPReg fp_result; 111 uint32_t fpcr; 112 uint32_t fpsr; 113 float_status fp_status; 114 115 uint64_t mactmp; 116 /* 117 * EMAC Hardware deals with 48-bit values composed of one 32-bit and 118 * two 8-bit parts. We store a single 64-bit value and 119 * rearrange/extend this when changing modes. 120 */ 121 uint64_t macc[4]; 122 uint32_t macsr; 123 uint32_t mac_mask; 124 125 /* MMU status. */ 126 struct { 127 /* 128 * Holds the "address" value in between raising an exception 129 * and creation of the exception stack frame. 130 * Used for both Format 7 exceptions (Access, i.e. mmu) 131 * and Format 2 exceptions (chk, div0, trapcc, etc). 132 */ 133 uint32_t ar; 134 uint32_t ssw; 135 /* 68040 */ 136 uint16_t tcr; 137 uint32_t urp; 138 uint32_t srp; 139 bool fault; 140 uint32_t ttr[4]; 141 uint32_t mmusr; 142 } mmu; 143 144 /* Control registers. */ 145 uint32_t vbr; 146 uint32_t mbar; 147 uint32_t rambar0; 148 uint32_t cacr; 149 uint32_t sfc; 150 uint32_t dfc; 151 152 int pending_vector; 153 int pending_level; 154 155 /* Fields up to this point are cleared by a CPU reset */ 156 struct {} end_reset_fields; 157 158 /* Fields from here on are preserved across CPU reset. */ 159 uint64_t features; 160 } CPUM68KState; 161 162 /* 163 * M68kCPU: 164 * @env: #CPUM68KState 165 * 166 * A Motorola 68k CPU. 167 */ 168 struct ArchCPU { 169 CPUState parent_obj; 170 171 CPUM68KState env; 172 }; 173 174 /* 175 * M68kCPUClass: 176 * @parent_realize: The parent class' realize handler. 177 * @parent_phases: The parent class' reset phase handlers. 178 * 179 * A Motorola 68k CPU model. 180 */ 181 struct M68kCPUClass { 182 CPUClass parent_class; 183 184 DeviceRealize parent_realize; 185 ResettablePhases parent_phases; 186 }; 187 188 #ifndef CONFIG_USER_ONLY 189 void m68k_cpu_do_interrupt(CPUState *cpu); 190 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 191 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 192 #endif /* !CONFIG_USER_ONLY */ 193 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 194 int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 195 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 196 197 void m68k_tcg_init(void); 198 void m68k_translate_code(CPUState *cs, TranslationBlock *tb, 199 int *max_insns, vaddr pc, void *host_pc); 200 void m68k_cpu_init_gdb(M68kCPU *cpu); 201 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 202 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 203 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 204 void cpu_m68k_restore_fp_status(CPUM68KState *env); 205 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 206 uint32_t cpu_m68k_get_fpsr(CPUM68KState *env); 207 void cpu_m68k_set_fpsr(CPUM68KState *env, uint32_t val); 208 209 /* 210 * Instead of computing the condition codes after each m68k instruction, 211 * QEMU just stores one operand (called CC_SRC), the result 212 * (called CC_DEST) and the type of operation (called CC_OP). When the 213 * condition codes are needed, the condition codes can be calculated 214 * using this information. Condition codes are not generated if they 215 * are only needed for conditional branches. 216 */ 217 typedef enum { 218 /* Translator only -- use env->cc_op. */ 219 CC_OP_DYNAMIC, 220 221 /* Each flag bit computed into cc_[xcnvz]. */ 222 CC_OP_FLAGS, 223 224 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 225 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 226 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 227 228 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 229 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 230 231 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 232 CC_OP_LOGIC, 233 234 CC_OP_NB 235 } CCOp; 236 237 #define CCF_C 0x01 238 #define CCF_V 0x02 239 #define CCF_Z 0x04 240 #define CCF_N 0x08 241 #define CCF_X 0x10 242 243 #define SR_I_SHIFT 8 244 #define SR_I 0x0700 245 #define SR_M 0x1000 246 #define SR_S 0x2000 247 #define SR_T_SHIFT 14 248 #define SR_T 0xc000 249 250 #define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT) 251 #define M68K_SR_TRACE_ANY_INS 0x2 252 253 #define M68K_SSP 0 254 #define M68K_USP 1 255 #define M68K_ISP 2 256 257 /* bits for 68040 special status word */ 258 #define M68K_CP_040 0x8000 259 #define M68K_CU_040 0x4000 260 #define M68K_CT_040 0x2000 261 #define M68K_CM_040 0x1000 262 #define M68K_MA_040 0x0800 263 #define M68K_ATC_040 0x0400 264 #define M68K_LK_040 0x0200 265 #define M68K_RW_040 0x0100 266 #define M68K_SIZ_040 0x0060 267 #define M68K_TT_040 0x0018 268 #define M68K_TM_040 0x0007 269 270 #define M68K_TM_040_DATA 0x0001 271 #define M68K_TM_040_CODE 0x0002 272 #define M68K_TM_040_SUPER 0x0004 273 274 /* bits for 68040 write back status word */ 275 #define M68K_WBV_040 0x80 276 #define M68K_WBSIZ_040 0x60 277 #define M68K_WBBYT_040 0x20 278 #define M68K_WBWRD_040 0x40 279 #define M68K_WBLNG_040 0x00 280 #define M68K_WBTT_040 0x18 281 #define M68K_WBTM_040 0x07 282 283 /* bus access size codes */ 284 #define M68K_BA_SIZE_MASK 0x60 285 #define M68K_BA_SIZE_BYTE 0x20 286 #define M68K_BA_SIZE_WORD 0x40 287 #define M68K_BA_SIZE_LONG 0x00 288 #define M68K_BA_SIZE_LINE 0x60 289 290 /* bus access transfer type codes */ 291 #define M68K_BA_TT_MOVE16 0x08 292 293 /* bits for 68040 MMU status register (mmusr) */ 294 #define M68K_MMU_B_040 0x0800 295 #define M68K_MMU_G_040 0x0400 296 #define M68K_MMU_U1_040 0x0200 297 #define M68K_MMU_U0_040 0x0100 298 #define M68K_MMU_S_040 0x0080 299 #define M68K_MMU_CM_040 0x0060 300 #define M68K_MMU_M_040 0x0010 301 #define M68K_MMU_WP_040 0x0004 302 #define M68K_MMU_T_040 0x0002 303 #define M68K_MMU_R_040 0x0001 304 305 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 306 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 307 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 308 M68K_MMU_WP_040) 309 310 /* bits for 68040 MMU Translation Control Register */ 311 #define M68K_TCR_ENABLED 0x8000 312 #define M68K_TCR_PAGE_8K 0x4000 313 314 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 315 #define M68K_DESC_WRITEPROT 0x00000004 316 #define M68K_DESC_USED 0x00000008 317 #define M68K_DESC_MODIFIED 0x00000010 318 #define M68K_DESC_CACHEMODE 0x00000060 319 #define M68K_DESC_CM_WRTHRU 0x00000000 320 #define M68K_DESC_CM_COPYBK 0x00000020 321 #define M68K_DESC_CM_SERIAL 0x00000040 322 #define M68K_DESC_CM_NCACHE 0x00000060 323 #define M68K_DESC_SUPERONLY 0x00000080 324 #define M68K_DESC_USERATTR 0x00000300 325 #define M68K_DESC_USERATTR_SHIFT 8 326 #define M68K_DESC_GLOBAL 0x00000400 327 #define M68K_DESC_URESERVED 0x00000800 328 329 #define M68K_ROOT_POINTER_ENTRIES 128 330 #define M68K_4K_PAGE_MASK (~0xff) 331 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 332 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 333 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 334 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 335 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 336 #define M68K_8K_PAGE_MASK (~0x7f) 337 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 338 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 339 #define M68K_UDT_VALID(entry) (entry & 2) 340 #define M68K_PDT_VALID(entry) (entry & 3) 341 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 342 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 343 #define M68K_TTS_POINTER_SHIFT 18 344 #define M68K_TTS_ROOT_SHIFT 25 345 346 /* bits for 68040 MMU Transparent Translation Registers */ 347 #define M68K_TTR_ADDR_BASE 0xff000000 348 #define M68K_TTR_ADDR_MASK 0x00ff0000 349 #define M68K_TTR_ADDR_MASK_SHIFT 8 350 #define M68K_TTR_ENABLED 0x00008000 351 #define M68K_TTR_SFIELD 0x00006000 352 #define M68K_TTR_SFIELD_USER 0x0000 353 #define M68K_TTR_SFIELD_SUPER 0x2000 354 355 /* m68k Control Registers */ 356 357 /* ColdFire */ 358 /* Memory Management Control Registers */ 359 #define M68K_CR_ASID 0x003 360 #define M68K_CR_ACR0 0x004 361 #define M68K_CR_ACR1 0x005 362 #define M68K_CR_ACR2 0x006 363 #define M68K_CR_ACR3 0x007 364 #define M68K_CR_MMUBAR 0x008 365 366 /* Processor Miscellaneous Registers */ 367 #define M68K_CR_PC 0x80F 368 369 /* Local Memory and Module Control Registers */ 370 #define M68K_CR_ROMBAR0 0xC00 371 #define M68K_CR_ROMBAR1 0xC01 372 #define M68K_CR_RAMBAR0 0xC04 373 #define M68K_CR_RAMBAR1 0xC05 374 #define M68K_CR_MPCR 0xC0C 375 #define M68K_CR_EDRAMBAR 0xC0D 376 #define M68K_CR_SECMBAR 0xC0E 377 #define M68K_CR_MBAR 0xC0F 378 379 /* Local Memory Address Permutation Control Registers */ 380 #define M68K_CR_PCR1U0 0xD02 381 #define M68K_CR_PCR1L0 0xD03 382 #define M68K_CR_PCR2U0 0xD04 383 #define M68K_CR_PCR2L0 0xD05 384 #define M68K_CR_PCR3U0 0xD06 385 #define M68K_CR_PCR3L0 0xD07 386 #define M68K_CR_PCR1U1 0xD0A 387 #define M68K_CR_PCR1L1 0xD0B 388 #define M68K_CR_PCR2U1 0xD0C 389 #define M68K_CR_PCR2L1 0xD0D 390 #define M68K_CR_PCR3U1 0xD0E 391 #define M68K_CR_PCR3L1 0xD0F 392 393 /* MC680x0 */ 394 /* MC680[1234]0/CPU32 */ 395 #define M68K_CR_SFC 0x000 396 #define M68K_CR_DFC 0x001 397 #define M68K_CR_USP 0x800 398 #define M68K_CR_VBR 0x801 /* + Coldfire */ 399 400 /* MC680[234]0 */ 401 #define M68K_CR_CACR 0x002 /* + Coldfire */ 402 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 403 #define M68K_CR_MSP 0x803 404 #define M68K_CR_ISP 0x804 405 406 /* MC68040/MC68LC040 */ 407 #define M68K_CR_TC 0x003 408 #define M68K_CR_ITT0 0x004 409 #define M68K_CR_ITT1 0x005 410 #define M68K_CR_DTT0 0x006 411 #define M68K_CR_DTT1 0x007 412 #define M68K_CR_MMUSR 0x805 413 #define M68K_CR_URP 0x806 414 #define M68K_CR_SRP 0x807 415 416 /* MC68EC040 */ 417 #define M68K_CR_IACR0 0x004 418 #define M68K_CR_IACR1 0x005 419 #define M68K_CR_DACR0 0x006 420 #define M68K_CR_DACR1 0x007 421 422 /* MC68060 */ 423 #define M68K_CR_BUSCR 0x008 424 #define M68K_CR_PCR 0x808 425 426 #define M68K_FPIAR_SHIFT 0 427 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 428 #define M68K_FPSR_SHIFT 1 429 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 430 #define M68K_FPCR_SHIFT 2 431 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 432 433 /* Floating-Point Status Register */ 434 435 /* Condition Code */ 436 #define FPSR_CC_MASK 0x0f000000 437 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 438 #define FPSR_CC_I 0x02000000 /* Infinity */ 439 #define FPSR_CC_Z 0x04000000 /* Zero */ 440 #define FPSR_CC_N 0x08000000 /* Negative */ 441 442 /* Quotient */ 443 444 #define FPSR_QT_MASK 0x00ff0000 445 #define FPSR_QT_SHIFT 16 446 447 /* Floating-Point Control Register */ 448 /* Rounding mode */ 449 #define FPCR_RND_MASK 0x0030 450 #define FPCR_RND_N 0x0000 451 #define FPCR_RND_Z 0x0010 452 #define FPCR_RND_M 0x0020 453 #define FPCR_RND_P 0x0030 454 455 /* Rounding precision */ 456 #define FPCR_PREC_MASK 0x00c0 457 #define FPCR_PREC_X 0x0000 458 #define FPCR_PREC_S 0x0040 459 #define FPCR_PREC_D 0x0080 460 #define FPCR_PREC_U 0x00c0 461 462 #define FPCR_EXCP_MASK 0xff00 463 464 /* CACR fields are implementation defined, but some bits are common. */ 465 #define M68K_CACR_EUSP 0x10 466 467 #define MACSR_PAV0 0x100 468 #define MACSR_OMC 0x080 469 #define MACSR_SU 0x040 470 #define MACSR_FI 0x020 471 #define MACSR_RT 0x010 472 #define MACSR_N 0x008 473 #define MACSR_Z 0x004 474 #define MACSR_V 0x002 475 #define MACSR_EV 0x001 476 477 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 478 void m68k_switch_sp(CPUM68KState *env); 479 480 void do_m68k_semihosting(CPUM68KState *env, int nr); 481 482 /* 483 * The 68000 family is defined in six main CPU classes, the 680[012346]0. 484 * Generally each successive CPU adds enhanced data/stack/instructions. 485 * However, some features are only common to one, or a few classes. 486 * The features cover those subsets of instructions. 487 * 488 * CPU32/32+ are basically 680010 compatible with some 68020 class 489 * instructions, and some additional CPU32 instructions. Mostly Supervisor 490 * state differences. 491 * 492 * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu. 493 * There are 4 ColdFire core ISA revisions: A, A+, B and C. 494 * Each feature covers the subset of instructions common to the 495 * ISA revisions mentioned. 496 */ 497 498 enum m68k_features { 499 /* Base Motorola CPU set (not set for Coldfire CPUs) */ 500 M68K_FEATURE_M68K, 501 /* Motorola CPU feature sets */ 502 M68K_FEATURE_M68010, 503 M68K_FEATURE_M68020, 504 M68K_FEATURE_M68030, 505 M68K_FEATURE_M68040, 506 M68K_FEATURE_M68060, 507 /* Base Coldfire set Rev A. */ 508 M68K_FEATURE_CF_ISA_A, 509 /* (ISA B or C). */ 510 M68K_FEATURE_CF_ISA_B, 511 /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 512 M68K_FEATURE_CF_ISA_APLUSC, 513 /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ 514 M68K_FEATURE_BRAL, 515 M68K_FEATURE_CF_FPU, 516 M68K_FEATURE_CF_MAC, 517 M68K_FEATURE_CF_EMAC, 518 /* Revision B EMAC (dual accumulate). */ 519 M68K_FEATURE_CF_EMAC_B, 520 /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ 521 M68K_FEATURE_USP, 522 /* Master Stack Pointer. (680[234]0) */ 523 M68K_FEATURE_MSP, 524 /* 68020+ full extension word. */ 525 M68K_FEATURE_EXT_FULL, 526 /* word sized address index registers. */ 527 M68K_FEATURE_WORD_INDEX, 528 /* scaled address index registers. */ 529 M68K_FEATURE_SCALED_INDEX, 530 /* 32 bit mul/div. (680[2346]0, and CPU32) */ 531 M68K_FEATURE_LONG_MULDIV, 532 /* 64 bit mul/div. (680[2346]0, and CPU32) */ 533 M68K_FEATURE_QUAD_MULDIV, 534 /* Bcc with Long branches. (680[2346]0, and CPU32) */ 535 M68K_FEATURE_BCCL, 536 /* BFxxx Bit field insns. (680[2346]0) */ 537 M68K_FEATURE_BITFIELD, 538 /* fpu insn. (680[46]0) */ 539 M68K_FEATURE_FPU, 540 /* CAS/CAS2[WL] insns. (680[2346]0) */ 541 M68K_FEATURE_CAS, 542 /* BKPT insn. (680[12346]0, and CPU32) */ 543 M68K_FEATURE_BKPT, 544 /* RTD insn. (680[12346]0, and CPU32) */ 545 M68K_FEATURE_RTD, 546 /* CHK2 insn. (680[2346]0, and CPU32) */ 547 M68K_FEATURE_CHK2, 548 /* MOVEP insn. (680[01234]0, and CPU32) */ 549 M68K_FEATURE_MOVEP, 550 /* MOVEC insn. (from 68010) */ 551 M68K_FEATURE_MOVEC, 552 /* Unaligned data accesses (680[2346]0) */ 553 M68K_FEATURE_UNALIGNED_DATA, 554 /* TRAPcc insn. (680[2346]0, and CPU32) */ 555 M68K_FEATURE_TRAPCC, 556 /* MOVE from SR privileged (from 68010) */ 557 M68K_FEATURE_MOVEFROMSR_PRIV, 558 /* Exception frame with format+vector (from 68010) */ 559 M68K_FEATURE_EXCEPTION_FORMAT_VEC, 560 }; 561 562 static inline bool m68k_feature(CPUM68KState *env, int feature) 563 { 564 return (env->features & BIT_ULL(feature)) != 0; 565 } 566 567 void register_m68k_insns (CPUM68KState *env); 568 569 enum { 570 /* 1 bit to define user level / supervisor access */ 571 ACCESS_SUPER = 0x01, 572 /* 1 bit to indicate direction */ 573 ACCESS_STORE = 0x02, 574 /* 1 bit to indicate debug access */ 575 ACCESS_DEBUG = 0x04, 576 /* PTEST instruction */ 577 ACCESS_PTEST = 0x08, 578 /* Type of instruction that generated the access */ 579 ACCESS_CODE = 0x10, /* Code fetch access */ 580 ACCESS_DATA = 0x20, /* Data load/store access */ 581 }; 582 583 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 584 585 /* MMU modes definitions */ 586 #define MMU_KERNEL_IDX 0 587 #define MMU_USER_IDX 1 588 589 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 590 MMUAccessType access_type, int mmu_idx, 591 bool probe, uintptr_t retaddr); 592 #ifndef CONFIG_USER_ONLY 593 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 594 unsigned size, MMUAccessType access_type, 595 int mmu_idx, MemTxAttrs attrs, 596 MemTxResult response, uintptr_t retaddr); 597 #endif 598 599 /* TB flags */ 600 #define TB_FLAGS_MACSR 0x0f 601 #define TB_FLAGS_MSR_S_BIT 13 602 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 603 #define TB_FLAGS_SFC_S_BIT 14 604 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 605 #define TB_FLAGS_DFC_S_BIT 15 606 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 607 #define TB_FLAGS_TRACE 16 608 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) 609 610 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, 611 uint64_t *cs_base, uint32_t *flags) 612 { 613 *pc = env->pc; 614 *cs_base = 0; 615 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 616 if (env->sr & SR_S) { 617 *flags |= TB_FLAGS_MSR_S; 618 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 619 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 620 } 621 if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { 622 *flags |= TB_FLAGS_TRACE; 623 } 624 } 625 626 void dump_mmu(CPUM68KState *env); 627 628 #endif 629