1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "qemu-common.h" 25 #include "exec/cpu-defs.h" 26 #include "cpu-qom.h" 27 28 #define OS_BYTE 0 29 #define OS_WORD 1 30 #define OS_LONG 2 31 #define OS_SINGLE 3 32 #define OS_DOUBLE 4 33 #define OS_EXTENDED 5 34 #define OS_PACKED 6 35 #define OS_UNSIZED 7 36 37 #define MAX_QREGS 32 38 39 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 40 #define EXCP_ADDRESS 3 /* Address error. */ 41 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 42 #define EXCP_DIV0 5 /* Divide by zero */ 43 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 44 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 45 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 46 #define EXCP_TRACE 9 47 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 48 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 49 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 50 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 51 #define EXCP_FORMAT 14 /* RTE format error. */ 52 #define EXCP_UNINITIALIZED 15 53 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 54 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 55 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 56 #define EXCP_TRAP0 32 /* User trap #0. */ 57 #define EXCP_TRAP15 47 /* User trap #15. */ 58 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 59 #define EXCP_FP_INEX 49 /* Inexact result */ 60 #define EXCP_FP_DZ 50 /* Divide by Zero */ 61 #define EXCP_FP_UNFL 51 /* Underflow */ 62 #define EXCP_FP_OPERR 52 /* Operand Error */ 63 #define EXCP_FP_OVFL 53 /* Overflow */ 64 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 65 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 66 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 67 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 68 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 69 70 #define EXCP_RTE 0x100 71 #define EXCP_HALT_INSN 0x101 72 73 #define M68K_DTTR0 0 74 #define M68K_DTTR1 1 75 #define M68K_ITTR0 2 76 #define M68K_ITTR1 3 77 78 #define M68K_MAX_TTR 2 79 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 80 81 #define TARGET_INSN_START_EXTRA_WORDS 1 82 83 typedef CPU_LDoubleU FPReg; 84 85 typedef struct CPUM68KState { 86 uint32_t dregs[8]; 87 uint32_t aregs[8]; 88 uint32_t pc; 89 uint32_t sr; 90 91 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ 92 int current_sp; 93 uint32_t sp[3]; 94 95 /* Condition flags. */ 96 uint32_t cc_op; 97 uint32_t cc_x; /* always 0/1 */ 98 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 99 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 100 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 101 uint32_t cc_z; /* == 0 or unused */ 102 103 FPReg fregs[8]; 104 FPReg fp_result; 105 uint32_t fpcr; 106 uint32_t fpsr; 107 float_status fp_status; 108 109 uint64_t mactmp; 110 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and 111 two 8-bit parts. We store a single 64-bit value and 112 rearrange/extend this when changing modes. */ 113 uint64_t macc[4]; 114 uint32_t macsr; 115 uint32_t mac_mask; 116 117 /* MMU status. */ 118 struct { 119 uint32_t ar; 120 uint32_t ssw; 121 /* 68040 */ 122 uint16_t tcr; 123 uint32_t urp; 124 uint32_t srp; 125 bool fault; 126 uint32_t ttr[4]; 127 uint32_t mmusr; 128 } mmu; 129 130 /* Control registers. */ 131 uint32_t vbr; 132 uint32_t mbar; 133 uint32_t rambar0; 134 uint32_t cacr; 135 uint32_t sfc; 136 uint32_t dfc; 137 138 int pending_vector; 139 int pending_level; 140 141 uint32_t qregs[MAX_QREGS]; 142 143 /* Fields up to this point are cleared by a CPU reset */ 144 struct {} end_reset_fields; 145 146 /* Fields from here on are preserved across CPU reset. */ 147 uint32_t features; 148 } CPUM68KState; 149 150 /** 151 * M68kCPU: 152 * @env: #CPUM68KState 153 * 154 * A Motorola 68k CPU. 155 */ 156 struct M68kCPU { 157 /*< private >*/ 158 CPUState parent_obj; 159 /*< public >*/ 160 161 CPUNegativeOffsetState neg; 162 CPUM68KState env; 163 }; 164 165 166 void m68k_cpu_do_interrupt(CPUState *cpu); 167 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 168 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 169 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 170 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 171 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 172 173 void m68k_tcg_init(void); 174 void m68k_cpu_init_gdb(M68kCPU *cpu); 175 /* you can call this signal handler from your SIGBUS and SIGSEGV 176 signal handlers to inform the virtual CPU of exceptions. non zero 177 is returned if the signal was handled by the virtual CPU. */ 178 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 179 void *puc); 180 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 181 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 182 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 183 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 184 185 186 /* Instead of computing the condition codes after each m68k instruction, 187 * QEMU just stores one operand (called CC_SRC), the result 188 * (called CC_DEST) and the type of operation (called CC_OP). When the 189 * condition codes are needed, the condition codes can be calculated 190 * using this information. Condition codes are not generated if they 191 * are only needed for conditional branches. 192 */ 193 typedef enum { 194 /* Translator only -- use env->cc_op. */ 195 CC_OP_DYNAMIC, 196 197 /* Each flag bit computed into cc_[xcnvz]. */ 198 CC_OP_FLAGS, 199 200 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 201 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 202 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 203 204 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 205 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 206 207 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 208 CC_OP_LOGIC, 209 210 CC_OP_NB 211 } CCOp; 212 213 #define CCF_C 0x01 214 #define CCF_V 0x02 215 #define CCF_Z 0x04 216 #define CCF_N 0x08 217 #define CCF_X 0x10 218 219 #define SR_I_SHIFT 8 220 #define SR_I 0x0700 221 #define SR_M 0x1000 222 #define SR_S 0x2000 223 #define SR_T_SHIFT 14 224 #define SR_T 0xc000 225 226 #define M68K_SSP 0 227 #define M68K_USP 1 228 #define M68K_ISP 2 229 230 /* bits for 68040 special status word */ 231 #define M68K_CP_040 0x8000 232 #define M68K_CU_040 0x4000 233 #define M68K_CT_040 0x2000 234 #define M68K_CM_040 0x1000 235 #define M68K_MA_040 0x0800 236 #define M68K_ATC_040 0x0400 237 #define M68K_LK_040 0x0200 238 #define M68K_RW_040 0x0100 239 #define M68K_SIZ_040 0x0060 240 #define M68K_TT_040 0x0018 241 #define M68K_TM_040 0x0007 242 243 #define M68K_TM_040_DATA 0x0001 244 #define M68K_TM_040_CODE 0x0002 245 #define M68K_TM_040_SUPER 0x0004 246 247 /* bits for 68040 write back status word */ 248 #define M68K_WBV_040 0x80 249 #define M68K_WBSIZ_040 0x60 250 #define M68K_WBBYT_040 0x20 251 #define M68K_WBWRD_040 0x40 252 #define M68K_WBLNG_040 0x00 253 #define M68K_WBTT_040 0x18 254 #define M68K_WBTM_040 0x07 255 256 /* bus access size codes */ 257 #define M68K_BA_SIZE_MASK 0x60 258 #define M68K_BA_SIZE_BYTE 0x20 259 #define M68K_BA_SIZE_WORD 0x40 260 #define M68K_BA_SIZE_LONG 0x00 261 #define M68K_BA_SIZE_LINE 0x60 262 263 /* bus access transfer type codes */ 264 #define M68K_BA_TT_MOVE16 0x08 265 266 /* bits for 68040 MMU status register (mmusr) */ 267 #define M68K_MMU_B_040 0x0800 268 #define M68K_MMU_G_040 0x0400 269 #define M68K_MMU_U1_040 0x0200 270 #define M68K_MMU_U0_040 0x0100 271 #define M68K_MMU_S_040 0x0080 272 #define M68K_MMU_CM_040 0x0060 273 #define M68K_MMU_M_040 0x0010 274 #define M68K_MMU_WP_040 0x0004 275 #define M68K_MMU_T_040 0x0002 276 #define M68K_MMU_R_040 0x0001 277 278 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 279 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 280 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 281 M68K_MMU_WP_040) 282 283 /* bits for 68040 MMU Translation Control Register */ 284 #define M68K_TCR_ENABLED 0x8000 285 #define M68K_TCR_PAGE_8K 0x4000 286 287 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 288 #define M68K_DESC_WRITEPROT 0x00000004 289 #define M68K_DESC_USED 0x00000008 290 #define M68K_DESC_MODIFIED 0x00000010 291 #define M68K_DESC_CACHEMODE 0x00000060 292 #define M68K_DESC_CM_WRTHRU 0x00000000 293 #define M68K_DESC_CM_COPYBK 0x00000020 294 #define M68K_DESC_CM_SERIAL 0x00000040 295 #define M68K_DESC_CM_NCACHE 0x00000060 296 #define M68K_DESC_SUPERONLY 0x00000080 297 #define M68K_DESC_USERATTR 0x00000300 298 #define M68K_DESC_USERATTR_SHIFT 8 299 #define M68K_DESC_GLOBAL 0x00000400 300 #define M68K_DESC_URESERVED 0x00000800 301 302 #define M68K_ROOT_POINTER_ENTRIES 128 303 #define M68K_4K_PAGE_MASK (~0xff) 304 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 305 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 306 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 307 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 308 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 309 #define M68K_8K_PAGE_MASK (~0x7f) 310 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 311 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 312 #define M68K_UDT_VALID(entry) (entry & 2) 313 #define M68K_PDT_VALID(entry) (entry & 3) 314 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 315 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 316 #define M68K_TTS_POINTER_SHIFT 18 317 #define M68K_TTS_ROOT_SHIFT 25 318 319 /* bits for 68040 MMU Transparent Translation Registers */ 320 #define M68K_TTR_ADDR_BASE 0xff000000 321 #define M68K_TTR_ADDR_MASK 0x00ff0000 322 #define M68K_TTR_ADDR_MASK_SHIFT 8 323 #define M68K_TTR_ENABLED 0x00008000 324 #define M68K_TTR_SFIELD 0x00006000 325 #define M68K_TTR_SFIELD_USER 0x0000 326 #define M68K_TTR_SFIELD_SUPER 0x2000 327 328 /* m68k Control Registers */ 329 330 /* ColdFire */ 331 /* Memory Management Control Registers */ 332 #define M68K_CR_ASID 0x003 333 #define M68K_CR_ACR0 0x004 334 #define M68K_CR_ACR1 0x005 335 #define M68K_CR_ACR2 0x006 336 #define M68K_CR_ACR3 0x007 337 #define M68K_CR_MMUBAR 0x008 338 339 /* Processor Miscellaneous Registers */ 340 #define M68K_CR_PC 0x80F 341 342 /* Local Memory and Module Control Registers */ 343 #define M68K_CR_ROMBAR0 0xC00 344 #define M68K_CR_ROMBAR1 0xC01 345 #define M68K_CR_RAMBAR0 0xC04 346 #define M68K_CR_RAMBAR1 0xC05 347 #define M68K_CR_MPCR 0xC0C 348 #define M68K_CR_EDRAMBAR 0xC0D 349 #define M68K_CR_SECMBAR 0xC0E 350 #define M68K_CR_MBAR 0xC0F 351 352 /* Local Memory Address Permutation Control Registers */ 353 #define M68K_CR_PCR1U0 0xD02 354 #define M68K_CR_PCR1L0 0xD03 355 #define M68K_CR_PCR2U0 0xD04 356 #define M68K_CR_PCR2L0 0xD05 357 #define M68K_CR_PCR3U0 0xD06 358 #define M68K_CR_PCR3L0 0xD07 359 #define M68K_CR_PCR1U1 0xD0A 360 #define M68K_CR_PCR1L1 0xD0B 361 #define M68K_CR_PCR2U1 0xD0C 362 #define M68K_CR_PCR2L1 0xD0D 363 #define M68K_CR_PCR3U1 0xD0E 364 #define M68K_CR_PCR3L1 0xD0F 365 366 /* MC680x0 */ 367 /* MC680[1234]0/CPU32 */ 368 #define M68K_CR_SFC 0x000 369 #define M68K_CR_DFC 0x001 370 #define M68K_CR_USP 0x800 371 #define M68K_CR_VBR 0x801 /* + Coldfire */ 372 373 /* MC680[234]0 */ 374 #define M68K_CR_CACR 0x002 /* + Coldfire */ 375 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 376 #define M68K_CR_MSP 0x803 377 #define M68K_CR_ISP 0x804 378 379 /* MC68040/MC68LC040 */ 380 #define M68K_CR_TC 0x003 381 #define M68K_CR_ITT0 0x004 382 #define M68K_CR_ITT1 0x005 383 #define M68K_CR_DTT0 0x006 384 #define M68K_CR_DTT1 0x007 385 #define M68K_CR_MMUSR 0x805 386 #define M68K_CR_URP 0x806 387 #define M68K_CR_SRP 0x807 388 389 /* MC68EC040 */ 390 #define M68K_CR_IACR0 0x004 391 #define M68K_CR_IACR1 0x005 392 #define M68K_CR_DACR0 0x006 393 #define M68K_CR_DACR1 0x007 394 395 #define M68K_FPIAR_SHIFT 0 396 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 397 #define M68K_FPSR_SHIFT 1 398 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 399 #define M68K_FPCR_SHIFT 2 400 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 401 402 /* Floating-Point Status Register */ 403 404 /* Condition Code */ 405 #define FPSR_CC_MASK 0x0f000000 406 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 407 #define FPSR_CC_I 0x02000000 /* Infinity */ 408 #define FPSR_CC_Z 0x04000000 /* Zero */ 409 #define FPSR_CC_N 0x08000000 /* Negative */ 410 411 /* Quotient */ 412 413 #define FPSR_QT_MASK 0x00ff0000 414 #define FPSR_QT_SHIFT 16 415 416 /* Floating-Point Control Register */ 417 /* Rounding mode */ 418 #define FPCR_RND_MASK 0x0030 419 #define FPCR_RND_N 0x0000 420 #define FPCR_RND_Z 0x0010 421 #define FPCR_RND_M 0x0020 422 #define FPCR_RND_P 0x0030 423 424 /* Rounding precision */ 425 #define FPCR_PREC_MASK 0x00c0 426 #define FPCR_PREC_X 0x0000 427 #define FPCR_PREC_S 0x0040 428 #define FPCR_PREC_D 0x0080 429 #define FPCR_PREC_U 0x00c0 430 431 #define FPCR_EXCP_MASK 0xff00 432 433 /* CACR fields are implementation defined, but some bits are common. */ 434 #define M68K_CACR_EUSP 0x10 435 436 #define MACSR_PAV0 0x100 437 #define MACSR_OMC 0x080 438 #define MACSR_SU 0x040 439 #define MACSR_FI 0x020 440 #define MACSR_RT 0x010 441 #define MACSR_N 0x008 442 #define MACSR_Z 0x004 443 #define MACSR_V 0x002 444 #define MACSR_EV 0x001 445 446 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 447 void m68k_switch_sp(CPUM68KState *env); 448 449 void do_m68k_semihosting(CPUM68KState *env, int nr); 450 451 /* There are 4 ColdFire core ISA revisions: A, A+, B and C. 452 Each feature covers the subset of instructions common to the 453 ISA revisions mentioned. */ 454 455 enum m68k_features { 456 M68K_FEATURE_M68000, 457 M68K_FEATURE_CF_ISA_A, 458 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 459 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 460 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ 461 M68K_FEATURE_CF_FPU, 462 M68K_FEATURE_CF_MAC, 463 M68K_FEATURE_CF_EMAC, 464 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 465 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ 466 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 467 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 468 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 469 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ 470 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ 471 M68K_FEATURE_BCCL, /* Long conditional branches. */ 472 M68K_FEATURE_BITFIELD, /* Bit field insns. */ 473 M68K_FEATURE_FPU, 474 M68K_FEATURE_CAS, 475 M68K_FEATURE_BKPT, 476 M68K_FEATURE_RTD, 477 M68K_FEATURE_CHK2, 478 M68K_FEATURE_M68040, /* instructions specific to MC68040 */ 479 M68K_FEATURE_MOVEP, 480 }; 481 482 static inline int m68k_feature(CPUM68KState *env, int feature) 483 { 484 return (env->features & (1u << feature)) != 0; 485 } 486 487 void m68k_cpu_list(void); 488 489 void register_m68k_insns (CPUM68KState *env); 490 491 enum { 492 /* 1 bit to define user level / supervisor access */ 493 ACCESS_SUPER = 0x01, 494 /* 1 bit to indicate direction */ 495 ACCESS_STORE = 0x02, 496 /* 1 bit to indicate debug access */ 497 ACCESS_DEBUG = 0x04, 498 /* PTEST instruction */ 499 ACCESS_PTEST = 0x08, 500 /* Type of instruction that generated the access */ 501 ACCESS_CODE = 0x10, /* Code fetch access */ 502 ACCESS_DATA = 0x20, /* Data load/store access */ 503 }; 504 505 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 506 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 507 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 508 509 #define cpu_signal_handler cpu_m68k_signal_handler 510 #define cpu_list m68k_cpu_list 511 512 /* MMU modes definitions */ 513 #define MMU_MODE0_SUFFIX _kernel 514 #define MMU_MODE1_SUFFIX _user 515 #define MMU_KERNEL_IDX 0 516 #define MMU_USER_IDX 1 517 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 518 { 519 return (env->sr & SR_S) == 0 ? 1 : 0; 520 } 521 522 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 523 MMUAccessType access_type, int mmu_idx, 524 bool probe, uintptr_t retaddr); 525 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 526 unsigned size, MMUAccessType access_type, 527 int mmu_idx, MemTxAttrs attrs, 528 MemTxResult response, uintptr_t retaddr); 529 530 typedef CPUM68KState CPUArchState; 531 typedef M68kCPU ArchCPU; 532 533 #include "exec/cpu-all.h" 534 535 /* TB flags */ 536 #define TB_FLAGS_MACSR 0x0f 537 #define TB_FLAGS_MSR_S_BIT 13 538 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 539 #define TB_FLAGS_SFC_S_BIT 14 540 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 541 #define TB_FLAGS_DFC_S_BIT 15 542 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 543 544 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 545 target_ulong *cs_base, uint32_t *flags) 546 { 547 *pc = env->pc; 548 *cs_base = 0; 549 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 550 if (env->sr & SR_S) { 551 *flags |= TB_FLAGS_MSR_S; 552 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 553 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 554 } 555 } 556 557 void dump_mmu(CPUM68KState *env); 558 559 #endif 560