1 /* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef M68K_CPU_H 22 #define M68K_CPU_H 23 24 #include "exec/cpu-defs.h" 25 #include "cpu-qom.h" 26 27 #define OS_BYTE 0 28 #define OS_WORD 1 29 #define OS_LONG 2 30 #define OS_SINGLE 3 31 #define OS_DOUBLE 4 32 #define OS_EXTENDED 5 33 #define OS_PACKED 6 34 #define OS_UNSIZED 7 35 36 #define EXCP_ACCESS 2 /* Access (MMU) error. */ 37 #define EXCP_ADDRESS 3 /* Address error. */ 38 #define EXCP_ILLEGAL 4 /* Illegal instruction. */ 39 #define EXCP_DIV0 5 /* Divide by zero */ 40 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 41 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 42 #define EXCP_PRIVILEGE 8 /* Privilege violation. */ 43 #define EXCP_TRACE 9 44 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 45 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 46 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 47 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 48 #define EXCP_FORMAT 14 /* RTE format error. */ 49 #define EXCP_UNINITIALIZED 15 50 #define EXCP_SPURIOUS 24 /* Spurious interrupt */ 51 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 52 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 53 #define EXCP_TRAP0 32 /* User trap #0. */ 54 #define EXCP_TRAP15 47 /* User trap #15. */ 55 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 56 #define EXCP_FP_INEX 49 /* Inexact result */ 57 #define EXCP_FP_DZ 50 /* Divide by Zero */ 58 #define EXCP_FP_UNFL 51 /* Underflow */ 59 #define EXCP_FP_OPERR 52 /* Operand Error */ 60 #define EXCP_FP_OVFL 53 /* Overflow */ 61 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 62 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 63 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 64 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 65 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 66 67 #define EXCP_RTE 0x100 68 #define EXCP_HALT_INSN 0x101 69 70 #define M68K_DTTR0 0 71 #define M68K_DTTR1 1 72 #define M68K_ITTR0 2 73 #define M68K_ITTR1 3 74 75 #define M68K_MAX_TTR 2 76 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 77 78 #define TARGET_INSN_START_EXTRA_WORDS 1 79 80 typedef CPU_LDoubleU FPReg; 81 82 typedef struct CPUM68KState { 83 uint32_t dregs[8]; 84 uint32_t aregs[8]; 85 uint32_t pc; 86 uint32_t sr; 87 88 /* 89 * The 68020/30/40 support two supervisor stacks, ISP and MSP. 90 * The 68000/10, Coldfire, and CPU32 only have USP/SSP. 91 * 92 * The current_sp is stored in aregs[7], the other here. 93 * The USP, SSP, and if used the additional ISP for 68020/30/40. 94 */ 95 int current_sp; 96 uint32_t sp[3]; 97 98 /* Condition flags. */ 99 uint32_t cc_op; 100 uint32_t cc_x; /* always 0/1 */ 101 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 102 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 103 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 104 uint32_t cc_z; /* == 0 or unused */ 105 106 FPReg fregs[8]; 107 FPReg fp_result; 108 uint32_t fpcr; 109 uint32_t fpsr; 110 float_status fp_status; 111 112 uint64_t mactmp; 113 /* 114 * EMAC Hardware deals with 48-bit values composed of one 32-bit and 115 * two 8-bit parts. We store a single 64-bit value and 116 * rearrange/extend this when changing modes. 117 */ 118 uint64_t macc[4]; 119 uint32_t macsr; 120 uint32_t mac_mask; 121 122 /* MMU status. */ 123 struct { 124 uint32_t ar; 125 uint32_t ssw; 126 /* 68040 */ 127 uint16_t tcr; 128 uint32_t urp; 129 uint32_t srp; 130 bool fault; 131 uint32_t ttr[4]; 132 uint32_t mmusr; 133 } mmu; 134 135 /* Control registers. */ 136 uint32_t vbr; 137 uint32_t mbar; 138 uint32_t rambar0; 139 uint32_t cacr; 140 uint32_t sfc; 141 uint32_t dfc; 142 143 int pending_vector; 144 int pending_level; 145 146 /* Fields up to this point are cleared by a CPU reset */ 147 struct {} end_reset_fields; 148 149 /* Fields from here on are preserved across CPU reset. */ 150 uint32_t features; 151 } CPUM68KState; 152 153 /* 154 * M68kCPU: 155 * @env: #CPUM68KState 156 * 157 * A Motorola 68k CPU. 158 */ 159 struct M68kCPU { 160 /*< private >*/ 161 CPUState parent_obj; 162 /*< public >*/ 163 164 CPUNegativeOffsetState neg; 165 CPUM68KState env; 166 }; 167 168 169 void m68k_cpu_do_interrupt(CPUState *cpu); 170 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 171 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 172 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 173 int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 174 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 175 176 void m68k_tcg_init(void); 177 void m68k_cpu_init_gdb(M68kCPU *cpu); 178 /* 179 * you can call this signal handler from your SIGBUS and SIGSEGV 180 * signal handlers to inform the virtual CPU of exceptions. non zero 181 * is returned if the signal was handled by the virtual CPU. 182 */ 183 int cpu_m68k_signal_handler(int host_signum, void *pinfo, 184 void *puc); 185 uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 186 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 187 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 188 void cpu_m68k_restore_fp_status(CPUM68KState *env); 189 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 190 191 192 /* 193 * Instead of computing the condition codes after each m68k instruction, 194 * QEMU just stores one operand (called CC_SRC), the result 195 * (called CC_DEST) and the type of operation (called CC_OP). When the 196 * condition codes are needed, the condition codes can be calculated 197 * using this information. Condition codes are not generated if they 198 * are only needed for conditional branches. 199 */ 200 typedef enum { 201 /* Translator only -- use env->cc_op. */ 202 CC_OP_DYNAMIC, 203 204 /* Each flag bit computed into cc_[xcnvz]. */ 205 CC_OP_FLAGS, 206 207 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 208 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 209 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 210 211 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 212 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 213 214 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 215 CC_OP_LOGIC, 216 217 CC_OP_NB 218 } CCOp; 219 220 #define CCF_C 0x01 221 #define CCF_V 0x02 222 #define CCF_Z 0x04 223 #define CCF_N 0x08 224 #define CCF_X 0x10 225 226 #define SR_I_SHIFT 8 227 #define SR_I 0x0700 228 #define SR_M 0x1000 229 #define SR_S 0x2000 230 #define SR_T_SHIFT 14 231 #define SR_T 0xc000 232 233 #define M68K_SSP 0 234 #define M68K_USP 1 235 #define M68K_ISP 2 236 237 /* bits for 68040 special status word */ 238 #define M68K_CP_040 0x8000 239 #define M68K_CU_040 0x4000 240 #define M68K_CT_040 0x2000 241 #define M68K_CM_040 0x1000 242 #define M68K_MA_040 0x0800 243 #define M68K_ATC_040 0x0400 244 #define M68K_LK_040 0x0200 245 #define M68K_RW_040 0x0100 246 #define M68K_SIZ_040 0x0060 247 #define M68K_TT_040 0x0018 248 #define M68K_TM_040 0x0007 249 250 #define M68K_TM_040_DATA 0x0001 251 #define M68K_TM_040_CODE 0x0002 252 #define M68K_TM_040_SUPER 0x0004 253 254 /* bits for 68040 write back status word */ 255 #define M68K_WBV_040 0x80 256 #define M68K_WBSIZ_040 0x60 257 #define M68K_WBBYT_040 0x20 258 #define M68K_WBWRD_040 0x40 259 #define M68K_WBLNG_040 0x00 260 #define M68K_WBTT_040 0x18 261 #define M68K_WBTM_040 0x07 262 263 /* bus access size codes */ 264 #define M68K_BA_SIZE_MASK 0x60 265 #define M68K_BA_SIZE_BYTE 0x20 266 #define M68K_BA_SIZE_WORD 0x40 267 #define M68K_BA_SIZE_LONG 0x00 268 #define M68K_BA_SIZE_LINE 0x60 269 270 /* bus access transfer type codes */ 271 #define M68K_BA_TT_MOVE16 0x08 272 273 /* bits for 68040 MMU status register (mmusr) */ 274 #define M68K_MMU_B_040 0x0800 275 #define M68K_MMU_G_040 0x0400 276 #define M68K_MMU_U1_040 0x0200 277 #define M68K_MMU_U0_040 0x0100 278 #define M68K_MMU_S_040 0x0080 279 #define M68K_MMU_CM_040 0x0060 280 #define M68K_MMU_M_040 0x0010 281 #define M68K_MMU_WP_040 0x0004 282 #define M68K_MMU_T_040 0x0002 283 #define M68K_MMU_R_040 0x0001 284 285 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 286 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 287 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 288 M68K_MMU_WP_040) 289 290 /* bits for 68040 MMU Translation Control Register */ 291 #define M68K_TCR_ENABLED 0x8000 292 #define M68K_TCR_PAGE_8K 0x4000 293 294 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 295 #define M68K_DESC_WRITEPROT 0x00000004 296 #define M68K_DESC_USED 0x00000008 297 #define M68K_DESC_MODIFIED 0x00000010 298 #define M68K_DESC_CACHEMODE 0x00000060 299 #define M68K_DESC_CM_WRTHRU 0x00000000 300 #define M68K_DESC_CM_COPYBK 0x00000020 301 #define M68K_DESC_CM_SERIAL 0x00000040 302 #define M68K_DESC_CM_NCACHE 0x00000060 303 #define M68K_DESC_SUPERONLY 0x00000080 304 #define M68K_DESC_USERATTR 0x00000300 305 #define M68K_DESC_USERATTR_SHIFT 8 306 #define M68K_DESC_GLOBAL 0x00000400 307 #define M68K_DESC_URESERVED 0x00000800 308 309 #define M68K_ROOT_POINTER_ENTRIES 128 310 #define M68K_4K_PAGE_MASK (~0xff) 311 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 312 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 313 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 314 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 315 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 316 #define M68K_8K_PAGE_MASK (~0x7f) 317 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 318 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 319 #define M68K_UDT_VALID(entry) (entry & 2) 320 #define M68K_PDT_VALID(entry) (entry & 3) 321 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 322 #define M68K_INDIRECT_POINTER(addr) (addr & ~3) 323 #define M68K_TTS_POINTER_SHIFT 18 324 #define M68K_TTS_ROOT_SHIFT 25 325 326 /* bits for 68040 MMU Transparent Translation Registers */ 327 #define M68K_TTR_ADDR_BASE 0xff000000 328 #define M68K_TTR_ADDR_MASK 0x00ff0000 329 #define M68K_TTR_ADDR_MASK_SHIFT 8 330 #define M68K_TTR_ENABLED 0x00008000 331 #define M68K_TTR_SFIELD 0x00006000 332 #define M68K_TTR_SFIELD_USER 0x0000 333 #define M68K_TTR_SFIELD_SUPER 0x2000 334 335 /* m68k Control Registers */ 336 337 /* ColdFire */ 338 /* Memory Management Control Registers */ 339 #define M68K_CR_ASID 0x003 340 #define M68K_CR_ACR0 0x004 341 #define M68K_CR_ACR1 0x005 342 #define M68K_CR_ACR2 0x006 343 #define M68K_CR_ACR3 0x007 344 #define M68K_CR_MMUBAR 0x008 345 346 /* Processor Miscellaneous Registers */ 347 #define M68K_CR_PC 0x80F 348 349 /* Local Memory and Module Control Registers */ 350 #define M68K_CR_ROMBAR0 0xC00 351 #define M68K_CR_ROMBAR1 0xC01 352 #define M68K_CR_RAMBAR0 0xC04 353 #define M68K_CR_RAMBAR1 0xC05 354 #define M68K_CR_MPCR 0xC0C 355 #define M68K_CR_EDRAMBAR 0xC0D 356 #define M68K_CR_SECMBAR 0xC0E 357 #define M68K_CR_MBAR 0xC0F 358 359 /* Local Memory Address Permutation Control Registers */ 360 #define M68K_CR_PCR1U0 0xD02 361 #define M68K_CR_PCR1L0 0xD03 362 #define M68K_CR_PCR2U0 0xD04 363 #define M68K_CR_PCR2L0 0xD05 364 #define M68K_CR_PCR3U0 0xD06 365 #define M68K_CR_PCR3L0 0xD07 366 #define M68K_CR_PCR1U1 0xD0A 367 #define M68K_CR_PCR1L1 0xD0B 368 #define M68K_CR_PCR2U1 0xD0C 369 #define M68K_CR_PCR2L1 0xD0D 370 #define M68K_CR_PCR3U1 0xD0E 371 #define M68K_CR_PCR3L1 0xD0F 372 373 /* MC680x0 */ 374 /* MC680[1234]0/CPU32 */ 375 #define M68K_CR_SFC 0x000 376 #define M68K_CR_DFC 0x001 377 #define M68K_CR_USP 0x800 378 #define M68K_CR_VBR 0x801 /* + Coldfire */ 379 380 /* MC680[234]0 */ 381 #define M68K_CR_CACR 0x002 /* + Coldfire */ 382 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 383 #define M68K_CR_MSP 0x803 384 #define M68K_CR_ISP 0x804 385 386 /* MC68040/MC68LC040 */ 387 #define M68K_CR_TC 0x003 388 #define M68K_CR_ITT0 0x004 389 #define M68K_CR_ITT1 0x005 390 #define M68K_CR_DTT0 0x006 391 #define M68K_CR_DTT1 0x007 392 #define M68K_CR_MMUSR 0x805 393 #define M68K_CR_URP 0x806 394 #define M68K_CR_SRP 0x807 395 396 /* MC68EC040 */ 397 #define M68K_CR_IACR0 0x004 398 #define M68K_CR_IACR1 0x005 399 #define M68K_CR_DACR0 0x006 400 #define M68K_CR_DACR1 0x007 401 402 /* MC68060 */ 403 #define M68K_CR_BUSCR 0x008 404 #define M68K_CR_PCR 0x808 405 406 #define M68K_FPIAR_SHIFT 0 407 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 408 #define M68K_FPSR_SHIFT 1 409 #define M68K_FPSR (1 << M68K_FPSR_SHIFT) 410 #define M68K_FPCR_SHIFT 2 411 #define M68K_FPCR (1 << M68K_FPCR_SHIFT) 412 413 /* Floating-Point Status Register */ 414 415 /* Condition Code */ 416 #define FPSR_CC_MASK 0x0f000000 417 #define FPSR_CC_A 0x01000000 /* Not-A-Number */ 418 #define FPSR_CC_I 0x02000000 /* Infinity */ 419 #define FPSR_CC_Z 0x04000000 /* Zero */ 420 #define FPSR_CC_N 0x08000000 /* Negative */ 421 422 /* Quotient */ 423 424 #define FPSR_QT_MASK 0x00ff0000 425 #define FPSR_QT_SHIFT 16 426 427 /* Floating-Point Control Register */ 428 /* Rounding mode */ 429 #define FPCR_RND_MASK 0x0030 430 #define FPCR_RND_N 0x0000 431 #define FPCR_RND_Z 0x0010 432 #define FPCR_RND_M 0x0020 433 #define FPCR_RND_P 0x0030 434 435 /* Rounding precision */ 436 #define FPCR_PREC_MASK 0x00c0 437 #define FPCR_PREC_X 0x0000 438 #define FPCR_PREC_S 0x0040 439 #define FPCR_PREC_D 0x0080 440 #define FPCR_PREC_U 0x00c0 441 442 #define FPCR_EXCP_MASK 0xff00 443 444 /* CACR fields are implementation defined, but some bits are common. */ 445 #define M68K_CACR_EUSP 0x10 446 447 #define MACSR_PAV0 0x100 448 #define MACSR_OMC 0x080 449 #define MACSR_SU 0x040 450 #define MACSR_FI 0x020 451 #define MACSR_RT 0x010 452 #define MACSR_N 0x008 453 #define MACSR_Z 0x004 454 #define MACSR_V 0x002 455 #define MACSR_EV 0x001 456 457 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 458 void m68k_switch_sp(CPUM68KState *env); 459 460 void do_m68k_semihosting(CPUM68KState *env, int nr); 461 462 /* 463 * The 68000 family is defined in six main CPU classes, the 680[012346]0. 464 * Generally each successive CPU adds enhanced data/stack/instructions. 465 * However, some features are only common to one, or a few classes. 466 * The features covers those subsets of instructons. 467 * 468 * CPU32/32+ are basically 680010 compatible with some 68020 class instructons, 469 * and some additional CPU32 instructions. Mostly Supervisor state differences. 470 * 471 * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu. 472 * There are 4 ColdFire core ISA revisions: A, A+, B and C. 473 * Each feature covers the subset of instructions common to the 474 * ISA revisions mentioned. 475 */ 476 477 enum m68k_features { 478 M68K_FEATURE_M68000, /* Base m68k instruction set */ 479 M68K_FEATURE_M68010, 480 M68K_FEATURE_M68020, 481 M68K_FEATURE_M68030, 482 M68K_FEATURE_M68040, 483 M68K_FEATURE_M68060, 484 M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */ 485 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ 486 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 487 M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ 488 M68K_FEATURE_CF_FPU, 489 M68K_FEATURE_CF_MAC, 490 M68K_FEATURE_CF_EMAC, 491 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ 492 M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/ 493 M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */ 494 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ 495 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ 496 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ 497 M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */ 498 M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */ 499 M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32) */ 500 M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */ 501 M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */ 502 M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */ 503 M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */ 504 M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */ 505 M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */ 506 M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */ 507 M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */ 508 }; 509 510 static inline int m68k_feature(CPUM68KState *env, int feature) 511 { 512 return (env->features & (1u << feature)) != 0; 513 } 514 515 void m68k_cpu_list(void); 516 517 void register_m68k_insns (CPUM68KState *env); 518 519 enum { 520 /* 1 bit to define user level / supervisor access */ 521 ACCESS_SUPER = 0x01, 522 /* 1 bit to indicate direction */ 523 ACCESS_STORE = 0x02, 524 /* 1 bit to indicate debug access */ 525 ACCESS_DEBUG = 0x04, 526 /* PTEST instruction */ 527 ACCESS_PTEST = 0x08, 528 /* Type of instruction that generated the access */ 529 ACCESS_CODE = 0x10, /* Code fetch access */ 530 ACCESS_DATA = 0x20, /* Data load/store access */ 531 }; 532 533 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 534 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 535 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 536 537 #define cpu_signal_handler cpu_m68k_signal_handler 538 #define cpu_list m68k_cpu_list 539 540 /* MMU modes definitions */ 541 #define MMU_KERNEL_IDX 0 542 #define MMU_USER_IDX 1 543 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 544 { 545 return (env->sr & SR_S) == 0 ? 1 : 0; 546 } 547 548 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 549 MMUAccessType access_type, int mmu_idx, 550 bool probe, uintptr_t retaddr); 551 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 552 unsigned size, MMUAccessType access_type, 553 int mmu_idx, MemTxAttrs attrs, 554 MemTxResult response, uintptr_t retaddr); 555 556 typedef CPUM68KState CPUArchState; 557 typedef M68kCPU ArchCPU; 558 559 #include "exec/cpu-all.h" 560 561 /* TB flags */ 562 #define TB_FLAGS_MACSR 0x0f 563 #define TB_FLAGS_MSR_S_BIT 13 564 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 565 #define TB_FLAGS_SFC_S_BIT 14 566 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 567 #define TB_FLAGS_DFC_S_BIT 15 568 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 569 570 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 571 target_ulong *cs_base, uint32_t *flags) 572 { 573 *pc = env->pc; 574 *cs_base = 0; 575 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 576 if (env->sr & SR_S) { 577 *flags |= TB_FLAGS_MSR_S; 578 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 579 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 580 } 581 } 582 583 void dump_mmu(CPUM68KState *env); 584 585 #endif 586