1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch Machine State 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "cpu.h" 10 #include "migration/cpu.h" 11 #include "internals.h" 12 13 static const VMStateDescription vmstate_fpu_reg = { 14 .name = "fpu_reg", 15 .version_id = 1, 16 .minimum_version_id = 1, 17 .fields = (VMStateField[]) { 18 VMSTATE_UINT64(UD(0), VReg), 19 VMSTATE_END_OF_LIST() 20 } 21 }; 22 23 #define VMSTATE_FPU_REGS(_field, _state, _start) \ 24 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, 32, 0, \ 25 vmstate_fpu_reg, fpr_t) 26 27 static bool fpu_needed(void *opaque) 28 { 29 LoongArchCPU *cpu = opaque; 30 31 return FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, FP); 32 } 33 34 static const VMStateDescription vmstate_fpu = { 35 .name = "cpu/fpu", 36 .version_id = 1, 37 .minimum_version_id = 1, 38 .needed = fpu_needed, 39 .fields = (VMStateField[]) { 40 VMSTATE_FPU_REGS(env.fpr, LoongArchCPU, 0), 41 VMSTATE_UINT32(env.fcsr0, LoongArchCPU), 42 VMSTATE_BOOL_ARRAY(env.cf, LoongArchCPU, 8), 43 VMSTATE_END_OF_LIST() 44 }, 45 }; 46 47 static const VMStateDescription vmstate_lsxh_reg = { 48 .name = "lsxh_reg", 49 .version_id = 1, 50 .minimum_version_id = 1, 51 .fields = (VMStateField[]) { 52 VMSTATE_UINT64(UD(1), VReg), 53 VMSTATE_END_OF_LIST() 54 } 55 }; 56 57 #define VMSTATE_LSXH_REGS(_field, _state, _start) \ 58 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, 32, 0, \ 59 vmstate_lsxh_reg, fpr_t) 60 61 static bool lsx_needed(void *opaque) 62 { 63 LoongArchCPU *cpu = opaque; 64 65 return FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, LSX); 66 } 67 68 static const VMStateDescription vmstate_lsx = { 69 .name = "cpu/lsx", 70 .version_id = 1, 71 .minimum_version_id = 1, 72 .needed = lsx_needed, 73 .fields = (VMStateField[]) { 74 VMSTATE_LSXH_REGS(env.fpr, LoongArchCPU, 0), 75 VMSTATE_END_OF_LIST() 76 }, 77 }; 78 79 /* TLB state */ 80 const VMStateDescription vmstate_tlb = { 81 .name = "cpu/tlb", 82 .version_id = 0, 83 .minimum_version_id = 0, 84 .fields = (VMStateField[]) { 85 VMSTATE_UINT64(tlb_misc, LoongArchTLB), 86 VMSTATE_UINT64(tlb_entry0, LoongArchTLB), 87 VMSTATE_UINT64(tlb_entry1, LoongArchTLB), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 /* LoongArch CPU state */ 93 const VMStateDescription vmstate_loongarch_cpu = { 94 .name = "cpu", 95 .version_id = 1, 96 .minimum_version_id = 1, 97 .fields = (VMStateField[]) { 98 VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32), 99 VMSTATE_UINTTL(env.pc, LoongArchCPU), 100 101 /* Remaining CSRs */ 102 VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU), 103 VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU), 104 VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU), 105 VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU), 106 VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU), 107 VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU), 108 VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU), 109 VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU), 110 VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU), 111 VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU), 112 VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU), 113 VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU), 114 VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU), 115 VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU), 116 VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU), 117 VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU), 118 VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU), 119 VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU), 120 VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU), 121 VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU), 122 VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU), 123 VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU), 124 VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU), 125 VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU), 126 VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU), 127 VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16), 128 VMSTATE_UINT64(env.CSR_TID, LoongArchCPU), 129 VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU), 130 VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU), 131 VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU), 132 VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU), 133 VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU), 134 VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU), 135 VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU), 136 VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU), 137 VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU), 138 VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU), 139 VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU), 140 VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU), 141 VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU), 142 VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU), 143 VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU), 144 VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU), 145 VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU), 146 VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU), 147 VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU), 148 VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU), 149 VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU), 150 VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU), 151 VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4), 152 153 /* Debug CSRs */ 154 VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU), 155 VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU), 156 VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU), 157 /* TLB */ 158 VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX, 159 0, vmstate_tlb, LoongArchTLB), 160 161 VMSTATE_END_OF_LIST() 162 }, 163 .subsections = (const VMStateDescription*[]) { 164 &vmstate_fpu, 165 &vmstate_lsx, 166 NULL 167 } 168 }; 169