1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch KVM 4 * 5 * Copyright (c) 2023 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include <sys/ioctl.h> 10 #include <linux/kvm.h> 11 12 #include "qemu/timer.h" 13 #include "qemu/error-report.h" 14 #include "qemu/main-loop.h" 15 #include "sysemu/sysemu.h" 16 #include "sysemu/kvm.h" 17 #include "sysemu/kvm_int.h" 18 #include "hw/pci/pci.h" 19 #include "exec/memattrs.h" 20 #include "exec/address-spaces.h" 21 #include "hw/boards.h" 22 #include "hw/irq.h" 23 #include "qemu/log.h" 24 #include "hw/loader.h" 25 #include "migration/migration.h" 26 #include "sysemu/runstate.h" 27 #include "cpu-csr.h" 28 #include "kvm_loongarch.h" 29 #include "trace.h" 30 31 static bool cap_has_mp_state; 32 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 33 KVM_CAP_LAST_INFO 34 }; 35 36 static int kvm_loongarch_get_regs_core(CPUState *cs) 37 { 38 int ret = 0; 39 int i; 40 struct kvm_regs regs; 41 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 42 CPULoongArchState *env = &cpu->env; 43 44 /* Get the current register set as KVM seems it */ 45 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 46 if (ret < 0) { 47 trace_kvm_failed_get_regs_core(strerror(errno)); 48 return ret; 49 } 50 /* gpr[0] value is always 0 */ 51 env->gpr[0] = 0; 52 for (i = 1; i < 32; i++) { 53 env->gpr[i] = regs.gpr[i]; 54 } 55 56 env->pc = regs.pc; 57 return ret; 58 } 59 60 static int kvm_loongarch_put_regs_core(CPUState *cs) 61 { 62 int ret = 0; 63 int i; 64 struct kvm_regs regs; 65 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 66 CPULoongArchState *env = &cpu->env; 67 68 /* Set the registers based on QEMU's view of things */ 69 for (i = 0; i < 32; i++) { 70 regs.gpr[i] = env->gpr[i]; 71 } 72 73 regs.pc = env->pc; 74 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 75 if (ret < 0) { 76 trace_kvm_failed_put_regs_core(strerror(errno)); 77 } 78 79 return ret; 80 } 81 82 static int kvm_loongarch_get_csr(CPUState *cs) 83 { 84 int ret = 0; 85 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 86 CPULoongArchState *env = &cpu->env; 87 88 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD), 89 &env->CSR_CRMD); 90 91 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRMD), 92 &env->CSR_PRMD); 93 94 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EUEN), 95 &env->CSR_EUEN); 96 97 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_MISC), 98 &env->CSR_MISC); 99 100 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ECFG), 101 &env->CSR_ECFG); 102 103 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ESTAT), 104 &env->CSR_ESTAT); 105 106 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ERA), 107 &env->CSR_ERA); 108 109 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADV), 110 &env->CSR_BADV); 111 112 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADI), 113 &env->CSR_BADI); 114 115 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EENTRY), 116 &env->CSR_EENTRY); 117 118 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBIDX), 119 &env->CSR_TLBIDX); 120 121 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBEHI), 122 &env->CSR_TLBEHI); 123 124 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO0), 125 &env->CSR_TLBELO0); 126 127 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO1), 128 &env->CSR_TLBELO1); 129 130 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ASID), 131 &env->CSR_ASID); 132 133 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDL), 134 &env->CSR_PGDL); 135 136 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDH), 137 &env->CSR_PGDH); 138 139 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGD), 140 &env->CSR_PGD); 141 142 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCL), 143 &env->CSR_PWCL); 144 145 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCH), 146 &env->CSR_PWCH); 147 148 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_STLBPS), 149 &env->CSR_STLBPS); 150 151 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_RVACFG), 152 &env->CSR_RVACFG); 153 154 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID), 155 &env->CSR_CPUID); 156 157 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG1), 158 &env->CSR_PRCFG1); 159 160 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG2), 161 &env->CSR_PRCFG2); 162 163 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG3), 164 &env->CSR_PRCFG3); 165 166 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(0)), 167 &env->CSR_SAVE[0]); 168 169 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(1)), 170 &env->CSR_SAVE[1]); 171 172 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(2)), 173 &env->CSR_SAVE[2]); 174 175 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(3)), 176 &env->CSR_SAVE[3]); 177 178 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(4)), 179 &env->CSR_SAVE[4]); 180 181 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(5)), 182 &env->CSR_SAVE[5]); 183 184 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(6)), 185 &env->CSR_SAVE[6]); 186 187 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(7)), 188 &env->CSR_SAVE[7]); 189 190 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TID), 191 &env->CSR_TID); 192 193 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CNTC), 194 &env->CSR_CNTC); 195 196 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TICLR), 197 &env->CSR_TICLR); 198 199 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_LLBCTL), 200 &env->CSR_LLBCTL); 201 202 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL1), 203 &env->CSR_IMPCTL1); 204 205 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL2), 206 &env->CSR_IMPCTL2); 207 208 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRENTRY), 209 &env->CSR_TLBRENTRY); 210 211 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRBADV), 212 &env->CSR_TLBRBADV); 213 214 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRERA), 215 &env->CSR_TLBRERA); 216 217 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRSAVE), 218 &env->CSR_TLBRSAVE); 219 220 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO0), 221 &env->CSR_TLBRELO0); 222 223 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO1), 224 &env->CSR_TLBRELO1); 225 226 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBREHI), 227 &env->CSR_TLBREHI); 228 229 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRPRMD), 230 &env->CSR_TLBRPRMD); 231 232 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(0)), 233 &env->CSR_DMW[0]); 234 235 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(1)), 236 &env->CSR_DMW[1]); 237 238 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(2)), 239 &env->CSR_DMW[2]); 240 241 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(3)), 242 &env->CSR_DMW[3]); 243 244 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TVAL), 245 &env->CSR_TVAL); 246 247 ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TCFG), 248 &env->CSR_TCFG); 249 250 return ret; 251 } 252 253 static int kvm_loongarch_put_csr(CPUState *cs, int level) 254 { 255 int ret = 0; 256 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 257 CPULoongArchState *env = &cpu->env; 258 259 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD), 260 &env->CSR_CRMD); 261 262 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRMD), 263 &env->CSR_PRMD); 264 265 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EUEN), 266 &env->CSR_EUEN); 267 268 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_MISC), 269 &env->CSR_MISC); 270 271 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ECFG), 272 &env->CSR_ECFG); 273 274 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ESTAT), 275 &env->CSR_ESTAT); 276 277 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ERA), 278 &env->CSR_ERA); 279 280 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADV), 281 &env->CSR_BADV); 282 283 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADI), 284 &env->CSR_BADI); 285 286 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EENTRY), 287 &env->CSR_EENTRY); 288 289 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBIDX), 290 &env->CSR_TLBIDX); 291 292 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBEHI), 293 &env->CSR_TLBEHI); 294 295 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO0), 296 &env->CSR_TLBELO0); 297 298 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO1), 299 &env->CSR_TLBELO1); 300 301 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ASID), 302 &env->CSR_ASID); 303 304 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDL), 305 &env->CSR_PGDL); 306 307 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDH), 308 &env->CSR_PGDH); 309 310 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGD), 311 &env->CSR_PGD); 312 313 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCL), 314 &env->CSR_PWCL); 315 316 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCH), 317 &env->CSR_PWCH); 318 319 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_STLBPS), 320 &env->CSR_STLBPS); 321 322 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_RVACFG), 323 &env->CSR_RVACFG); 324 325 /* CPUID is constant after poweron, it should be set only once */ 326 if (level >= KVM_PUT_FULL_STATE) { 327 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID), 328 &env->CSR_CPUID); 329 } 330 331 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG1), 332 &env->CSR_PRCFG1); 333 334 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG2), 335 &env->CSR_PRCFG2); 336 337 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG3), 338 &env->CSR_PRCFG3); 339 340 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(0)), 341 &env->CSR_SAVE[0]); 342 343 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(1)), 344 &env->CSR_SAVE[1]); 345 346 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(2)), 347 &env->CSR_SAVE[2]); 348 349 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(3)), 350 &env->CSR_SAVE[3]); 351 352 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(4)), 353 &env->CSR_SAVE[4]); 354 355 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(5)), 356 &env->CSR_SAVE[5]); 357 358 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(6)), 359 &env->CSR_SAVE[6]); 360 361 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(7)), 362 &env->CSR_SAVE[7]); 363 364 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TID), 365 &env->CSR_TID); 366 367 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CNTC), 368 &env->CSR_CNTC); 369 370 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TICLR), 371 &env->CSR_TICLR); 372 373 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_LLBCTL), 374 &env->CSR_LLBCTL); 375 376 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL1), 377 &env->CSR_IMPCTL1); 378 379 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL2), 380 &env->CSR_IMPCTL2); 381 382 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRENTRY), 383 &env->CSR_TLBRENTRY); 384 385 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRBADV), 386 &env->CSR_TLBRBADV); 387 388 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRERA), 389 &env->CSR_TLBRERA); 390 391 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRSAVE), 392 &env->CSR_TLBRSAVE); 393 394 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO0), 395 &env->CSR_TLBRELO0); 396 397 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO1), 398 &env->CSR_TLBRELO1); 399 400 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBREHI), 401 &env->CSR_TLBREHI); 402 403 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRPRMD), 404 &env->CSR_TLBRPRMD); 405 406 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(0)), 407 &env->CSR_DMW[0]); 408 409 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(1)), 410 &env->CSR_DMW[1]); 411 412 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(2)), 413 &env->CSR_DMW[2]); 414 415 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(3)), 416 &env->CSR_DMW[3]); 417 /* 418 * timer cfg must be put at last since it is used to enable 419 * guest timer 420 */ 421 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TVAL), 422 &env->CSR_TVAL); 423 424 ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TCFG), 425 &env->CSR_TCFG); 426 return ret; 427 } 428 429 static int kvm_loongarch_get_regs_fp(CPUState *cs) 430 { 431 int ret, i; 432 struct kvm_fpu fpu; 433 434 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 435 CPULoongArchState *env = &cpu->env; 436 437 ret = kvm_vcpu_ioctl(cs, KVM_GET_FPU, &fpu); 438 if (ret < 0) { 439 trace_kvm_failed_get_fpu(strerror(errno)); 440 return ret; 441 } 442 443 env->fcsr0 = fpu.fcsr; 444 for (i = 0; i < 32; i++) { 445 env->fpr[i].vreg.UD[0] = fpu.fpr[i].val64[0]; 446 } 447 for (i = 0; i < 8; i++) { 448 env->cf[i] = fpu.fcc & 0xFF; 449 fpu.fcc = fpu.fcc >> 8; 450 } 451 452 return ret; 453 } 454 455 static int kvm_loongarch_put_regs_fp(CPUState *cs) 456 { 457 int ret, i; 458 struct kvm_fpu fpu; 459 460 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 461 CPULoongArchState *env = &cpu->env; 462 463 fpu.fcsr = env->fcsr0; 464 fpu.fcc = 0; 465 for (i = 0; i < 32; i++) { 466 fpu.fpr[i].val64[0] = env->fpr[i].vreg.UD[0]; 467 } 468 469 for (i = 0; i < 8; i++) { 470 fpu.fcc |= env->cf[i] << (8 * i); 471 } 472 473 ret = kvm_vcpu_ioctl(cs, KVM_SET_FPU, &fpu); 474 if (ret < 0) { 475 trace_kvm_failed_put_fpu(strerror(errno)); 476 } 477 478 return ret; 479 } 480 481 void kvm_arch_reset_vcpu(CPULoongArchState *env) 482 { 483 env->mp_state = KVM_MP_STATE_RUNNABLE; 484 } 485 486 static int kvm_loongarch_get_mpstate(CPUState *cs) 487 { 488 int ret = 0; 489 struct kvm_mp_state mp_state; 490 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 491 CPULoongArchState *env = &cpu->env; 492 493 if (cap_has_mp_state) { 494 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); 495 if (ret) { 496 trace_kvm_failed_get_mpstate(strerror(errno)); 497 return ret; 498 } 499 env->mp_state = mp_state.mp_state; 500 } 501 502 return ret; 503 } 504 505 static int kvm_loongarch_put_mpstate(CPUState *cs) 506 { 507 int ret = 0; 508 509 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 510 CPULoongArchState *env = &cpu->env; 511 512 struct kvm_mp_state mp_state = { 513 .mp_state = env->mp_state 514 }; 515 516 if (cap_has_mp_state) { 517 ret = kvm_vcpu_ioctl(cs, KVM_SET_MP_STATE, &mp_state); 518 if (ret) { 519 trace_kvm_failed_put_mpstate(strerror(errno)); 520 } 521 } 522 523 return ret; 524 } 525 526 static int kvm_loongarch_get_cpucfg(CPUState *cs) 527 { 528 int i, ret = 0; 529 uint64_t val; 530 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 531 CPULoongArchState *env = &cpu->env; 532 533 for (i = 0; i < 21; i++) { 534 ret = kvm_get_one_reg(cs, KVM_IOC_CPUCFG(i), &val); 535 if (ret < 0) { 536 trace_kvm_failed_get_cpucfg(strerror(errno)); 537 } 538 env->cpucfg[i] = (uint32_t)val; 539 } 540 return ret; 541 } 542 543 static int kvm_check_cpucfg2(CPUState *cs) 544 { 545 int ret; 546 uint64_t val; 547 struct kvm_device_attr attr = { 548 .group = KVM_LOONGARCH_VCPU_CPUCFG, 549 .attr = 2, 550 .addr = (uint64_t)&val, 551 }; 552 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 553 CPULoongArchState *env = &cpu->env; 554 555 ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr); 556 557 if (!ret) { 558 kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr); 559 env->cpucfg[2] &= val; 560 561 if (FIELD_EX32(env->cpucfg[2], CPUCFG2, FP)) { 562 /* The FP minimal version is 1. */ 563 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, FP_VER, 1); 564 } 565 566 if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LLFTP)) { 567 /* The LLFTP minimal version is 1. */ 568 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LLFTP_VER, 1); 569 } 570 } 571 572 return ret; 573 } 574 575 static int kvm_loongarch_put_cpucfg(CPUState *cs) 576 { 577 int i, ret = 0; 578 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 579 CPULoongArchState *env = &cpu->env; 580 uint64_t val; 581 582 for (i = 0; i < 21; i++) { 583 if (i == 2) { 584 ret = kvm_check_cpucfg2(cs); 585 if (ret) { 586 return ret; 587 } 588 } 589 val = env->cpucfg[i]; 590 ret = kvm_set_one_reg(cs, KVM_IOC_CPUCFG(i), &val); 591 if (ret < 0) { 592 trace_kvm_failed_put_cpucfg(strerror(errno)); 593 } 594 } 595 return ret; 596 } 597 598 int kvm_arch_get_registers(CPUState *cs) 599 { 600 int ret; 601 602 ret = kvm_loongarch_get_regs_core(cs); 603 if (ret) { 604 return ret; 605 } 606 607 ret = kvm_loongarch_get_csr(cs); 608 if (ret) { 609 return ret; 610 } 611 612 ret = kvm_loongarch_get_regs_fp(cs); 613 if (ret) { 614 return ret; 615 } 616 617 ret = kvm_loongarch_get_mpstate(cs); 618 if (ret) { 619 return ret; 620 } 621 622 ret = kvm_loongarch_get_cpucfg(cs); 623 return ret; 624 } 625 626 int kvm_arch_put_registers(CPUState *cs, int level) 627 { 628 int ret; 629 630 ret = kvm_loongarch_put_regs_core(cs); 631 if (ret) { 632 return ret; 633 } 634 635 ret = kvm_loongarch_put_csr(cs, level); 636 if (ret) { 637 return ret; 638 } 639 640 ret = kvm_loongarch_put_regs_fp(cs); 641 if (ret) { 642 return ret; 643 } 644 645 ret = kvm_loongarch_put_mpstate(cs); 646 if (ret) { 647 return ret; 648 } 649 650 ret = kvm_loongarch_put_cpucfg(cs); 651 return ret; 652 } 653 654 static void kvm_loongarch_vm_stage_change(void *opaque, bool running, 655 RunState state) 656 { 657 int ret; 658 CPUState *cs = opaque; 659 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 660 661 if (running) { 662 ret = kvm_set_one_reg(cs, KVM_REG_LOONGARCH_COUNTER, 663 &cpu->kvm_state_counter); 664 if (ret < 0) { 665 trace_kvm_failed_put_counter(strerror(errno)); 666 } 667 } else { 668 ret = kvm_get_one_reg(cs, KVM_REG_LOONGARCH_COUNTER, 669 &cpu->kvm_state_counter); 670 if (ret < 0) { 671 trace_kvm_failed_get_counter(strerror(errno)); 672 } 673 } 674 } 675 676 int kvm_arch_init_vcpu(CPUState *cs) 677 { 678 qemu_add_vm_change_state_handler(kvm_loongarch_vm_stage_change, cs); 679 return 0; 680 } 681 682 int kvm_arch_destroy_vcpu(CPUState *cs) 683 { 684 return 0; 685 } 686 687 unsigned long kvm_arch_vcpu_id(CPUState *cs) 688 { 689 return cs->cpu_index; 690 } 691 692 int kvm_arch_release_virq_post(int virq) 693 { 694 return 0; 695 } 696 697 int kvm_arch_msi_data_to_gsi(uint32_t data) 698 { 699 abort(); 700 } 701 702 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 703 uint64_t address, uint32_t data, PCIDevice *dev) 704 { 705 return 0; 706 } 707 708 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 709 int vector, PCIDevice *dev) 710 { 711 return 0; 712 } 713 714 void kvm_arch_init_irq_routing(KVMState *s) 715 { 716 } 717 718 int kvm_arch_get_default_type(MachineState *ms) 719 { 720 return 0; 721 } 722 723 int kvm_arch_init(MachineState *ms, KVMState *s) 724 { 725 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 726 return 0; 727 } 728 729 int kvm_arch_irqchip_create(KVMState *s) 730 { 731 return 0; 732 } 733 734 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 735 { 736 } 737 738 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 739 { 740 return MEMTXATTRS_UNSPECIFIED; 741 } 742 743 int kvm_arch_process_async_events(CPUState *cs) 744 { 745 return cs->halted; 746 } 747 748 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 749 { 750 return true; 751 } 752 753 bool kvm_arch_cpu_check_are_resettable(void) 754 { 755 return true; 756 } 757 758 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 759 { 760 int ret = 0; 761 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 762 CPULoongArchState *env = &cpu->env; 763 MemTxAttrs attrs = {}; 764 765 attrs.requester_id = env_cpu(env)->cpu_index; 766 767 trace_kvm_arch_handle_exit(run->exit_reason); 768 switch (run->exit_reason) { 769 case KVM_EXIT_LOONGARCH_IOCSR: 770 address_space_rw(env->address_space_iocsr, 771 run->iocsr_io.phys_addr, 772 attrs, 773 run->iocsr_io.data, 774 run->iocsr_io.len, 775 run->iocsr_io.is_write); 776 break; 777 default: 778 ret = -1; 779 warn_report("KVM: unknown exit reason %d", run->exit_reason); 780 break; 781 } 782 return ret; 783 } 784 785 int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level) 786 { 787 struct kvm_interrupt intr; 788 CPUState *cs = CPU(cpu); 789 790 if (level) { 791 intr.irq = irq; 792 } else { 793 intr.irq = -irq; 794 } 795 796 trace_kvm_set_intr(irq, level); 797 return kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 798 } 799 800 void kvm_arch_accel_class_init(ObjectClass *oc) 801 { 802 } 803