1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 2021 Loongson Technology Corporation Limited 4 */ 5 6static const uint32_t fcsr_mask[4] = { 7 UINT32_MAX, FCSR0_M1, FCSR0_M2, FCSR0_M3 8}; 9 10static bool trans_fsel(DisasContext *ctx, arg_fsel *a) 11{ 12 TCGv zero = tcg_constant_tl(0); 13 TCGv dest = get_fpr(ctx, a->fd); 14 TCGv src1 = get_fpr(ctx, a->fj); 15 TCGv src2 = get_fpr(ctx, a->fk); 16 TCGv cond; 17 18 CHECK_FPE; 19 20 cond = tcg_temp_new(); 21 tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca])); 22 tcg_gen_movcond_tl(TCG_COND_EQ, dest, cond, zero, src1, src2); 23 set_fpr(a->fd, dest); 24 25 return true; 26} 27 28static bool gen_f2f(DisasContext *ctx, arg_ff *a, 29 void (*func)(TCGv, TCGv), bool nanbox) 30{ 31 TCGv dest = get_fpr(ctx, a->fd); 32 TCGv src = get_fpr(ctx, a->fj); 33 34 CHECK_FPE; 35 36 func(dest, src); 37 if (nanbox) { 38 gen_nanbox_s(dest, dest); 39 } 40 set_fpr(a->fd, dest); 41 42 return true; 43} 44 45static bool gen_r2f(DisasContext *ctx, arg_fr *a, 46 void (*func)(TCGv, TCGv)) 47{ 48 TCGv src = gpr_src(ctx, a->rj, EXT_NONE); 49 TCGv dest = get_fpr(ctx, a->fd); 50 51 CHECK_FPE; 52 53 func(dest, src); 54 set_fpr(a->fd, dest); 55 56 return true; 57} 58 59static bool gen_f2r(DisasContext *ctx, arg_rf *a, 60 void (*func)(TCGv, TCGv)) 61{ 62 TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); 63 TCGv src = get_fpr(ctx, a->fj); 64 65 CHECK_FPE; 66 67 func(dest, src); 68 gen_set_gpr(a->rd, dest, EXT_NONE); 69 70 return true; 71} 72 73static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a) 74{ 75 uint32_t mask = fcsr_mask[a->fcsrd]; 76 TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE); 77 78 CHECK_FPE; 79 80 if (mask == UINT32_MAX) { 81 tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0)); 82 } else { 83 TCGv_i32 fcsr0 = tcg_temp_new_i32(); 84 TCGv_i32 temp = tcg_temp_new_i32(); 85 86 tcg_gen_ld_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); 87 tcg_gen_extrl_i64_i32(temp, Rj); 88 tcg_gen_andi_i32(temp, temp, mask); 89 tcg_gen_andi_i32(fcsr0, fcsr0, ~mask); 90 tcg_gen_or_i32(fcsr0, fcsr0, temp); 91 tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); 92 } 93 94 /* 95 * Install the new rounding mode to fpu_status, if changed. 96 * Note that FCSR3 is exactly the rounding mode field. 97 */ 98 if (mask & FCSR0_M3) { 99 gen_helper_set_rounding_mode(cpu_env); 100 } 101 return true; 102} 103 104static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a) 105{ 106 TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); 107 108 CHECK_FPE; 109 110 tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0)); 111 tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]); 112 gen_set_gpr(a->rd, dest, EXT_NONE); 113 114 return true; 115} 116 117static void gen_movgr2fr_w(TCGv dest, TCGv src) 118{ 119 tcg_gen_deposit_i64(dest, dest, src, 0, 32); 120} 121 122static void gen_movgr2frh_w(TCGv dest, TCGv src) 123{ 124 tcg_gen_deposit_i64(dest, dest, src, 32, 32); 125} 126 127static void gen_movfrh2gr_s(TCGv dest, TCGv src) 128{ 129 tcg_gen_sextract_tl(dest, src, 32, 32); 130} 131 132static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a) 133{ 134 TCGv t0; 135 TCGv src = get_fpr(ctx, a->fj); 136 137 CHECK_FPE; 138 139 t0 = tcg_temp_new(); 140 tcg_gen_andi_tl(t0, src, 0x1); 141 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); 142 143 return true; 144} 145 146static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a) 147{ 148 TCGv dest = get_fpr(ctx, a->fd); 149 150 CHECK_FPE; 151 152 tcg_gen_ld8u_tl(dest, cpu_env, 153 offsetof(CPULoongArchState, cf[a->cj & 0x7])); 154 set_fpr(a->fd, dest); 155 156 return true; 157} 158 159static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a) 160{ 161 TCGv t0; 162 163 CHECK_FPE; 164 165 t0 = tcg_temp_new(); 166 tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1); 167 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); 168 169 return true; 170} 171 172static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a) 173{ 174 CHECK_FPE; 175 176 tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env, 177 offsetof(CPULoongArchState, cf[a->cj & 0x7])); 178 return true; 179} 180 181TRANS(fmov_s, gen_f2f, tcg_gen_mov_tl, true) 182TRANS(fmov_d, gen_f2f, tcg_gen_mov_tl, false) 183TRANS(movgr2fr_w, gen_r2f, gen_movgr2fr_w) 184TRANS(movgr2fr_d, gen_r2f, tcg_gen_mov_tl) 185TRANS(movgr2frh_w, gen_r2f, gen_movgr2frh_w) 186TRANS(movfr2gr_s, gen_f2r, tcg_gen_ext32s_tl) 187TRANS(movfr2gr_d, gen_f2r, tcg_gen_mov_tl) 188TRANS(movfrh2gr_s, gen_f2r, gen_movfrh2gr_s) 189