1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 2021 Loongson Technology Corporation Limited 4 */ 5 6static const uint32_t fcsr_mask[4] = { 7 UINT32_MAX, FCSR0_M1, FCSR0_M2, FCSR0_M3 8}; 9 10static bool trans_fsel(DisasContext *ctx, arg_fsel *a) 11{ 12 TCGv zero = tcg_constant_tl(0); 13 TCGv cond; 14 15 CHECK_FPE; 16 17 cond = tcg_temp_new(); 18 tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca])); 19 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero, 20 cpu_fpr[a->fj], cpu_fpr[a->fk]); 21 tcg_temp_free(cond); 22 23 return true; 24} 25 26static bool gen_f2f(DisasContext *ctx, arg_ff *a, 27 void (*func)(TCGv, TCGv), bool nanbox) 28{ 29 TCGv dest = cpu_fpr[a->fd]; 30 TCGv src = cpu_fpr[a->fj]; 31 32 CHECK_FPE; 33 34 func(dest, src); 35 if (nanbox) { 36 gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]); 37 } 38 39 return true; 40} 41 42static bool gen_r2f(DisasContext *ctx, arg_fr *a, 43 void (*func)(TCGv, TCGv)) 44{ 45 TCGv src = gpr_src(ctx, a->rj, EXT_NONE); 46 47 CHECK_FPE; 48 49 func(cpu_fpr[a->fd], src); 50 return true; 51} 52 53static bool gen_f2r(DisasContext *ctx, arg_rf *a, 54 void (*func)(TCGv, TCGv)) 55{ 56 TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); 57 58 CHECK_FPE; 59 60 func(dest, cpu_fpr[a->fj]); 61 gen_set_gpr(a->rd, dest, EXT_NONE); 62 63 return true; 64} 65 66static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a) 67{ 68 uint32_t mask = fcsr_mask[a->fcsrd]; 69 TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE); 70 71 CHECK_FPE; 72 73 if (mask == UINT32_MAX) { 74 tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0)); 75 } else { 76 TCGv_i32 fcsr0 = tcg_temp_new_i32(); 77 TCGv_i32 temp = tcg_temp_new_i32(); 78 79 tcg_gen_ld_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); 80 tcg_gen_extrl_i64_i32(temp, Rj); 81 tcg_gen_andi_i32(temp, temp, mask); 82 tcg_gen_andi_i32(fcsr0, fcsr0, ~mask); 83 tcg_gen_or_i32(fcsr0, fcsr0, temp); 84 tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); 85 86 tcg_temp_free_i32(temp); 87 tcg_temp_free_i32(fcsr0); 88 } 89 90 /* 91 * Install the new rounding mode to fpu_status, if changed. 92 * Note that FCSR3 is exactly the rounding mode field. 93 */ 94 if (mask & FCSR0_M3) { 95 gen_helper_set_rounding_mode(cpu_env); 96 } 97 return true; 98} 99 100static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a) 101{ 102 TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); 103 104 CHECK_FPE; 105 106 tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0)); 107 tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]); 108 gen_set_gpr(a->rd, dest, EXT_NONE); 109 110 return true; 111} 112 113static void gen_movgr2fr_w(TCGv dest, TCGv src) 114{ 115 tcg_gen_deposit_i64(dest, dest, src, 0, 32); 116} 117 118static void gen_movgr2frh_w(TCGv dest, TCGv src) 119{ 120 tcg_gen_deposit_i64(dest, dest, src, 32, 32); 121} 122 123static void gen_movfrh2gr_s(TCGv dest, TCGv src) 124{ 125 tcg_gen_sextract_tl(dest, src, 32, 32); 126} 127 128static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a) 129{ 130 TCGv t0; 131 132 CHECK_FPE; 133 134 t0 = tcg_temp_new(); 135 tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1); 136 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); 137 tcg_temp_free(t0); 138 139 return true; 140} 141 142static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a) 143{ 144 CHECK_FPE; 145 146 tcg_gen_ld8u_tl(cpu_fpr[a->fd], cpu_env, 147 offsetof(CPULoongArchState, cf[a->cj & 0x7])); 148 return true; 149} 150 151static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a) 152{ 153 TCGv t0; 154 155 CHECK_FPE; 156 157 t0 = tcg_temp_new(); 158 tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1); 159 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); 160 tcg_temp_free(t0); 161 162 return true; 163} 164 165static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a) 166{ 167 CHECK_FPE; 168 169 tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env, 170 offsetof(CPULoongArchState, cf[a->cj & 0x7])); 171 return true; 172} 173 174TRANS(fmov_s, gen_f2f, tcg_gen_mov_tl, true) 175TRANS(fmov_d, gen_f2f, tcg_gen_mov_tl, false) 176TRANS(movgr2fr_w, gen_r2f, gen_movgr2fr_w) 177TRANS(movgr2fr_d, gen_r2f, tcg_gen_mov_tl) 178TRANS(movgr2frh_w, gen_r2f, gen_movgr2frh_w) 179TRANS(movfr2gr_s, gen_f2r, tcg_gen_ext32s_tl) 180TRANS(movfr2gr_d, gen_f2r, tcg_gen_mov_tl) 181TRANS(movfrh2gr_s, gen_f2r, gen_movfrh2gr_s) 182