1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (c) 2021 Loongson Technology Corporation Limited
4 */
5
6static bool gen_rrr(DisasContext *ctx, arg_rrr *a,
7                    DisasExtend src1_ext, DisasExtend src2_ext,
8                    DisasExtend dst_ext, void (*func)(TCGv, TCGv, TCGv))
9{
10    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
11    TCGv src1 = gpr_src(ctx, a->rj, src1_ext);
12    TCGv src2 = gpr_src(ctx, a->rk, src2_ext);
13
14    func(dest, src1, src2);
15    gen_set_gpr(a->rd, dest, dst_ext);
16
17    return true;
18}
19
20static bool gen_rri_v(DisasContext *ctx, arg_rr_i *a,
21                      DisasExtend src_ext, DisasExtend dst_ext,
22                      void (*func)(TCGv, TCGv, TCGv))
23{
24    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
25    TCGv src1 = gpr_src(ctx, a->rj, src_ext);
26    TCGv src2 = tcg_constant_tl(a->imm);
27
28    func(dest, src1, src2);
29    gen_set_gpr(a->rd, dest, dst_ext);
30
31    return true;
32}
33
34static bool gen_rri_c(DisasContext *ctx, arg_rr_i *a,
35                      DisasExtend src_ext, DisasExtend dst_ext,
36                      void (*func)(TCGv, TCGv, target_long))
37{
38    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
39    TCGv src1 = gpr_src(ctx, a->rj, src_ext);
40
41    func(dest, src1, a->imm);
42    gen_set_gpr(a->rd, dest, dst_ext);
43
44    return true;
45}
46
47static bool gen_rrr_sa(DisasContext *ctx, arg_rrr_sa *a,
48                       DisasExtend src_ext, DisasExtend dst_ext,
49                       void (*func)(TCGv, TCGv, TCGv, target_long))
50{
51    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
52    TCGv src1 = gpr_src(ctx, a->rj, src_ext);
53    TCGv src2 = gpr_src(ctx, a->rk, src_ext);
54
55    func(dest, src1, src2, a->sa);
56    gen_set_gpr(a->rd, dest, dst_ext);
57
58    return true;
59}
60
61static bool trans_lu12i_w(DisasContext *ctx, arg_lu12i_w *a)
62{
63    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
64
65    tcg_gen_movi_tl(dest, a->imm << 12);
66    gen_set_gpr(a->rd, dest, EXT_NONE);
67
68    return true;
69}
70
71static bool gen_pc(DisasContext *ctx, arg_r_i *a,
72                   target_ulong (*func)(target_ulong, int))
73{
74    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
75    target_ulong addr = func(ctx->base.pc_next, a->imm);
76
77    tcg_gen_movi_tl(dest, addr);
78    gen_set_gpr(a->rd, dest, EXT_NONE);
79
80    return true;
81}
82
83static void gen_slt(TCGv dest, TCGv src1, TCGv src2)
84{
85    tcg_gen_setcond_tl(TCG_COND_LT, dest, src1, src2);
86}
87
88static void gen_sltu(TCGv dest, TCGv src1, TCGv src2)
89{
90    tcg_gen_setcond_tl(TCG_COND_LTU, dest, src1, src2);
91}
92
93static void gen_mulh_w(TCGv dest, TCGv src1, TCGv src2)
94{
95    tcg_gen_mul_i64(dest, src1, src2);
96    tcg_gen_sari_i64(dest, dest, 32);
97}
98
99static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src2)
100{
101    TCGv discard = tcg_temp_new();
102    tcg_gen_muls2_tl(discard, dest, src1, src2);
103    tcg_temp_free(discard);
104}
105
106static void gen_mulh_du(TCGv dest, TCGv src1, TCGv src2)
107{
108    TCGv discard = tcg_temp_new();
109    tcg_gen_mulu2_tl(discard, dest, src1, src2);
110    tcg_temp_free(discard);
111}
112
113static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
114{
115    TCGv t0 = tcg_temp_new();
116    TCGv t1 = tcg_temp_new();
117    TCGv zero = tcg_constant_tl(0);
118
119    /*
120     * If min / -1, set the divisor to 1.
121     * This avoids potential host overflow trap and produces min.
122     * If x / 0, set the divisor to 1.
123     * This avoids potential host overflow trap;
124     * the required result is undefined.
125     */
126    tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, INT64_MIN);
127    tcg_gen_setcondi_tl(TCG_COND_EQ, t0, src2, -1);
128    tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src2, 0);
129    tcg_gen_and_tl(ret, ret, t0);
130    tcg_gen_or_tl(ret, ret, t1);
131    tcg_gen_movcond_tl(TCG_COND_NE, ret, ret, zero, ret, src2);
132
133    tcg_temp_free(t0);
134    tcg_temp_free(t1);
135}
136
137static void prep_divisor_du(TCGv ret, TCGv src2)
138{
139    TCGv zero = tcg_constant_tl(0);
140    TCGv one = tcg_constant_tl(1);
141
142    /*
143     * If x / 0, set the divisor to 1.
144     * This avoids potential host overflow trap;
145     * the required result is undefined.
146     */
147    tcg_gen_movcond_tl(TCG_COND_EQ, ret, src2, zero, one, src2);
148}
149
150static void gen_div_d(TCGv dest, TCGv src1, TCGv src2)
151{
152    TCGv t0 = tcg_temp_new();
153    prep_divisor_d(t0, src1, src2);
154    tcg_gen_div_tl(dest, src1, t0);
155    tcg_temp_free(t0);
156}
157
158static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
159{
160    TCGv t0 = tcg_temp_new();
161    prep_divisor_d(t0, src1, src2);
162    tcg_gen_rem_tl(dest, src1, t0);
163    tcg_temp_free(t0);
164}
165
166static void gen_div_du(TCGv dest, TCGv src1, TCGv src2)
167{
168    TCGv t0 = tcg_temp_new();
169    prep_divisor_du(t0, src2);
170    tcg_gen_divu_tl(dest, src1, t0);
171    tcg_temp_free(t0);
172}
173
174static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
175{
176    TCGv t0 = tcg_temp_new();
177    prep_divisor_du(t0, src2);
178    tcg_gen_remu_tl(dest, src1, t0);
179    tcg_temp_free(t0);
180}
181
182static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
183{
184    TCGv t0 = tcg_temp_new();
185    /* We need not check for integer overflow for div_w. */
186    prep_divisor_du(t0, src2);
187    tcg_gen_div_tl(dest, src1, t0);
188    tcg_temp_free(t0);
189}
190
191static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)
192{
193    TCGv t0 = tcg_temp_new();
194    /* We need not check for integer overflow for rem_w. */
195    prep_divisor_du(t0, src2);
196    tcg_gen_rem_tl(dest, src1, t0);
197    tcg_temp_free(t0);
198}
199
200static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa)
201{
202    TCGv t0 = tcg_temp_new();
203    tcg_gen_shli_tl(t0, src1, sa);
204    tcg_gen_add_tl(dest, t0, src2);
205    tcg_temp_free(t0);
206}
207
208static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a)
209{
210    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
211    TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
212    TCGv src2 = tcg_constant_tl(a->imm);
213
214    tcg_gen_deposit_tl(dest, src1, src2, 32, 32);
215    gen_set_gpr(a->rd, dest, EXT_NONE);
216
217    return true;
218}
219
220static bool trans_lu52i_d(DisasContext *ctx, arg_lu52i_d *a)
221{
222    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
223    TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
224    TCGv src2 = tcg_constant_tl(a->imm);
225
226    tcg_gen_deposit_tl(dest, src1, src2, 52, 12);
227    gen_set_gpr(a->rd, dest, EXT_NONE);
228
229    return true;
230}
231
232static target_ulong gen_pcaddi(target_ulong pc, int imm)
233{
234    return pc + (imm << 2);
235}
236
237static target_ulong gen_pcalau12i(target_ulong pc, int imm)
238{
239    return (pc + (imm << 12)) & ~0xfff;
240}
241
242static target_ulong gen_pcaddu12i(target_ulong pc, int imm)
243{
244    return pc + (imm << 12);
245}
246
247static target_ulong gen_pcaddu18i(target_ulong pc, int imm)
248{
249    return pc + ((target_ulong)(imm) << 18);
250}
251
252static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a)
253{
254    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
255    TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
256
257    tcg_gen_addi_tl(dest, src1, a->imm << 16);
258    gen_set_gpr(a->rd, dest, EXT_NONE);
259
260    return true;
261}
262
263TRANS(add_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl)
264TRANS(add_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)
265TRANS(sub_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl)
266TRANS(sub_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)
267TRANS(and, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl)
268TRANS(or, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl)
269TRANS(xor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl)
270TRANS(nor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_nor_tl)
271TRANS(andn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_andc_tl)
272TRANS(orn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl)
273TRANS(slt, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt)
274TRANS(sltu, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)
275TRANS(mul_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl)
276TRANS(mul_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
277TRANS(mulh_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w)
278TRANS(mulh_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w)
279TRANS(mulh_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
280TRANS(mulh_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
281TRANS(mulw_d_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)
282TRANS(mulw_d_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)
283TRANS(div_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w)
284TRANS(mod_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w)
285TRANS(div_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du)
286TRANS(mod_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du)
287TRANS(div_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)
288TRANS(mod_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)
289TRANS(div_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)
290TRANS(mod_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)
291TRANS(slti, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt)
292TRANS(sltui, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu)
293TRANS(addi_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl)
294TRANS(addi_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
295TRANS(alsl_w, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
296TRANS(alsl_wu, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
297TRANS(alsl_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
298TRANS(pcaddi, gen_pc, gen_pcaddi)
299TRANS(pcalau12i, gen_pc, gen_pcalau12i)
300TRANS(pcaddu12i, gen_pc, gen_pcaddu12i)
301TRANS(pcaddu18i, gen_pc, gen_pcaddu18i)
302TRANS(andi, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)
303TRANS(ori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)
304TRANS(xori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl)
305