1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef LOONGARCH_CPU_H 9 #define LOONGARCH_CPU_H 10 11 #include "exec/cpu-defs.h" 12 #include "fpu/softfloat-types.h" 13 #include "hw/registerfields.h" 14 #include "qemu/timer.h" 15 #ifndef CONFIG_USER_ONLY 16 #include "exec/memory.h" 17 #endif 18 #include "cpu-csr.h" 19 20 #define IOCSRF_TEMP 0 21 #define IOCSRF_NODECNT 1 22 #define IOCSRF_MSI 2 23 #define IOCSRF_EXTIOI 3 24 #define IOCSRF_CSRIPI 4 25 #define IOCSRF_FREQCSR 5 26 #define IOCSRF_FREQSCALE 6 27 #define IOCSRF_DVFSV1 7 28 #define IOCSRF_GMOD 9 29 #define IOCSRF_VM 11 30 31 #define VERSION_REG 0x0 32 #define FEATURE_REG 0x8 33 #define VENDOR_REG 0x10 34 #define CPUNAME_REG 0x20 35 #define MISC_FUNC_REG 0x420 36 #define IOCSRM_EXTIOI_EN 48 37 38 #define IOCSR_MEM_SIZE 0x428 39 40 #define TCG_GUEST_DEFAULT_MO (0) 41 42 #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ 43 #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ 44 #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ 45 #define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */ 46 47 FIELD(FCSR0, ENABLES, 0, 5) 48 FIELD(FCSR0, RM, 8, 2) 49 FIELD(FCSR0, FLAGS, 16, 5) 50 FIELD(FCSR0, CAUSE, 24, 5) 51 52 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) 53 #define SET_FP_CAUSE(REG, V) \ 54 do { \ 55 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \ 56 } while (0) 57 58 #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) 59 #define SET_FP_ENABLES(REG, V) \ 60 do { \ 61 (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \ 62 } while (0) 63 64 #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) 65 #define SET_FP_FLAGS(REG, V) \ 66 do { \ 67 (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \ 68 } while (0) 69 70 #define UPDATE_FP_FLAGS(REG, V) \ 71 do { \ 72 (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \ 73 } while (0) 74 75 #define FP_INEXACT 1 76 #define FP_UNDERFLOW 2 77 #define FP_OVERFLOW 4 78 #define FP_DIV0 8 79 #define FP_INVALID 16 80 81 #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) ) 82 #define EXCODE_MCODE(code) ( (code) & 0x3f ) 83 #define EXCODE_SUBCODE(code) ( (code) >> 6 ) 84 85 #define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */ 86 #define EXCCODE_INT EXCODE(0, 0) 87 #define EXCCODE_PIL EXCODE(1, 0) 88 #define EXCCODE_PIS EXCODE(2, 0) 89 #define EXCCODE_PIF EXCODE(3, 0) 90 #define EXCCODE_PME EXCODE(4, 0) 91 #define EXCCODE_PNR EXCODE(5, 0) 92 #define EXCCODE_PNX EXCODE(6, 0) 93 #define EXCCODE_PPI EXCODE(7, 0) 94 #define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */ 95 #define EXCCODE_ADEM EXCODE(8, 1) 96 #define EXCCODE_ALE EXCODE(9, 0) 97 #define EXCCODE_BCE EXCODE(10, 0) 98 #define EXCCODE_SYS EXCODE(11, 0) 99 #define EXCCODE_BRK EXCODE(12, 0) 100 #define EXCCODE_INE EXCODE(13, 0) 101 #define EXCCODE_IPE EXCODE(14, 0) 102 #define EXCCODE_FPD EXCODE(15, 0) 103 #define EXCCODE_SXD EXCODE(16, 0) 104 #define EXCCODE_ASXD EXCODE(17, 0) 105 #define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */ 106 #define EXCCODE_VFPE EXCODE(18, 1) 107 #define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */ 108 #define EXCCODE_WPEM EXCODE(19, 1) 109 #define EXCCODE_BTD EXCODE(20, 0) 110 #define EXCCODE_BTE EXCODE(21, 0) 111 #define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */ 112 113 /* cpucfg[0] bits */ 114 FIELD(CPUCFG0, PRID, 0, 32) 115 116 /* cpucfg[1] bits */ 117 FIELD(CPUCFG1, ARCH, 0, 2) 118 FIELD(CPUCFG1, PGMMU, 2, 1) 119 FIELD(CPUCFG1, IOCSR, 3, 1) 120 FIELD(CPUCFG1, PALEN, 4, 8) 121 FIELD(CPUCFG1, VALEN, 12, 8) 122 FIELD(CPUCFG1, UAL, 20, 1) 123 FIELD(CPUCFG1, RI, 21, 1) 124 FIELD(CPUCFG1, EP, 22, 1) 125 FIELD(CPUCFG1, RPLV, 23, 1) 126 FIELD(CPUCFG1, HP, 24, 1) 127 FIELD(CPUCFG1, IOCSR_BRD, 25, 1) 128 FIELD(CPUCFG1, MSG_INT, 26, 1) 129 130 /* cpucfg[2] bits */ 131 FIELD(CPUCFG2, FP, 0, 1) 132 FIELD(CPUCFG2, FP_SP, 1, 1) 133 FIELD(CPUCFG2, FP_DP, 2, 1) 134 FIELD(CPUCFG2, FP_VER, 3, 3) 135 FIELD(CPUCFG2, LSX, 6, 1) 136 FIELD(CPUCFG2, LASX, 7, 1) 137 FIELD(CPUCFG2, COMPLEX, 8, 1) 138 FIELD(CPUCFG2, CRYPTO, 9, 1) 139 FIELD(CPUCFG2, LVZ, 10, 1) 140 FIELD(CPUCFG2, LVZ_VER, 11, 3) 141 FIELD(CPUCFG2, LLFTP, 14, 1) 142 FIELD(CPUCFG2, LLFTP_VER, 15, 3) 143 FIELD(CPUCFG2, LBT_X86, 18, 1) 144 FIELD(CPUCFG2, LBT_ARM, 19, 1) 145 FIELD(CPUCFG2, LBT_MIPS, 20, 1) 146 FIELD(CPUCFG2, LSPW, 21, 1) 147 FIELD(CPUCFG2, LAM, 22, 1) 148 149 /* cpucfg[3] bits */ 150 FIELD(CPUCFG3, CCDMA, 0, 1) 151 FIELD(CPUCFG3, SFB, 1, 1) 152 FIELD(CPUCFG3, UCACC, 2, 1) 153 FIELD(CPUCFG3, LLEXC, 3, 1) 154 FIELD(CPUCFG3, SCDLY, 4, 1) 155 FIELD(CPUCFG3, LLDBAR, 5, 1) 156 FIELD(CPUCFG3, ITLBHMC, 6, 1) 157 FIELD(CPUCFG3, ICHMC, 7, 1) 158 FIELD(CPUCFG3, SPW_LVL, 8, 3) 159 FIELD(CPUCFG3, SPW_HP_HF, 11, 1) 160 FIELD(CPUCFG3, RVA, 12, 1) 161 FIELD(CPUCFG3, RVAMAX, 13, 4) 162 163 /* cpucfg[4] bits */ 164 FIELD(CPUCFG4, CC_FREQ, 0, 32) 165 166 /* cpucfg[5] bits */ 167 FIELD(CPUCFG5, CC_MUL, 0, 16) 168 FIELD(CPUCFG5, CC_DIV, 16, 16) 169 170 /* cpucfg[6] bits */ 171 FIELD(CPUCFG6, PMP, 0, 1) 172 FIELD(CPUCFG6, PMVER, 1, 3) 173 FIELD(CPUCFG6, PMNUM, 4, 4) 174 FIELD(CPUCFG6, PMBITS, 8, 6) 175 FIELD(CPUCFG6, UPM, 14, 1) 176 177 /* cpucfg[16] bits */ 178 FIELD(CPUCFG16, L1_IUPRE, 0, 1) 179 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1) 180 FIELD(CPUCFG16, L1_DPRE, 2, 1) 181 FIELD(CPUCFG16, L2_IUPRE, 3, 1) 182 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1) 183 FIELD(CPUCFG16, L2_IUPRIV, 5, 1) 184 FIELD(CPUCFG16, L2_IUINCL, 6, 1) 185 FIELD(CPUCFG16, L2_DPRE, 7, 1) 186 FIELD(CPUCFG16, L2_DPRIV, 8, 1) 187 FIELD(CPUCFG16, L2_DINCL, 9, 1) 188 FIELD(CPUCFG16, L3_IUPRE, 10, 1) 189 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1) 190 FIELD(CPUCFG16, L3_IUPRIV, 12, 1) 191 FIELD(CPUCFG16, L3_IUINCL, 13, 1) 192 FIELD(CPUCFG16, L3_DPRE, 14, 1) 193 FIELD(CPUCFG16, L3_DPRIV, 15, 1) 194 FIELD(CPUCFG16, L3_DINCL, 16, 1) 195 196 /* cpucfg[17] bits */ 197 FIELD(CPUCFG17, L1IU_WAYS, 0, 16) 198 FIELD(CPUCFG17, L1IU_SETS, 16, 8) 199 FIELD(CPUCFG17, L1IU_SIZE, 24, 7) 200 201 /* cpucfg[18] bits */ 202 FIELD(CPUCFG18, L1D_WAYS, 0, 16) 203 FIELD(CPUCFG18, L1D_SETS, 16, 8) 204 FIELD(CPUCFG18, L1D_SIZE, 24, 7) 205 206 /* cpucfg[19] bits */ 207 FIELD(CPUCFG19, L2IU_WAYS, 0, 16) 208 FIELD(CPUCFG19, L2IU_SETS, 16, 8) 209 FIELD(CPUCFG19, L2IU_SIZE, 24, 7) 210 211 /* cpucfg[20] bits */ 212 FIELD(CPUCFG20, L3IU_WAYS, 0, 16) 213 FIELD(CPUCFG20, L3IU_SETS, 16, 8) 214 FIELD(CPUCFG20, L3IU_SIZE, 24, 7) 215 216 /*CSR_CRMD */ 217 FIELD(CSR_CRMD, PLV, 0, 2) 218 FIELD(CSR_CRMD, IE, 2, 1) 219 FIELD(CSR_CRMD, DA, 3, 1) 220 FIELD(CSR_CRMD, PG, 4, 1) 221 FIELD(CSR_CRMD, DATF, 5, 2) 222 FIELD(CSR_CRMD, DATM, 7, 2) 223 FIELD(CSR_CRMD, WE, 9, 1) 224 225 extern const char * const regnames[32]; 226 extern const char * const fregnames[32]; 227 228 #define N_IRQS 13 229 #define IRQ_TIMER 11 230 #define IRQ_IPI 12 231 232 #define LOONGARCH_STLB 2048 /* 2048 STLB */ 233 #define LOONGARCH_MTLB 64 /* 64 MTLB */ 234 #define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB) 235 236 /* 237 * define the ASID PS E VPPN field of TLB 238 */ 239 FIELD(TLB_MISC, E, 0, 1) 240 FIELD(TLB_MISC, ASID, 1, 10) 241 FIELD(TLB_MISC, VPPN, 13, 35) 242 FIELD(TLB_MISC, PS, 48, 6) 243 244 struct LoongArchTLB { 245 uint64_t tlb_misc; 246 /* Fields corresponding to CSR_TLBELO0/1 */ 247 uint64_t tlb_entry0; 248 uint64_t tlb_entry1; 249 }; 250 typedef struct LoongArchTLB LoongArchTLB; 251 252 typedef struct CPUArchState { 253 uint64_t gpr[32]; 254 uint64_t pc; 255 256 uint64_t fpr[32]; 257 float_status fp_status; 258 bool cf[8]; 259 260 uint32_t fcsr0; 261 uint32_t fcsr0_mask; 262 263 uint32_t cpucfg[21]; 264 265 uint64_t lladdr; /* LL virtual address compared against SC */ 266 uint64_t llval; 267 268 /* LoongArch CSRs */ 269 uint64_t CSR_CRMD; 270 uint64_t CSR_PRMD; 271 uint64_t CSR_EUEN; 272 uint64_t CSR_MISC; 273 uint64_t CSR_ECFG; 274 uint64_t CSR_ESTAT; 275 uint64_t CSR_ERA; 276 uint64_t CSR_BADV; 277 uint64_t CSR_BADI; 278 uint64_t CSR_EENTRY; 279 uint64_t CSR_TLBIDX; 280 uint64_t CSR_TLBEHI; 281 uint64_t CSR_TLBELO0; 282 uint64_t CSR_TLBELO1; 283 uint64_t CSR_ASID; 284 uint64_t CSR_PGDL; 285 uint64_t CSR_PGDH; 286 uint64_t CSR_PGD; 287 uint64_t CSR_PWCL; 288 uint64_t CSR_PWCH; 289 uint64_t CSR_STLBPS; 290 uint64_t CSR_RVACFG; 291 uint64_t CSR_PRCFG1; 292 uint64_t CSR_PRCFG2; 293 uint64_t CSR_PRCFG3; 294 uint64_t CSR_SAVE[16]; 295 uint64_t CSR_TID; 296 uint64_t CSR_TCFG; 297 uint64_t CSR_TVAL; 298 uint64_t CSR_CNTC; 299 uint64_t CSR_TICLR; 300 uint64_t CSR_LLBCTL; 301 uint64_t CSR_IMPCTL1; 302 uint64_t CSR_IMPCTL2; 303 uint64_t CSR_TLBRENTRY; 304 uint64_t CSR_TLBRBADV; 305 uint64_t CSR_TLBRERA; 306 uint64_t CSR_TLBRSAVE; 307 uint64_t CSR_TLBRELO0; 308 uint64_t CSR_TLBRELO1; 309 uint64_t CSR_TLBREHI; 310 uint64_t CSR_TLBRPRMD; 311 uint64_t CSR_MERRCTL; 312 uint64_t CSR_MERRINFO1; 313 uint64_t CSR_MERRINFO2; 314 uint64_t CSR_MERRENTRY; 315 uint64_t CSR_MERRERA; 316 uint64_t CSR_MERRSAVE; 317 uint64_t CSR_CTAG; 318 uint64_t CSR_DMW[4]; 319 uint64_t CSR_DBG; 320 uint64_t CSR_DERA; 321 uint64_t CSR_DSAVE; 322 323 #ifndef CONFIG_USER_ONLY 324 LoongArchTLB tlb[LOONGARCH_TLB_MAX]; 325 326 AddressSpace address_space_iocsr; 327 MemoryRegion system_iocsr; 328 MemoryRegion iocsr_mem; 329 bool load_elf; 330 uint64_t elf_address; 331 #endif 332 } CPULoongArchState; 333 334 /** 335 * LoongArchCPU: 336 * @env: #CPULoongArchState 337 * 338 * A LoongArch CPU. 339 */ 340 struct ArchCPU { 341 /*< private >*/ 342 CPUState parent_obj; 343 /*< public >*/ 344 345 CPUNegativeOffsetState neg; 346 CPULoongArchState env; 347 QEMUTimer timer; 348 349 /* 'compatible' string for this CPU for Linux device trees */ 350 const char *dtb_compatible; 351 }; 352 353 #define TYPE_LOONGARCH_CPU "loongarch-cpu" 354 355 OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, 356 LOONGARCH_CPU) 357 358 /** 359 * LoongArchCPUClass: 360 * @parent_realize: The parent class' realize handler. 361 * @parent_phases: The parent class' reset phase handlers. 362 * 363 * A LoongArch CPU model. 364 */ 365 struct LoongArchCPUClass { 366 /*< private >*/ 367 CPUClass parent_class; 368 /*< public >*/ 369 370 DeviceRealize parent_realize; 371 ResettablePhases parent_phases; 372 }; 373 374 /* 375 * LoongArch CPUs has 4 privilege levels. 376 * 0 for kernel mode, 3 for user mode. 377 * Define an extra index for DA(direct addressing) mode. 378 */ 379 #define MMU_PLV_KERNEL 0 380 #define MMU_PLV_USER 3 381 #define MMU_IDX_KERNEL MMU_PLV_KERNEL 382 #define MMU_IDX_USER MMU_PLV_USER 383 #define MMU_IDX_DA 4 384 385 static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) 386 { 387 #ifdef CONFIG_USER_ONLY 388 return MMU_IDX_USER; 389 #else 390 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { 391 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 392 } 393 return MMU_IDX_DA; 394 #endif 395 } 396 397 /* 398 * LoongArch CPUs hardware flags. 399 */ 400 #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ 401 #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ 402 #define HW_FLAGS_EUEN_FPE 0x04 403 404 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, 405 target_ulong *pc, 406 target_ulong *cs_base, 407 uint32_t *flags) 408 { 409 *pc = env->pc; 410 *cs_base = 0; 411 *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); 412 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; 413 } 414 415 void loongarch_cpu_list(void); 416 417 #define cpu_list loongarch_cpu_list 418 419 #include "exec/cpu-all.h" 420 421 #define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU 422 #define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX 423 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU 424 425 #endif /* LOONGARCH_CPU_H */ 426