xref: /openbmc/qemu/target/loongarch/cpu.h (revision b61af9b0)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * QEMU LoongArch CPU
4  *
5  * Copyright (c) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #ifndef LOONGARCH_CPU_H
9 #define LOONGARCH_CPU_H
10 
11 #include "qemu/int128.h"
12 #include "exec/cpu-defs.h"
13 #include "fpu/softfloat-types.h"
14 #include "hw/registerfields.h"
15 #include "qemu/timer.h"
16 #ifndef CONFIG_USER_ONLY
17 #include "exec/memory.h"
18 #endif
19 #include "cpu-csr.h"
20 #include "cpu-qom.h"
21 
22 #define IOCSRF_TEMP             0
23 #define IOCSRF_NODECNT          1
24 #define IOCSRF_MSI              2
25 #define IOCSRF_EXTIOI           3
26 #define IOCSRF_CSRIPI           4
27 #define IOCSRF_FREQCSR          5
28 #define IOCSRF_FREQSCALE        6
29 #define IOCSRF_DVFSV1           7
30 #define IOCSRF_GMOD             9
31 #define IOCSRF_VM               11
32 
33 #define VERSION_REG             0x0
34 #define FEATURE_REG             0x8
35 #define VENDOR_REG              0x10
36 #define CPUNAME_REG             0x20
37 #define MISC_FUNC_REG           0x420
38 #define IOCSRM_EXTIOI_EN        48
39 
40 #define IOCSR_MEM_SIZE          0x428
41 
42 #define TCG_GUEST_DEFAULT_MO (0)
43 
44 #define FCSR0_M1    0x1f         /* FCSR1 mask, Enables */
45 #define FCSR0_M2    0x1f1f0000   /* FCSR2 mask, Cause and Flags */
46 #define FCSR0_M3    0x300        /* FCSR3 mask, Round Mode */
47 #define FCSR0_RM    8            /* Round Mode bit num on fcsr0 */
48 
49 FIELD(FCSR0, ENABLES, 0, 5)
50 FIELD(FCSR0, RM, 8, 2)
51 FIELD(FCSR0, FLAGS, 16, 5)
52 FIELD(FCSR0, CAUSE, 24, 5)
53 
54 #define GET_FP_CAUSE(REG)      FIELD_EX32(REG, FCSR0, CAUSE)
55 #define SET_FP_CAUSE(REG, V) \
56     do { \
57         (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
58     } while (0)
59 #define UPDATE_FP_CAUSE(REG, V) \
60     do { \
61         (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \
62     } while (0)
63 
64 #define GET_FP_ENABLES(REG)    FIELD_EX32(REG, FCSR0, ENABLES)
65 #define SET_FP_ENABLES(REG, V) \
66     do { \
67         (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
68     } while (0)
69 
70 #define GET_FP_FLAGS(REG)      FIELD_EX32(REG, FCSR0, FLAGS)
71 #define SET_FP_FLAGS(REG, V) \
72     do { \
73         (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
74     } while (0)
75 
76 #define UPDATE_FP_FLAGS(REG, V) \
77     do { \
78         (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
79     } while (0)
80 
81 #define FP_INEXACT        1
82 #define FP_UNDERFLOW      2
83 #define FP_OVERFLOW       4
84 #define FP_DIV0           8
85 #define FP_INVALID        16
86 
87 #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
88 #define EXCODE_MCODE(code)    ( (code) & 0x3f )
89 #define EXCODE_SUBCODE(code)  ( (code) >> 6 )
90 
91 #define  EXCCODE_EXTERNAL_INT        64   /* plus external interrupt number */
92 #define  EXCCODE_INT                 EXCODE(0, 0)
93 #define  EXCCODE_PIL                 EXCODE(1, 0)
94 #define  EXCCODE_PIS                 EXCODE(2, 0)
95 #define  EXCCODE_PIF                 EXCODE(3, 0)
96 #define  EXCCODE_PME                 EXCODE(4, 0)
97 #define  EXCCODE_PNR                 EXCODE(5, 0)
98 #define  EXCCODE_PNX                 EXCODE(6, 0)
99 #define  EXCCODE_PPI                 EXCODE(7, 0)
100 #define  EXCCODE_ADEF                EXCODE(8, 0) /* Different exception subcode */
101 #define  EXCCODE_ADEM                EXCODE(8, 1)
102 #define  EXCCODE_ALE                 EXCODE(9, 0)
103 #define  EXCCODE_BCE                 EXCODE(10, 0)
104 #define  EXCCODE_SYS                 EXCODE(11, 0)
105 #define  EXCCODE_BRK                 EXCODE(12, 0)
106 #define  EXCCODE_INE                 EXCODE(13, 0)
107 #define  EXCCODE_IPE                 EXCODE(14, 0)
108 #define  EXCCODE_FPD                 EXCODE(15, 0)
109 #define  EXCCODE_SXD                 EXCODE(16, 0)
110 #define  EXCCODE_ASXD                EXCODE(17, 0)
111 #define  EXCCODE_FPE                 EXCODE(18, 0) /* Different exception subcode */
112 #define  EXCCODE_VFPE                EXCODE(18, 1)
113 #define  EXCCODE_WPEF                EXCODE(19, 0) /* Different exception subcode */
114 #define  EXCCODE_WPEM                EXCODE(19, 1)
115 #define  EXCCODE_BTD                 EXCODE(20, 0)
116 #define  EXCCODE_BTE                 EXCODE(21, 0)
117 #define  EXCCODE_DBP                 EXCODE(26, 0) /* Reserved subcode used for debug */
118 
119 /* cpucfg[0] bits */
120 FIELD(CPUCFG0, PRID, 0, 32)
121 
122 /* cpucfg[1] bits */
123 FIELD(CPUCFG1, ARCH, 0, 2)
124 FIELD(CPUCFG1, PGMMU, 2, 1)
125 FIELD(CPUCFG1, IOCSR, 3, 1)
126 FIELD(CPUCFG1, PALEN, 4, 8)
127 FIELD(CPUCFG1, VALEN, 12, 8)
128 FIELD(CPUCFG1, UAL, 20, 1)
129 FIELD(CPUCFG1, RI, 21, 1)
130 FIELD(CPUCFG1, EP, 22, 1)
131 FIELD(CPUCFG1, RPLV, 23, 1)
132 FIELD(CPUCFG1, HP, 24, 1)
133 FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
134 FIELD(CPUCFG1, MSG_INT, 26, 1)
135 
136 /* cpucfg[1].arch */
137 #define CPUCFG1_ARCH_LA32R       0
138 #define CPUCFG1_ARCH_LA32        1
139 #define CPUCFG1_ARCH_LA64        2
140 
141 /* cpucfg[2] bits */
142 FIELD(CPUCFG2, FP, 0, 1)
143 FIELD(CPUCFG2, FP_SP, 1, 1)
144 FIELD(CPUCFG2, FP_DP, 2, 1)
145 FIELD(CPUCFG2, FP_VER, 3, 3)
146 FIELD(CPUCFG2, LSX, 6, 1)
147 FIELD(CPUCFG2, LASX, 7, 1)
148 FIELD(CPUCFG2, COMPLEX, 8, 1)
149 FIELD(CPUCFG2, CRYPTO, 9, 1)
150 FIELD(CPUCFG2, LVZ, 10, 1)
151 FIELD(CPUCFG2, LVZ_VER, 11, 3)
152 FIELD(CPUCFG2, LLFTP, 14, 1)
153 FIELD(CPUCFG2, LLFTP_VER, 15, 3)
154 FIELD(CPUCFG2, LBT_X86, 18, 1)
155 FIELD(CPUCFG2, LBT_ARM, 19, 1)
156 FIELD(CPUCFG2, LBT_MIPS, 20, 1)
157 FIELD(CPUCFG2, LSPW, 21, 1)
158 FIELD(CPUCFG2, LAM, 22, 1)
159 
160 /* cpucfg[3] bits */
161 FIELD(CPUCFG3, CCDMA, 0, 1)
162 FIELD(CPUCFG3, SFB, 1, 1)
163 FIELD(CPUCFG3, UCACC, 2, 1)
164 FIELD(CPUCFG3, LLEXC, 3, 1)
165 FIELD(CPUCFG3, SCDLY, 4, 1)
166 FIELD(CPUCFG3, LLDBAR, 5, 1)
167 FIELD(CPUCFG3, ITLBHMC, 6, 1)
168 FIELD(CPUCFG3, ICHMC, 7, 1)
169 FIELD(CPUCFG3, SPW_LVL, 8, 3)
170 FIELD(CPUCFG3, SPW_HP_HF, 11, 1)
171 FIELD(CPUCFG3, RVA, 12, 1)
172 FIELD(CPUCFG3, RVAMAX, 13, 4)
173 
174 /* cpucfg[4] bits */
175 FIELD(CPUCFG4, CC_FREQ, 0, 32)
176 
177 /* cpucfg[5] bits */
178 FIELD(CPUCFG5, CC_MUL, 0, 16)
179 FIELD(CPUCFG5, CC_DIV, 16, 16)
180 
181 /* cpucfg[6] bits */
182 FIELD(CPUCFG6, PMP, 0, 1)
183 FIELD(CPUCFG6, PMVER, 1, 3)
184 FIELD(CPUCFG6, PMNUM, 4, 4)
185 FIELD(CPUCFG6, PMBITS, 8, 6)
186 FIELD(CPUCFG6, UPM, 14, 1)
187 
188 /* cpucfg[16] bits */
189 FIELD(CPUCFG16, L1_IUPRE, 0, 1)
190 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1)
191 FIELD(CPUCFG16, L1_DPRE, 2, 1)
192 FIELD(CPUCFG16, L2_IUPRE, 3, 1)
193 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1)
194 FIELD(CPUCFG16, L2_IUPRIV, 5, 1)
195 FIELD(CPUCFG16, L2_IUINCL, 6, 1)
196 FIELD(CPUCFG16, L2_DPRE, 7, 1)
197 FIELD(CPUCFG16, L2_DPRIV, 8, 1)
198 FIELD(CPUCFG16, L2_DINCL, 9, 1)
199 FIELD(CPUCFG16, L3_IUPRE, 10, 1)
200 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1)
201 FIELD(CPUCFG16, L3_IUPRIV, 12, 1)
202 FIELD(CPUCFG16, L3_IUINCL, 13, 1)
203 FIELD(CPUCFG16, L3_DPRE, 14, 1)
204 FIELD(CPUCFG16, L3_DPRIV, 15, 1)
205 FIELD(CPUCFG16, L3_DINCL, 16, 1)
206 
207 /* cpucfg[17] bits */
208 FIELD(CPUCFG17, L1IU_WAYS, 0, 16)
209 FIELD(CPUCFG17, L1IU_SETS, 16, 8)
210 FIELD(CPUCFG17, L1IU_SIZE, 24, 7)
211 
212 /* cpucfg[18] bits */
213 FIELD(CPUCFG18, L1D_WAYS, 0, 16)
214 FIELD(CPUCFG18, L1D_SETS, 16, 8)
215 FIELD(CPUCFG18, L1D_SIZE, 24, 7)
216 
217 /* cpucfg[19] bits */
218 FIELD(CPUCFG19, L2IU_WAYS, 0, 16)
219 FIELD(CPUCFG19, L2IU_SETS, 16, 8)
220 FIELD(CPUCFG19, L2IU_SIZE, 24, 7)
221 
222 /* cpucfg[20] bits */
223 FIELD(CPUCFG20, L3IU_WAYS, 0, 16)
224 FIELD(CPUCFG20, L3IU_SETS, 16, 8)
225 FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
226 
227 /*CSR_CRMD */
228 FIELD(CSR_CRMD, PLV, 0, 2)
229 FIELD(CSR_CRMD, IE, 2, 1)
230 FIELD(CSR_CRMD, DA, 3, 1)
231 FIELD(CSR_CRMD, PG, 4, 1)
232 FIELD(CSR_CRMD, DATF, 5, 2)
233 FIELD(CSR_CRMD, DATM, 7, 2)
234 FIELD(CSR_CRMD, WE, 9, 1)
235 
236 extern const char * const regnames[32];
237 extern const char * const fregnames[32];
238 
239 #define N_IRQS      13
240 #define IRQ_TIMER   11
241 #define IRQ_IPI     12
242 
243 #define LOONGARCH_STLB         2048 /* 2048 STLB */
244 #define LOONGARCH_MTLB         64   /* 64 MTLB */
245 #define LOONGARCH_TLB_MAX      (LOONGARCH_STLB + LOONGARCH_MTLB)
246 
247 /*
248  * define the ASID PS E VPPN field of TLB
249  */
250 FIELD(TLB_MISC, E, 0, 1)
251 FIELD(TLB_MISC, ASID, 1, 10)
252 FIELD(TLB_MISC, VPPN, 13, 35)
253 FIELD(TLB_MISC, PS, 48, 6)
254 
255 #define LSX_LEN    (128)
256 #define LASX_LEN   (256)
257 
258 typedef union VReg {
259     int8_t   B[LASX_LEN / 8];
260     int16_t  H[LASX_LEN / 16];
261     int32_t  W[LASX_LEN / 32];
262     int64_t  D[LASX_LEN / 64];
263     uint8_t  UB[LASX_LEN / 8];
264     uint16_t UH[LASX_LEN / 16];
265     uint32_t UW[LASX_LEN / 32];
266     uint64_t UD[LASX_LEN / 64];
267     Int128   Q[LASX_LEN / 128];
268 } VReg;
269 
270 typedef union fpr_t fpr_t;
271 union fpr_t {
272     VReg  vreg;
273 };
274 
275 struct LoongArchTLB {
276     uint64_t tlb_misc;
277     /* Fields corresponding to CSR_TLBELO0/1 */
278     uint64_t tlb_entry0;
279     uint64_t tlb_entry1;
280 };
281 typedef struct LoongArchTLB LoongArchTLB;
282 
283 typedef struct CPUArchState {
284     uint64_t gpr[32];
285     uint64_t pc;
286 
287     fpr_t fpr[32];
288     float_status fp_status;
289     bool cf[8];
290 
291     uint32_t fcsr0;
292     uint32_t fcsr0_mask;
293 
294     uint32_t cpucfg[21];
295 
296     uint64_t lladdr; /* LL virtual address compared against SC */
297     uint64_t llval;
298 
299     /* LoongArch CSRs */
300     uint64_t CSR_CRMD;
301     uint64_t CSR_PRMD;
302     uint64_t CSR_EUEN;
303     uint64_t CSR_MISC;
304     uint64_t CSR_ECFG;
305     uint64_t CSR_ESTAT;
306     uint64_t CSR_ERA;
307     uint64_t CSR_BADV;
308     uint64_t CSR_BADI;
309     uint64_t CSR_EENTRY;
310     uint64_t CSR_TLBIDX;
311     uint64_t CSR_TLBEHI;
312     uint64_t CSR_TLBELO0;
313     uint64_t CSR_TLBELO1;
314     uint64_t CSR_ASID;
315     uint64_t CSR_PGDL;
316     uint64_t CSR_PGDH;
317     uint64_t CSR_PGD;
318     uint64_t CSR_PWCL;
319     uint64_t CSR_PWCH;
320     uint64_t CSR_STLBPS;
321     uint64_t CSR_RVACFG;
322     uint64_t CSR_CPUID;
323     uint64_t CSR_PRCFG1;
324     uint64_t CSR_PRCFG2;
325     uint64_t CSR_PRCFG3;
326     uint64_t CSR_SAVE[16];
327     uint64_t CSR_TID;
328     uint64_t CSR_TCFG;
329     uint64_t CSR_TVAL;
330     uint64_t CSR_CNTC;
331     uint64_t CSR_TICLR;
332     uint64_t CSR_LLBCTL;
333     uint64_t CSR_IMPCTL1;
334     uint64_t CSR_IMPCTL2;
335     uint64_t CSR_TLBRENTRY;
336     uint64_t CSR_TLBRBADV;
337     uint64_t CSR_TLBRERA;
338     uint64_t CSR_TLBRSAVE;
339     uint64_t CSR_TLBRELO0;
340     uint64_t CSR_TLBRELO1;
341     uint64_t CSR_TLBREHI;
342     uint64_t CSR_TLBRPRMD;
343     uint64_t CSR_MERRCTL;
344     uint64_t CSR_MERRINFO1;
345     uint64_t CSR_MERRINFO2;
346     uint64_t CSR_MERRENTRY;
347     uint64_t CSR_MERRERA;
348     uint64_t CSR_MERRSAVE;
349     uint64_t CSR_CTAG;
350     uint64_t CSR_DMW[4];
351     uint64_t CSR_DBG;
352     uint64_t CSR_DERA;
353     uint64_t CSR_DSAVE;
354 
355 #ifndef CONFIG_USER_ONLY
356     LoongArchTLB  tlb[LOONGARCH_TLB_MAX];
357 
358     AddressSpace *address_space_iocsr;
359     bool load_elf;
360     uint64_t elf_address;
361     uint32_t mp_state;
362     /* Store ipistate to access from this struct */
363     DeviceState *ipistate;
364 #endif
365 } CPULoongArchState;
366 
367 /**
368  * LoongArchCPU:
369  * @env: #CPULoongArchState
370  *
371  * A LoongArch CPU.
372  */
373 struct ArchCPU {
374     CPUState parent_obj;
375 
376     CPULoongArchState env;
377     QEMUTimer timer;
378     uint32_t  phy_id;
379 
380     /* 'compatible' string for this CPU for Linux device trees */
381     const char *dtb_compatible;
382     /* used by KVM_REG_LOONGARCH_COUNTER ioctl to access guest time counters */
383     uint64_t kvm_state_counter;
384 };
385 
386 /**
387  * LoongArchCPUClass:
388  * @parent_realize: The parent class' realize handler.
389  * @parent_phases: The parent class' reset phase handlers.
390  *
391  * A LoongArch CPU model.
392  */
393 struct LoongArchCPUClass {
394     CPUClass parent_class;
395 
396     DeviceRealize parent_realize;
397     ResettablePhases parent_phases;
398 };
399 
400 /*
401  * LoongArch CPUs has 4 privilege levels.
402  * 0 for kernel mode, 3 for user mode.
403  * Define an extra index for DA(direct addressing) mode.
404  */
405 #define MMU_PLV_KERNEL   0
406 #define MMU_PLV_USER     3
407 #define MMU_KERNEL_IDX   MMU_PLV_KERNEL
408 #define MMU_USER_IDX     MMU_PLV_USER
409 #define MMU_DA_IDX       4
410 
411 static inline bool is_la64(CPULoongArchState *env)
412 {
413     return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
414 }
415 
416 static inline bool is_va32(CPULoongArchState *env)
417 {
418     /* VA32 if !LA64 or VA32L[1-3] */
419     bool va32 = !is_la64(env);
420     uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
421     if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) {
422         va32 = true;
423     }
424     return va32;
425 }
426 
427 static inline void set_pc(CPULoongArchState *env, uint64_t value)
428 {
429     if (is_va32(env)) {
430         env->pc = (uint32_t)value;
431     } else {
432         env->pc = value;
433     }
434 }
435 
436 /*
437  * LoongArch CPUs hardware flags.
438  */
439 #define HW_FLAGS_PLV_MASK   R_CSR_CRMD_PLV_MASK  /* 0x03 */
440 #define HW_FLAGS_EUEN_FPE   0x04
441 #define HW_FLAGS_EUEN_SXE   0x08
442 #define HW_FLAGS_CRMD_PG    R_CSR_CRMD_PG_MASK   /* 0x10 */
443 #define HW_FLAGS_VA32       0x20
444 #define HW_FLAGS_EUEN_ASXE  0x40
445 
446 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
447                                         uint64_t *cs_base, uint32_t *flags)
448 {
449     *pc = env->pc;
450     *cs_base = 0;
451     *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
452     *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
453     *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
454     *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
455     *flags |= is_va32(env) * HW_FLAGS_VA32;
456 }
457 
458 #include "exec/cpu-all.h"
459 
460 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
461 
462 void loongarch_cpu_post_init(Object *obj);
463 
464 #endif /* LOONGARCH_CPU_H */
465