1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "sysemu/qtest.h" 14 #include "sysemu/tcg.h" 15 #include "sysemu/kvm.h" 16 #include "kvm/kvm_loongarch.h" 17 #include "exec/exec-all.h" 18 #include "cpu.h" 19 #include "internals.h" 20 #include "fpu/softfloat-helpers.h" 21 #include "cpu-csr.h" 22 #ifndef CONFIG_USER_ONLY 23 #include "sysemu/reset.h" 24 #endif 25 #include "vec.h" 26 #ifdef CONFIG_KVM 27 #include <linux/kvm.h> 28 #endif 29 #ifdef CONFIG_TCG 30 #include "exec/cpu_ldst.h" 31 #include "tcg/tcg.h" 32 #endif 33 34 const char * const regnames[32] = { 35 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 36 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 37 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 38 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 39 }; 40 41 const char * const fregnames[32] = { 42 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 43 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 44 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 45 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 46 }; 47 48 static const char * const excp_names[] = { 49 [EXCCODE_INT] = "Interrupt", 50 [EXCCODE_PIL] = "Page invalid exception for load", 51 [EXCCODE_PIS] = "Page invalid exception for store", 52 [EXCCODE_PIF] = "Page invalid exception for fetch", 53 [EXCCODE_PME] = "Page modified exception", 54 [EXCCODE_PNR] = "Page Not Readable exception", 55 [EXCCODE_PNX] = "Page Not Executable exception", 56 [EXCCODE_PPI] = "Page Privilege error", 57 [EXCCODE_ADEF] = "Address error for instruction fetch", 58 [EXCCODE_ADEM] = "Address error for Memory access", 59 [EXCCODE_SYS] = "Syscall", 60 [EXCCODE_BRK] = "Break", 61 [EXCCODE_INE] = "Instruction Non-Existent", 62 [EXCCODE_IPE] = "Instruction privilege error", 63 [EXCCODE_FPD] = "Floating Point Disabled", 64 [EXCCODE_FPE] = "Floating Point Exception", 65 [EXCCODE_DBP] = "Debug breakpoint", 66 [EXCCODE_BCE] = "Bound Check Exception", 67 [EXCCODE_SXD] = "128 bit vector instructions Disable exception", 68 [EXCCODE_ASXD] = "256 bit vector instructions Disable exception", 69 }; 70 71 const char *loongarch_exception_name(int32_t exception) 72 { 73 assert(excp_names[exception]); 74 return excp_names[exception]; 75 } 76 77 void G_NORETURN do_raise_exception(CPULoongArchState *env, 78 uint32_t exception, 79 uintptr_t pc) 80 { 81 CPUState *cs = env_cpu(env); 82 83 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", 84 __func__, 85 exception, 86 loongarch_exception_name(exception)); 87 cs->exception_index = exception; 88 89 cpu_loop_exit_restore(cs, pc); 90 } 91 92 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 93 { 94 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 95 CPULoongArchState *env = &cpu->env; 96 97 set_pc(env, value); 98 } 99 100 static vaddr loongarch_cpu_get_pc(CPUState *cs) 101 { 102 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 103 CPULoongArchState *env = &cpu->env; 104 105 return env->pc; 106 } 107 108 #ifndef CONFIG_USER_ONLY 109 #include "hw/loongarch/virt.h" 110 111 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 112 { 113 LoongArchCPU *cpu = opaque; 114 CPULoongArchState *env = &cpu->env; 115 CPUState *cs = CPU(cpu); 116 117 if (irq < 0 || irq >= N_IRQS) { 118 return; 119 } 120 121 if (kvm_enabled()) { 122 kvm_loongarch_set_interrupt(cpu, irq, level); 123 } else if (tcg_enabled()) { 124 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 125 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 126 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 127 } else { 128 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 129 } 130 } 131 } 132 133 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 134 { 135 bool ret = 0; 136 137 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 138 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 139 140 return ret; 141 } 142 143 /* Check if there is pending and not masked out interrupt */ 144 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 145 { 146 uint32_t pending; 147 uint32_t status; 148 149 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 150 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 151 152 return (pending & status) != 0; 153 } 154 #endif 155 156 #ifdef CONFIG_TCG 157 #ifndef CONFIG_USER_ONLY 158 static void loongarch_cpu_do_interrupt(CPUState *cs) 159 { 160 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 161 CPULoongArchState *env = &cpu->env; 162 bool update_badinstr = 1; 163 int cause = -1; 164 const char *name; 165 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 166 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 167 168 if (cs->exception_index != EXCCODE_INT) { 169 if (cs->exception_index < 0 || 170 cs->exception_index >= ARRAY_SIZE(excp_names)) { 171 name = "unknown"; 172 } else { 173 name = excp_names[cs->exception_index]; 174 } 175 176 qemu_log_mask(CPU_LOG_INT, 177 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 178 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, 179 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); 180 } 181 182 switch (cs->exception_index) { 183 case EXCCODE_DBP: 184 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 185 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 186 goto set_DERA; 187 set_DERA: 188 env->CSR_DERA = env->pc; 189 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 190 set_pc(env, env->CSR_EENTRY + 0x480); 191 break; 192 case EXCCODE_INT: 193 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 194 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 195 goto set_DERA; 196 } 197 QEMU_FALLTHROUGH; 198 case EXCCODE_PIF: 199 case EXCCODE_ADEF: 200 cause = cs->exception_index; 201 update_badinstr = 0; 202 break; 203 case EXCCODE_SYS: 204 case EXCCODE_BRK: 205 case EXCCODE_INE: 206 case EXCCODE_IPE: 207 case EXCCODE_FPD: 208 case EXCCODE_FPE: 209 case EXCCODE_SXD: 210 case EXCCODE_ASXD: 211 env->CSR_BADV = env->pc; 212 QEMU_FALLTHROUGH; 213 case EXCCODE_BCE: 214 case EXCCODE_ADEM: 215 case EXCCODE_PIL: 216 case EXCCODE_PIS: 217 case EXCCODE_PME: 218 case EXCCODE_PNR: 219 case EXCCODE_PNX: 220 case EXCCODE_PPI: 221 cause = cs->exception_index; 222 break; 223 default: 224 qemu_log("Error: exception(%d) has not been supported\n", 225 cs->exception_index); 226 abort(); 227 } 228 229 if (update_badinstr) { 230 env->CSR_BADI = cpu_ldl_code(env, env->pc); 231 } 232 233 /* Save PLV and IE */ 234 if (tlbfill) { 235 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 236 FIELD_EX64(env->CSR_CRMD, 237 CSR_CRMD, PLV)); 238 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 239 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 240 /* set the DA mode */ 241 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 242 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 243 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 244 PC, (env->pc >> 2)); 245 } else { 246 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 247 EXCODE_MCODE(cause)); 248 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 249 EXCODE_SUBCODE(cause)); 250 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 251 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 252 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 253 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 254 env->CSR_ERA = env->pc; 255 } 256 257 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 258 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 259 260 if (vec_size) { 261 vec_size = (1 << vec_size) * 4; 262 } 263 264 if (cs->exception_index == EXCCODE_INT) { 265 /* Interrupt */ 266 uint32_t vector = 0; 267 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 268 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 269 270 /* Find the highest-priority interrupt. */ 271 vector = 31 - clz32(pending); 272 set_pc(env, env->CSR_EENTRY + \ 273 (EXCCODE_EXTERNAL_INT + vector) * vec_size); 274 qemu_log_mask(CPU_LOG_INT, 275 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 276 " cause %d\n" " A " TARGET_FMT_lx " D " 277 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 278 TARGET_FMT_lx "\n", 279 __func__, env->pc, env->CSR_ERA, 280 cause, env->CSR_BADV, env->CSR_DERA, vector, 281 env->CSR_ECFG, env->CSR_ESTAT); 282 } else { 283 if (tlbfill) { 284 set_pc(env, env->CSR_TLBRENTRY); 285 } else { 286 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); 287 } 288 qemu_log_mask(CPU_LOG_INT, 289 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 290 " cause %d%s\n, ESTAT " TARGET_FMT_lx 291 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 292 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 293 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 294 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 295 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 296 env->CSR_ECFG, 297 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 298 env->CSR_BADI, env->gpr[11], cs->cpu_index, 299 env->CSR_ASID); 300 } 301 cs->exception_index = -1; 302 } 303 304 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 305 vaddr addr, unsigned size, 306 MMUAccessType access_type, 307 int mmu_idx, MemTxAttrs attrs, 308 MemTxResult response, 309 uintptr_t retaddr) 310 { 311 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 312 CPULoongArchState *env = &cpu->env; 313 314 if (access_type == MMU_INST_FETCH) { 315 do_raise_exception(env, EXCCODE_ADEF, retaddr); 316 } else { 317 do_raise_exception(env, EXCCODE_ADEM, retaddr); 318 } 319 } 320 321 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 322 { 323 if (interrupt_request & CPU_INTERRUPT_HARD) { 324 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 325 CPULoongArchState *env = &cpu->env; 326 327 if (cpu_loongarch_hw_interrupts_enabled(env) && 328 cpu_loongarch_hw_interrupts_pending(env)) { 329 /* Raise it */ 330 cs->exception_index = EXCCODE_INT; 331 loongarch_cpu_do_interrupt(cs); 332 return true; 333 } 334 } 335 return false; 336 } 337 #endif 338 339 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 340 const TranslationBlock *tb) 341 { 342 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 343 CPULoongArchState *env = &cpu->env; 344 345 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 346 set_pc(env, tb->pc); 347 } 348 349 static void loongarch_restore_state_to_opc(CPUState *cs, 350 const TranslationBlock *tb, 351 const uint64_t *data) 352 { 353 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 354 CPULoongArchState *env = &cpu->env; 355 356 set_pc(env, data[0]); 357 } 358 #endif /* CONFIG_TCG */ 359 360 static bool loongarch_cpu_has_work(CPUState *cs) 361 { 362 #ifdef CONFIG_USER_ONLY 363 return true; 364 #else 365 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 366 CPULoongArchState *env = &cpu->env; 367 bool has_work = false; 368 369 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 370 cpu_loongarch_hw_interrupts_pending(env)) { 371 has_work = true; 372 } 373 374 return has_work; 375 #endif 376 } 377 378 static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) 379 { 380 CPULoongArchState *env = cpu_env(cs); 381 382 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { 383 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 384 } 385 return MMU_DA_IDX; 386 } 387 388 static void loongarch_la464_initfn(Object *obj) 389 { 390 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 391 CPULoongArchState *env = &cpu->env; 392 int i; 393 394 for (i = 0; i < 21; i++) { 395 env->cpucfg[i] = 0x0; 396 } 397 398 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 399 env->cpucfg[0] = 0x14c010; /* PRID */ 400 401 uint32_t data = 0; 402 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 403 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 404 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 405 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); 406 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 407 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 408 data = FIELD_DP32(data, CPUCFG1, RI, 1); 409 data = FIELD_DP32(data, CPUCFG1, EP, 1); 410 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 411 data = FIELD_DP32(data, CPUCFG1, HP, 1); 412 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 413 env->cpucfg[1] = data; 414 415 data = 0; 416 data = FIELD_DP32(data, CPUCFG2, FP, 1); 417 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 418 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 419 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 420 data = FIELD_DP32(data, CPUCFG2, LSX, 1), 421 data = FIELD_DP32(data, CPUCFG2, LASX, 1), 422 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 423 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 424 data = FIELD_DP32(data, CPUCFG2, LSPW, 1); 425 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 426 env->cpucfg[2] = data; 427 428 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 429 430 data = 0; 431 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 432 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 433 env->cpucfg[5] = data; 434 435 data = 0; 436 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 437 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 438 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 439 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 440 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 441 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 442 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 443 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 444 env->cpucfg[16] = data; 445 446 data = 0; 447 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 448 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 449 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 450 env->cpucfg[17] = data; 451 452 data = 0; 453 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 454 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 455 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 456 env->cpucfg[18] = data; 457 458 data = 0; 459 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 460 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 461 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 462 env->cpucfg[19] = data; 463 464 data = 0; 465 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 466 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 467 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 468 env->cpucfg[20] = data; 469 470 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 471 loongarch_cpu_post_init(obj); 472 } 473 474 static void loongarch_la132_initfn(Object *obj) 475 { 476 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 477 CPULoongArchState *env = &cpu->env; 478 479 int i; 480 481 for (i = 0; i < 21; i++) { 482 env->cpucfg[i] = 0x0; 483 } 484 485 cpu->dtb_compatible = "loongarch,Loongson-1C103"; 486 env->cpucfg[0] = 0x148042; /* PRID */ 487 488 uint32_t data = 0; 489 data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ 490 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 491 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 492 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ 493 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ 494 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 495 data = FIELD_DP32(data, CPUCFG1, RI, 0); 496 data = FIELD_DP32(data, CPUCFG1, EP, 0); 497 data = FIELD_DP32(data, CPUCFG1, RPLV, 0); 498 data = FIELD_DP32(data, CPUCFG1, HP, 1); 499 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 500 env->cpucfg[1] = data; 501 } 502 503 static void loongarch_max_initfn(Object *obj) 504 { 505 /* '-cpu max' for TCG: we use cpu la464. */ 506 loongarch_la464_initfn(obj); 507 } 508 509 static void loongarch_cpu_reset_hold(Object *obj) 510 { 511 CPUState *cs = CPU(obj); 512 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 513 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); 514 CPULoongArchState *env = &cpu->env; 515 516 if (lacc->parent_phases.hold) { 517 lacc->parent_phases.hold(obj); 518 } 519 520 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 521 env->fcsr0 = 0x0; 522 523 int n; 524 /* Set csr registers value after reset */ 525 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 526 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 527 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 528 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 529 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); 530 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); 531 532 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 533 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 534 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 535 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 536 537 env->CSR_MISC = 0; 538 539 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 540 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 541 542 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 543 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 544 env->CSR_CPUID = cs->cpu_index; 545 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 546 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 547 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 548 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 549 env->CSR_TID = cs->cpu_index; 550 551 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 552 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 553 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 554 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 555 556 for (n = 0; n < 4; n++) { 557 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 558 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 559 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 560 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 561 } 562 563 #ifndef CONFIG_USER_ONLY 564 env->pc = 0x1c000000; 565 memset(env->tlb, 0, sizeof(env->tlb)); 566 if (kvm_enabled()) { 567 kvm_arch_reset_vcpu(env); 568 } 569 #endif 570 571 #ifdef CONFIG_TCG 572 restore_fp_status(env); 573 #endif 574 cs->exception_index = -1; 575 } 576 577 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 578 { 579 info->print_insn = print_insn_loongarch; 580 } 581 582 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 583 { 584 CPUState *cs = CPU(dev); 585 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 586 Error *local_err = NULL; 587 588 cpu_exec_realizefn(cs, &local_err); 589 if (local_err != NULL) { 590 error_propagate(errp, local_err); 591 return; 592 } 593 594 loongarch_cpu_register_gdb_regs_for_features(cs); 595 596 cpu_reset(cs); 597 qemu_init_vcpu(cs); 598 599 lacc->parent_realize(dev, errp); 600 } 601 602 static bool loongarch_get_lsx(Object *obj, Error **errp) 603 { 604 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 605 bool ret; 606 607 if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) { 608 ret = true; 609 } else { 610 ret = false; 611 } 612 return ret; 613 } 614 615 static void loongarch_set_lsx(Object *obj, bool value, Error **errp) 616 { 617 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 618 619 if (value) { 620 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1); 621 } else { 622 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 0); 623 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0); 624 } 625 } 626 627 static bool loongarch_get_lasx(Object *obj, Error **errp) 628 { 629 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 630 bool ret; 631 632 if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) { 633 ret = true; 634 } else { 635 ret = false; 636 } 637 return ret; 638 } 639 640 static void loongarch_set_lasx(Object *obj, bool value, Error **errp) 641 { 642 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 643 644 if (value) { 645 if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) { 646 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1); 647 } 648 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 1); 649 } else { 650 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0); 651 } 652 } 653 654 void loongarch_cpu_post_init(Object *obj) 655 { 656 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 657 658 if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) { 659 object_property_add_bool(obj, "lsx", loongarch_get_lsx, 660 loongarch_set_lsx); 661 } 662 if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) { 663 object_property_add_bool(obj, "lasx", loongarch_get_lasx, 664 loongarch_set_lasx); 665 } 666 } 667 668 static void loongarch_cpu_init(Object *obj) 669 { 670 #ifndef CONFIG_USER_ONLY 671 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 672 673 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 674 #ifdef CONFIG_TCG 675 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 676 &loongarch_constant_timer_cb, cpu); 677 #endif 678 #endif 679 } 680 681 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 682 { 683 ObjectClass *oc; 684 685 oc = object_class_by_name(cpu_model); 686 if (!oc) { 687 g_autofree char *typename 688 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 689 oc = object_class_by_name(typename); 690 } 691 692 return oc; 693 } 694 695 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 696 { 697 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 698 CPULoongArchState *env = &cpu->env; 699 int i; 700 701 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 702 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, 703 get_float_exception_flags(&env->fp_status)); 704 705 /* gpr */ 706 for (i = 0; i < 32; i++) { 707 if ((i & 3) == 0) { 708 qemu_fprintf(f, " GPR%02d:", i); 709 } 710 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 711 if ((i & 3) == 3) { 712 qemu_fprintf(f, "\n"); 713 } 714 } 715 716 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); 717 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); 718 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); 719 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); 720 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); 721 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); 722 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); 723 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); 724 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," 725 " PRCFG3=%016" PRIx64 "\n", 726 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); 727 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); 728 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); 729 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); 730 qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG); 731 qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL); 732 733 /* fpr */ 734 if (flags & CPU_DUMP_FPU) { 735 for (i = 0; i < 32; i++) { 736 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); 737 if ((i & 3) == 3) { 738 qemu_fprintf(f, "\n"); 739 } 740 } 741 } 742 } 743 744 #ifdef CONFIG_TCG 745 #include "hw/core/tcg-cpu-ops.h" 746 747 static const TCGCPUOps loongarch_tcg_ops = { 748 .initialize = loongarch_translate_init, 749 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 750 .restore_state_to_opc = loongarch_restore_state_to_opc, 751 752 #ifndef CONFIG_USER_ONLY 753 .tlb_fill = loongarch_cpu_tlb_fill, 754 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 755 .do_interrupt = loongarch_cpu_do_interrupt, 756 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 757 #endif 758 }; 759 #endif /* CONFIG_TCG */ 760 761 #ifndef CONFIG_USER_ONLY 762 #include "hw/core/sysemu-cpu-ops.h" 763 764 static const struct SysemuCPUOps loongarch_sysemu_ops = { 765 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 766 }; 767 768 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) 769 { 770 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 771 772 return cpu->phy_id; 773 } 774 #endif 775 776 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 777 { 778 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 779 CPUClass *cc = CPU_CLASS(c); 780 DeviceClass *dc = DEVICE_CLASS(c); 781 ResettableClass *rc = RESETTABLE_CLASS(c); 782 783 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 784 &lacc->parent_realize); 785 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, 786 &lacc->parent_phases); 787 788 cc->class_by_name = loongarch_cpu_class_by_name; 789 cc->has_work = loongarch_cpu_has_work; 790 cc->mmu_index = loongarch_cpu_mmu_index; 791 cc->dump_state = loongarch_cpu_dump_state; 792 cc->set_pc = loongarch_cpu_set_pc; 793 cc->get_pc = loongarch_cpu_get_pc; 794 #ifndef CONFIG_USER_ONLY 795 cc->get_arch_id = loongarch_cpu_get_arch_id; 796 dc->vmsd = &vmstate_loongarch_cpu; 797 cc->sysemu_ops = &loongarch_sysemu_ops; 798 #endif 799 cc->disas_set_info = loongarch_cpu_disas_set_info; 800 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 801 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 802 cc->gdb_stop_before_watchpoint = true; 803 804 #ifdef CONFIG_TCG 805 cc->tcg_ops = &loongarch_tcg_ops; 806 #endif 807 } 808 809 static const gchar *loongarch32_gdb_arch_name(CPUState *cs) 810 { 811 return "loongarch32"; 812 } 813 814 static void loongarch32_cpu_class_init(ObjectClass *c, void *data) 815 { 816 CPUClass *cc = CPU_CLASS(c); 817 818 cc->gdb_num_core_regs = 35; 819 cc->gdb_core_xml_file = "loongarch-base32.xml"; 820 cc->gdb_arch_name = loongarch32_gdb_arch_name; 821 } 822 823 static const gchar *loongarch64_gdb_arch_name(CPUState *cs) 824 { 825 return "loongarch64"; 826 } 827 828 static void loongarch64_cpu_class_init(ObjectClass *c, void *data) 829 { 830 CPUClass *cc = CPU_CLASS(c); 831 832 cc->gdb_num_core_regs = 35; 833 cc->gdb_core_xml_file = "loongarch-base64.xml"; 834 cc->gdb_arch_name = loongarch64_gdb_arch_name; 835 } 836 837 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ 838 { \ 839 .parent = TYPE_LOONGARCH##size##_CPU, \ 840 .instance_init = initfn, \ 841 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 842 } 843 844 static const TypeInfo loongarch_cpu_type_infos[] = { 845 { 846 .name = TYPE_LOONGARCH_CPU, 847 .parent = TYPE_CPU, 848 .instance_size = sizeof(LoongArchCPU), 849 .instance_align = __alignof(LoongArchCPU), 850 .instance_init = loongarch_cpu_init, 851 852 .abstract = true, 853 .class_size = sizeof(LoongArchCPUClass), 854 .class_init = loongarch_cpu_class_init, 855 }, 856 { 857 .name = TYPE_LOONGARCH32_CPU, 858 .parent = TYPE_LOONGARCH_CPU, 859 860 .abstract = true, 861 .class_init = loongarch32_cpu_class_init, 862 }, 863 { 864 .name = TYPE_LOONGARCH64_CPU, 865 .parent = TYPE_LOONGARCH_CPU, 866 867 .abstract = true, 868 .class_init = loongarch64_cpu_class_init, 869 }, 870 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), 871 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), 872 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), 873 }; 874 875 DEFINE_TYPES(loongarch_cpu_type_infos) 876