1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "sysemu/qtest.h" 14 #include "exec/exec-all.h" 15 #include "qapi/qapi-commands-machine-target.h" 16 #include "cpu.h" 17 #include "internals.h" 18 #include "fpu/softfloat-helpers.h" 19 #include "cpu-csr.h" 20 #include "sysemu/reset.h" 21 22 const char * const regnames[32] = { 23 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 24 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 25 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 26 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 27 }; 28 29 const char * const fregnames[32] = { 30 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 31 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 32 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 33 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 34 }; 35 36 static const char * const excp_names[] = { 37 [EXCCODE_INT] = "Interrupt", 38 [EXCCODE_PIL] = "Page invalid exception for load", 39 [EXCCODE_PIS] = "Page invalid exception for store", 40 [EXCCODE_PIF] = "Page invalid exception for fetch", 41 [EXCCODE_PME] = "Page modified exception", 42 [EXCCODE_PNR] = "Page Not Readable exception", 43 [EXCCODE_PNX] = "Page Not Executable exception", 44 [EXCCODE_PPI] = "Page Privilege error", 45 [EXCCODE_ADEF] = "Address error for instruction fetch", 46 [EXCCODE_ADEM] = "Address error for Memory access", 47 [EXCCODE_SYS] = "Syscall", 48 [EXCCODE_BRK] = "Break", 49 [EXCCODE_INE] = "Instruction Non-Existent", 50 [EXCCODE_IPE] = "Instruction privilege error", 51 [EXCCODE_FPE] = "Floating Point Exception", 52 [EXCCODE_DBP] = "Debug breakpoint", 53 [EXCCODE_BCE] = "Bound Check Exception", 54 }; 55 56 const char *loongarch_exception_name(int32_t exception) 57 { 58 assert(excp_names[exception]); 59 return excp_names[exception]; 60 } 61 62 void G_NORETURN do_raise_exception(CPULoongArchState *env, 63 uint32_t exception, 64 uintptr_t pc) 65 { 66 CPUState *cs = env_cpu(env); 67 68 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", 69 __func__, 70 exception, 71 loongarch_exception_name(exception)); 72 cs->exception_index = exception; 73 74 cpu_loop_exit_restore(cs, pc); 75 } 76 77 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 78 { 79 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 80 CPULoongArchState *env = &cpu->env; 81 82 env->pc = value; 83 } 84 85 static vaddr loongarch_cpu_get_pc(CPUState *cs) 86 { 87 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 88 CPULoongArchState *env = &cpu->env; 89 90 return env->pc; 91 } 92 93 #ifndef CONFIG_USER_ONLY 94 #include "hw/loongarch/virt.h" 95 96 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 97 { 98 LoongArchCPU *cpu = opaque; 99 CPULoongArchState *env = &cpu->env; 100 CPUState *cs = CPU(cpu); 101 102 if (irq < 0 || irq >= N_IRQS) { 103 return; 104 } 105 106 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 107 108 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 109 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 110 } else { 111 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 112 } 113 } 114 115 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 116 { 117 bool ret = 0; 118 119 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 120 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 121 122 return ret; 123 } 124 125 /* Check if there is pending and not masked out interrupt */ 126 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 127 { 128 uint32_t pending; 129 uint32_t status; 130 bool r; 131 132 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 133 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 134 135 r = (pending & status) != 0; 136 return r; 137 } 138 139 static void loongarch_cpu_do_interrupt(CPUState *cs) 140 { 141 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 142 CPULoongArchState *env = &cpu->env; 143 bool update_badinstr = 1; 144 int cause = -1; 145 const char *name; 146 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 147 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 148 149 if (cs->exception_index != EXCCODE_INT) { 150 if (cs->exception_index < 0 || 151 cs->exception_index >= ARRAY_SIZE(excp_names)) { 152 name = "unknown"; 153 } else { 154 name = excp_names[cs->exception_index]; 155 } 156 157 qemu_log_mask(CPU_LOG_INT, 158 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 159 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, 160 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); 161 } 162 163 switch (cs->exception_index) { 164 case EXCCODE_DBP: 165 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 166 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 167 goto set_DERA; 168 set_DERA: 169 env->CSR_DERA = env->pc; 170 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 171 env->pc = env->CSR_EENTRY + 0x480; 172 break; 173 case EXCCODE_INT: 174 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 175 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 176 goto set_DERA; 177 } 178 QEMU_FALLTHROUGH; 179 case EXCCODE_PIF: 180 cause = cs->exception_index; 181 update_badinstr = 0; 182 break; 183 case EXCCODE_SYS: 184 case EXCCODE_BRK: 185 case EXCCODE_INE: 186 case EXCCODE_IPE: 187 case EXCCODE_FPE: 188 case EXCCODE_BCE: 189 env->CSR_BADV = env->pc; 190 QEMU_FALLTHROUGH; 191 case EXCCODE_ADEM: 192 case EXCCODE_PIL: 193 case EXCCODE_PIS: 194 case EXCCODE_PME: 195 case EXCCODE_PNR: 196 case EXCCODE_PNX: 197 case EXCCODE_PPI: 198 cause = cs->exception_index; 199 break; 200 default: 201 qemu_log("Error: exception(%d) has not been supported\n", 202 cs->exception_index); 203 abort(); 204 } 205 206 if (update_badinstr) { 207 env->CSR_BADI = cpu_ldl_code(env, env->pc); 208 } 209 210 /* Save PLV and IE */ 211 if (tlbfill) { 212 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 213 FIELD_EX64(env->CSR_CRMD, 214 CSR_CRMD, PLV)); 215 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 216 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 217 /* set the DA mode */ 218 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 219 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 220 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 221 PC, (env->pc >> 2)); 222 } else { 223 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause); 224 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 225 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 226 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 227 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 228 env->CSR_ERA = env->pc; 229 } 230 231 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 232 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 233 234 if (vec_size) { 235 vec_size = (1 << vec_size) * 4; 236 } 237 238 if (cs->exception_index == EXCCODE_INT) { 239 /* Interrupt */ 240 uint32_t vector = 0; 241 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 242 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 243 244 /* Find the highest-priority interrupt. */ 245 vector = 31 - clz32(pending); 246 env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size; 247 qemu_log_mask(CPU_LOG_INT, 248 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 249 " cause %d\n" " A " TARGET_FMT_lx " D " 250 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 251 TARGET_FMT_lx "\n", 252 __func__, env->pc, env->CSR_ERA, 253 cause, env->CSR_BADV, env->CSR_DERA, vector, 254 env->CSR_ECFG, env->CSR_ESTAT); 255 } else { 256 if (tlbfill) { 257 env->pc = env->CSR_TLBRENTRY; 258 } else { 259 env->pc = env->CSR_EENTRY; 260 env->pc += cause * vec_size; 261 } 262 qemu_log_mask(CPU_LOG_INT, 263 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 264 " cause %d%s\n, ESTAT " TARGET_FMT_lx 265 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 266 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 267 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 268 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 269 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 270 env->CSR_ECFG, 271 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 272 env->CSR_BADI, env->gpr[11], cs->cpu_index, 273 env->CSR_ASID); 274 } 275 cs->exception_index = -1; 276 } 277 278 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 279 vaddr addr, unsigned size, 280 MMUAccessType access_type, 281 int mmu_idx, MemTxAttrs attrs, 282 MemTxResult response, 283 uintptr_t retaddr) 284 { 285 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 286 CPULoongArchState *env = &cpu->env; 287 288 if (access_type == MMU_INST_FETCH) { 289 do_raise_exception(env, EXCCODE_ADEF, retaddr); 290 } else { 291 do_raise_exception(env, EXCCODE_ADEM, retaddr); 292 } 293 } 294 295 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 296 { 297 if (interrupt_request & CPU_INTERRUPT_HARD) { 298 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 299 CPULoongArchState *env = &cpu->env; 300 301 if (cpu_loongarch_hw_interrupts_enabled(env) && 302 cpu_loongarch_hw_interrupts_pending(env)) { 303 /* Raise it */ 304 cs->exception_index = EXCCODE_INT; 305 loongarch_cpu_do_interrupt(cs); 306 return true; 307 } 308 } 309 return false; 310 } 311 #endif 312 313 #ifdef CONFIG_TCG 314 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 315 const TranslationBlock *tb) 316 { 317 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 318 CPULoongArchState *env = &cpu->env; 319 320 env->pc = tb_pc(tb); 321 } 322 #endif /* CONFIG_TCG */ 323 324 static bool loongarch_cpu_has_work(CPUState *cs) 325 { 326 #ifdef CONFIG_USER_ONLY 327 return true; 328 #else 329 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 330 CPULoongArchState *env = &cpu->env; 331 bool has_work = false; 332 333 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 334 cpu_loongarch_hw_interrupts_pending(env)) { 335 has_work = true; 336 } 337 338 return has_work; 339 #endif 340 } 341 342 static void loongarch_la464_initfn(Object *obj) 343 { 344 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 345 CPULoongArchState *env = &cpu->env; 346 int i; 347 348 for (i = 0; i < 21; i++) { 349 env->cpucfg[i] = 0x0; 350 } 351 352 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 353 env->cpucfg[0] = 0x14c010; /* PRID */ 354 355 uint32_t data = 0; 356 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 357 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 358 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 359 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); 360 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 361 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 362 data = FIELD_DP32(data, CPUCFG1, RI, 1); 363 data = FIELD_DP32(data, CPUCFG1, EP, 1); 364 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 365 data = FIELD_DP32(data, CPUCFG1, HP, 1); 366 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 367 env->cpucfg[1] = data; 368 369 data = 0; 370 data = FIELD_DP32(data, CPUCFG2, FP, 1); 371 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 372 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 373 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 374 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 375 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 376 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 377 env->cpucfg[2] = data; 378 379 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 380 381 data = 0; 382 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 383 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 384 env->cpucfg[5] = data; 385 386 data = 0; 387 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 388 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 389 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 390 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 391 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 392 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 393 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 394 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 395 env->cpucfg[16] = data; 396 397 data = 0; 398 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 399 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 400 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 401 env->cpucfg[17] = data; 402 403 data = 0; 404 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 405 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 406 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 407 env->cpucfg[18] = data; 408 409 data = 0; 410 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 411 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 412 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 413 env->cpucfg[19] = data; 414 415 data = 0; 416 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 417 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 418 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 419 env->cpucfg[20] = data; 420 421 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 422 } 423 424 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) 425 { 426 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 427 428 qemu_printf("%s\n", typename); 429 } 430 431 void loongarch_cpu_list(void) 432 { 433 GSList *list; 434 list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false); 435 g_slist_foreach(list, loongarch_cpu_list_entry, NULL); 436 g_slist_free(list); 437 } 438 439 static void loongarch_cpu_reset(DeviceState *dev) 440 { 441 CPUState *cs = CPU(dev); 442 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 443 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); 444 CPULoongArchState *env = &cpu->env; 445 446 lacc->parent_reset(dev); 447 448 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 449 env->fcsr0 = 0x0; 450 451 int n; 452 /* Set csr registers value after reset */ 453 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 454 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 455 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 456 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 457 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); 458 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); 459 460 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 461 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 462 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 463 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 464 465 env->CSR_MISC = 0; 466 467 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 468 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 469 470 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 471 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 472 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 473 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 474 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 475 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 476 477 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 478 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 479 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 480 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 481 482 for (n = 0; n < 4; n++) { 483 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 484 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 485 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 486 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 487 } 488 489 #ifndef CONFIG_USER_ONLY 490 env->pc = 0x1c000000; 491 memset(env->tlb, 0, sizeof(env->tlb)); 492 #endif 493 494 restore_fp_status(env); 495 cs->exception_index = -1; 496 } 497 498 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 499 { 500 info->print_insn = print_insn_loongarch; 501 } 502 503 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 504 { 505 CPUState *cs = CPU(dev); 506 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 507 Error *local_err = NULL; 508 509 cpu_exec_realizefn(cs, &local_err); 510 if (local_err != NULL) { 511 error_propagate(errp, local_err); 512 return; 513 } 514 515 loongarch_cpu_register_gdb_regs_for_features(cs); 516 517 cpu_reset(cs); 518 qemu_init_vcpu(cs); 519 520 lacc->parent_realize(dev, errp); 521 } 522 523 #ifndef CONFIG_USER_ONLY 524 static void loongarch_qemu_write(void *opaque, hwaddr addr, 525 uint64_t val, unsigned size) 526 { 527 } 528 529 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 530 { 531 switch (addr) { 532 case FEATURE_REG: 533 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 534 1ULL << IOCSRF_CSRIPI; 535 case VENDOR_REG: 536 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 537 case CPUNAME_REG: 538 return 0x303030354133ULL; /* "3A5000" */ 539 case MISC_FUNC_REG: 540 return 1ULL << IOCSRM_EXTIOI_EN; 541 } 542 return 0ULL; 543 } 544 545 static const MemoryRegionOps loongarch_qemu_ops = { 546 .read = loongarch_qemu_read, 547 .write = loongarch_qemu_write, 548 .endianness = DEVICE_LITTLE_ENDIAN, 549 .valid = { 550 .min_access_size = 4, 551 .max_access_size = 8, 552 }, 553 .impl = { 554 .min_access_size = 8, 555 .max_access_size = 8, 556 }, 557 }; 558 #endif 559 560 static void loongarch_cpu_init(Object *obj) 561 { 562 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 563 564 cpu_set_cpustate_pointers(cpu); 565 566 #ifndef CONFIG_USER_ONLY 567 CPULoongArchState *env = &cpu->env; 568 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 569 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 570 &loongarch_constant_timer_cb, cpu); 571 memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, 572 env, "iocsr", UINT64_MAX); 573 address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); 574 memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, 575 NULL, "iocsr_misc", 0x428); 576 memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); 577 #endif 578 } 579 580 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 581 { 582 ObjectClass *oc; 583 584 oc = object_class_by_name(cpu_model); 585 if (!oc) { 586 g_autofree char *typename 587 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 588 oc = object_class_by_name(typename); 589 if (!oc) { 590 return NULL; 591 } 592 } 593 594 if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) 595 && !object_class_is_abstract(oc)) { 596 return oc; 597 } 598 return NULL; 599 } 600 601 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 602 { 603 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 604 CPULoongArchState *env = &cpu->env; 605 int i; 606 607 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 608 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, 609 get_float_exception_flags(&env->fp_status)); 610 611 /* gpr */ 612 for (i = 0; i < 32; i++) { 613 if ((i & 3) == 0) { 614 qemu_fprintf(f, " GPR%02d:", i); 615 } 616 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 617 if ((i & 3) == 3) { 618 qemu_fprintf(f, "\n"); 619 } 620 } 621 622 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); 623 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); 624 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); 625 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); 626 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); 627 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); 628 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); 629 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); 630 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," 631 " PRCFG3=%016" PRIx64 "\n", 632 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); 633 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); 634 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); 635 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); 636 637 /* fpr */ 638 if (flags & CPU_DUMP_FPU) { 639 for (i = 0; i < 32; i++) { 640 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]); 641 if ((i & 3) == 3) { 642 qemu_fprintf(f, "\n"); 643 } 644 } 645 } 646 } 647 648 #ifdef CONFIG_TCG 649 #include "hw/core/tcg-cpu-ops.h" 650 651 static struct TCGCPUOps loongarch_tcg_ops = { 652 .initialize = loongarch_translate_init, 653 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 654 655 #ifndef CONFIG_USER_ONLY 656 .tlb_fill = loongarch_cpu_tlb_fill, 657 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 658 .do_interrupt = loongarch_cpu_do_interrupt, 659 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 660 #endif 661 }; 662 #endif /* CONFIG_TCG */ 663 664 #ifndef CONFIG_USER_ONLY 665 #include "hw/core/sysemu-cpu-ops.h" 666 667 static const struct SysemuCPUOps loongarch_sysemu_ops = { 668 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 669 }; 670 #endif 671 672 static gchar *loongarch_gdb_arch_name(CPUState *cs) 673 { 674 return g_strdup("loongarch64"); 675 } 676 677 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 678 { 679 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 680 CPUClass *cc = CPU_CLASS(c); 681 DeviceClass *dc = DEVICE_CLASS(c); 682 683 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 684 &lacc->parent_realize); 685 device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset); 686 687 cc->class_by_name = loongarch_cpu_class_by_name; 688 cc->has_work = loongarch_cpu_has_work; 689 cc->dump_state = loongarch_cpu_dump_state; 690 cc->set_pc = loongarch_cpu_set_pc; 691 cc->get_pc = loongarch_cpu_get_pc; 692 #ifndef CONFIG_USER_ONLY 693 dc->vmsd = &vmstate_loongarch_cpu; 694 cc->sysemu_ops = &loongarch_sysemu_ops; 695 #endif 696 cc->disas_set_info = loongarch_cpu_disas_set_info; 697 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 698 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 699 cc->disas_set_info = loongarch_cpu_disas_set_info; 700 cc->gdb_num_core_regs = 35; 701 cc->gdb_core_xml_file = "loongarch-base64.xml"; 702 cc->gdb_stop_before_watchpoint = true; 703 cc->gdb_arch_name = loongarch_gdb_arch_name; 704 705 #ifdef CONFIG_TCG 706 cc->tcg_ops = &loongarch_tcg_ops; 707 #endif 708 } 709 710 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ 711 { \ 712 .parent = TYPE_LOONGARCH_CPU, \ 713 .instance_init = initfn, \ 714 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 715 } 716 717 static const TypeInfo loongarch_cpu_type_infos[] = { 718 { 719 .name = TYPE_LOONGARCH_CPU, 720 .parent = TYPE_CPU, 721 .instance_size = sizeof(LoongArchCPU), 722 .instance_init = loongarch_cpu_init, 723 724 .abstract = true, 725 .class_size = sizeof(LoongArchCPUClass), 726 .class_init = loongarch_cpu_class_init, 727 }, 728 DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn), 729 }; 730 731 DEFINE_TYPES(loongarch_cpu_type_infos) 732 733 static void loongarch_cpu_add_definition(gpointer data, gpointer user_data) 734 { 735 ObjectClass *oc = data; 736 CpuDefinitionInfoList **cpu_list = user_data; 737 CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1); 738 const char *typename = object_class_get_name(oc); 739 740 info->name = g_strndup(typename, 741 strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU)); 742 info->q_typename = g_strdup(typename); 743 744 QAPI_LIST_PREPEND(*cpu_list, info); 745 } 746 747 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 748 { 749 CpuDefinitionInfoList *cpu_list = NULL; 750 GSList *list; 751 752 list = object_class_get_list(TYPE_LOONGARCH_CPU, false); 753 g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list); 754 g_slist_free(list); 755 756 return cpu_list; 757 } 758