1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "sysemu/qtest.h" 14 #include "exec/cpu_ldst.h" 15 #include "exec/exec-all.h" 16 #include "cpu.h" 17 #include "internals.h" 18 #include "fpu/softfloat-helpers.h" 19 #include "cpu-csr.h" 20 #include "sysemu/reset.h" 21 #include "tcg/tcg.h" 22 23 const char * const regnames[32] = { 24 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 25 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 26 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 27 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 28 }; 29 30 const char * const fregnames[32] = { 31 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 32 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 33 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 34 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 35 }; 36 37 static const char * const excp_names[] = { 38 [EXCCODE_INT] = "Interrupt", 39 [EXCCODE_PIL] = "Page invalid exception for load", 40 [EXCCODE_PIS] = "Page invalid exception for store", 41 [EXCCODE_PIF] = "Page invalid exception for fetch", 42 [EXCCODE_PME] = "Page modified exception", 43 [EXCCODE_PNR] = "Page Not Readable exception", 44 [EXCCODE_PNX] = "Page Not Executable exception", 45 [EXCCODE_PPI] = "Page Privilege error", 46 [EXCCODE_ADEF] = "Address error for instruction fetch", 47 [EXCCODE_ADEM] = "Address error for Memory access", 48 [EXCCODE_SYS] = "Syscall", 49 [EXCCODE_BRK] = "Break", 50 [EXCCODE_INE] = "Instruction Non-Existent", 51 [EXCCODE_IPE] = "Instruction privilege error", 52 [EXCCODE_FPD] = "Floating Point Disabled", 53 [EXCCODE_FPE] = "Floating Point Exception", 54 [EXCCODE_DBP] = "Debug breakpoint", 55 [EXCCODE_BCE] = "Bound Check Exception", 56 [EXCCODE_SXD] = "128 bit vector instructions Disable exception", 57 }; 58 59 const char *loongarch_exception_name(int32_t exception) 60 { 61 assert(excp_names[exception]); 62 return excp_names[exception]; 63 } 64 65 void G_NORETURN do_raise_exception(CPULoongArchState *env, 66 uint32_t exception, 67 uintptr_t pc) 68 { 69 CPUState *cs = env_cpu(env); 70 71 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", 72 __func__, 73 exception, 74 loongarch_exception_name(exception)); 75 cs->exception_index = exception; 76 77 cpu_loop_exit_restore(cs, pc); 78 } 79 80 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 81 { 82 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 83 CPULoongArchState *env = &cpu->env; 84 85 set_pc(env, value); 86 } 87 88 static vaddr loongarch_cpu_get_pc(CPUState *cs) 89 { 90 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 91 CPULoongArchState *env = &cpu->env; 92 93 return env->pc; 94 } 95 96 #ifndef CONFIG_USER_ONLY 97 #include "hw/loongarch/virt.h" 98 99 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 100 { 101 LoongArchCPU *cpu = opaque; 102 CPULoongArchState *env = &cpu->env; 103 CPUState *cs = CPU(cpu); 104 105 if (irq < 0 || irq >= N_IRQS) { 106 return; 107 } 108 109 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 110 111 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 112 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 113 } else { 114 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 115 } 116 } 117 118 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 119 { 120 bool ret = 0; 121 122 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 123 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 124 125 return ret; 126 } 127 128 /* Check if there is pending and not masked out interrupt */ 129 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 130 { 131 uint32_t pending; 132 uint32_t status; 133 134 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 135 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 136 137 return (pending & status) != 0; 138 } 139 140 static void loongarch_cpu_do_interrupt(CPUState *cs) 141 { 142 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 143 CPULoongArchState *env = &cpu->env; 144 bool update_badinstr = 1; 145 int cause = -1; 146 const char *name; 147 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 148 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 149 150 if (cs->exception_index != EXCCODE_INT) { 151 if (cs->exception_index < 0 || 152 cs->exception_index >= ARRAY_SIZE(excp_names)) { 153 name = "unknown"; 154 } else { 155 name = excp_names[cs->exception_index]; 156 } 157 158 qemu_log_mask(CPU_LOG_INT, 159 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 160 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, 161 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); 162 } 163 164 switch (cs->exception_index) { 165 case EXCCODE_DBP: 166 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 167 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 168 goto set_DERA; 169 set_DERA: 170 env->CSR_DERA = env->pc; 171 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 172 set_pc(env, env->CSR_EENTRY + 0x480); 173 break; 174 case EXCCODE_INT: 175 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 176 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 177 goto set_DERA; 178 } 179 QEMU_FALLTHROUGH; 180 case EXCCODE_PIF: 181 case EXCCODE_ADEF: 182 cause = cs->exception_index; 183 update_badinstr = 0; 184 break; 185 case EXCCODE_SYS: 186 case EXCCODE_BRK: 187 case EXCCODE_INE: 188 case EXCCODE_IPE: 189 case EXCCODE_FPD: 190 case EXCCODE_FPE: 191 case EXCCODE_SXD: 192 env->CSR_BADV = env->pc; 193 QEMU_FALLTHROUGH; 194 case EXCCODE_BCE: 195 case EXCCODE_ADEM: 196 case EXCCODE_PIL: 197 case EXCCODE_PIS: 198 case EXCCODE_PME: 199 case EXCCODE_PNR: 200 case EXCCODE_PNX: 201 case EXCCODE_PPI: 202 cause = cs->exception_index; 203 break; 204 default: 205 qemu_log("Error: exception(%d) has not been supported\n", 206 cs->exception_index); 207 abort(); 208 } 209 210 if (update_badinstr) { 211 env->CSR_BADI = cpu_ldl_code(env, env->pc); 212 } 213 214 /* Save PLV and IE */ 215 if (tlbfill) { 216 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 217 FIELD_EX64(env->CSR_CRMD, 218 CSR_CRMD, PLV)); 219 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 220 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 221 /* set the DA mode */ 222 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 223 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 224 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 225 PC, (env->pc >> 2)); 226 } else { 227 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 228 EXCODE_MCODE(cause)); 229 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 230 EXCODE_SUBCODE(cause)); 231 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 232 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 233 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 234 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 235 env->CSR_ERA = env->pc; 236 } 237 238 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 239 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 240 241 if (vec_size) { 242 vec_size = (1 << vec_size) * 4; 243 } 244 245 if (cs->exception_index == EXCCODE_INT) { 246 /* Interrupt */ 247 uint32_t vector = 0; 248 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 249 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 250 251 /* Find the highest-priority interrupt. */ 252 vector = 31 - clz32(pending); 253 set_pc(env, env->CSR_EENTRY + \ 254 (EXCCODE_EXTERNAL_INT + vector) * vec_size); 255 qemu_log_mask(CPU_LOG_INT, 256 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 257 " cause %d\n" " A " TARGET_FMT_lx " D " 258 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 259 TARGET_FMT_lx "\n", 260 __func__, env->pc, env->CSR_ERA, 261 cause, env->CSR_BADV, env->CSR_DERA, vector, 262 env->CSR_ECFG, env->CSR_ESTAT); 263 } else { 264 if (tlbfill) { 265 set_pc(env, env->CSR_TLBRENTRY); 266 } else { 267 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); 268 } 269 qemu_log_mask(CPU_LOG_INT, 270 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 271 " cause %d%s\n, ESTAT " TARGET_FMT_lx 272 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 273 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 274 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 275 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 276 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 277 env->CSR_ECFG, 278 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 279 env->CSR_BADI, env->gpr[11], cs->cpu_index, 280 env->CSR_ASID); 281 } 282 cs->exception_index = -1; 283 } 284 285 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 286 vaddr addr, unsigned size, 287 MMUAccessType access_type, 288 int mmu_idx, MemTxAttrs attrs, 289 MemTxResult response, 290 uintptr_t retaddr) 291 { 292 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 293 CPULoongArchState *env = &cpu->env; 294 295 if (access_type == MMU_INST_FETCH) { 296 do_raise_exception(env, EXCCODE_ADEF, retaddr); 297 } else { 298 do_raise_exception(env, EXCCODE_ADEM, retaddr); 299 } 300 } 301 302 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 303 { 304 if (interrupt_request & CPU_INTERRUPT_HARD) { 305 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 306 CPULoongArchState *env = &cpu->env; 307 308 if (cpu_loongarch_hw_interrupts_enabled(env) && 309 cpu_loongarch_hw_interrupts_pending(env)) { 310 /* Raise it */ 311 cs->exception_index = EXCCODE_INT; 312 loongarch_cpu_do_interrupt(cs); 313 return true; 314 } 315 } 316 return false; 317 } 318 #endif 319 320 #ifdef CONFIG_TCG 321 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 322 const TranslationBlock *tb) 323 { 324 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 325 CPULoongArchState *env = &cpu->env; 326 327 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 328 set_pc(env, tb->pc); 329 } 330 331 static void loongarch_restore_state_to_opc(CPUState *cs, 332 const TranslationBlock *tb, 333 const uint64_t *data) 334 { 335 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 336 CPULoongArchState *env = &cpu->env; 337 338 set_pc(env, data[0]); 339 } 340 #endif /* CONFIG_TCG */ 341 342 static bool loongarch_cpu_has_work(CPUState *cs) 343 { 344 #ifdef CONFIG_USER_ONLY 345 return true; 346 #else 347 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 348 CPULoongArchState *env = &cpu->env; 349 bool has_work = false; 350 351 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 352 cpu_loongarch_hw_interrupts_pending(env)) { 353 has_work = true; 354 } 355 356 return has_work; 357 #endif 358 } 359 360 static void loongarch_la464_initfn(Object *obj) 361 { 362 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 363 CPULoongArchState *env = &cpu->env; 364 int i; 365 366 for (i = 0; i < 21; i++) { 367 env->cpucfg[i] = 0x0; 368 } 369 370 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 371 env->cpucfg[0] = 0x14c010; /* PRID */ 372 373 uint32_t data = 0; 374 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 375 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 376 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 377 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); 378 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 379 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 380 data = FIELD_DP32(data, CPUCFG1, RI, 1); 381 data = FIELD_DP32(data, CPUCFG1, EP, 1); 382 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 383 data = FIELD_DP32(data, CPUCFG1, HP, 1); 384 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 385 env->cpucfg[1] = data; 386 387 data = 0; 388 data = FIELD_DP32(data, CPUCFG2, FP, 1); 389 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 390 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 391 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 392 data = FIELD_DP32(data, CPUCFG2, LSX, 1), 393 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 394 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 395 data = FIELD_DP32(data, CPUCFG2, LSPW, 1); 396 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 397 env->cpucfg[2] = data; 398 399 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 400 401 data = 0; 402 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 403 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 404 env->cpucfg[5] = data; 405 406 data = 0; 407 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 408 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 409 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 410 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 411 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 412 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 413 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 414 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 415 env->cpucfg[16] = data; 416 417 data = 0; 418 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 419 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 420 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 421 env->cpucfg[17] = data; 422 423 data = 0; 424 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 425 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 426 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 427 env->cpucfg[18] = data; 428 429 data = 0; 430 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 431 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 432 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 433 env->cpucfg[19] = data; 434 435 data = 0; 436 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 437 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 438 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 439 env->cpucfg[20] = data; 440 441 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 442 } 443 444 static void loongarch_la132_initfn(Object *obj) 445 { 446 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 447 CPULoongArchState *env = &cpu->env; 448 449 int i; 450 451 for (i = 0; i < 21; i++) { 452 env->cpucfg[i] = 0x0; 453 } 454 455 cpu->dtb_compatible = "loongarch,Loongson-1C103"; 456 env->cpucfg[0] = 0x148042; /* PRID */ 457 458 uint32_t data = 0; 459 data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ 460 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 461 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 462 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ 463 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ 464 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 465 data = FIELD_DP32(data, CPUCFG1, RI, 0); 466 data = FIELD_DP32(data, CPUCFG1, EP, 0); 467 data = FIELD_DP32(data, CPUCFG1, RPLV, 0); 468 data = FIELD_DP32(data, CPUCFG1, HP, 1); 469 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 470 env->cpucfg[1] = data; 471 } 472 473 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) 474 { 475 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 476 477 qemu_printf("%s\n", typename); 478 } 479 480 void loongarch_cpu_list(void) 481 { 482 GSList *list; 483 list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false); 484 g_slist_foreach(list, loongarch_cpu_list_entry, NULL); 485 g_slist_free(list); 486 } 487 488 static void loongarch_cpu_reset_hold(Object *obj) 489 { 490 CPUState *cs = CPU(obj); 491 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 492 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); 493 CPULoongArchState *env = &cpu->env; 494 495 if (lacc->parent_phases.hold) { 496 lacc->parent_phases.hold(obj); 497 } 498 499 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 500 env->fcsr0 = 0x0; 501 502 int n; 503 /* Set csr registers value after reset */ 504 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 505 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 506 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 507 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 508 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); 509 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); 510 511 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 512 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 513 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 514 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 515 516 env->CSR_MISC = 0; 517 518 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 519 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 520 521 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 522 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 523 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 524 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 525 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 526 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 527 528 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 529 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 530 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 531 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 532 533 for (n = 0; n < 4; n++) { 534 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 535 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 536 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 537 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 538 } 539 540 #ifndef CONFIG_USER_ONLY 541 env->pc = 0x1c000000; 542 memset(env->tlb, 0, sizeof(env->tlb)); 543 #endif 544 545 restore_fp_status(env); 546 cs->exception_index = -1; 547 } 548 549 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 550 { 551 info->print_insn = print_insn_loongarch; 552 } 553 554 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 555 { 556 CPUState *cs = CPU(dev); 557 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 558 Error *local_err = NULL; 559 560 cpu_exec_realizefn(cs, &local_err); 561 if (local_err != NULL) { 562 error_propagate(errp, local_err); 563 return; 564 } 565 566 loongarch_cpu_register_gdb_regs_for_features(cs); 567 568 cpu_reset(cs); 569 qemu_init_vcpu(cs); 570 571 lacc->parent_realize(dev, errp); 572 } 573 574 #ifndef CONFIG_USER_ONLY 575 static void loongarch_qemu_write(void *opaque, hwaddr addr, 576 uint64_t val, unsigned size) 577 { 578 qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n", 579 __func__, addr); 580 } 581 582 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 583 { 584 switch (addr) { 585 case VERSION_REG: 586 return 0x11ULL; 587 case FEATURE_REG: 588 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 589 1ULL << IOCSRF_CSRIPI; 590 case VENDOR_REG: 591 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 592 case CPUNAME_REG: 593 return 0x303030354133ULL; /* "3A5000" */ 594 case MISC_FUNC_REG: 595 return 1ULL << IOCSRM_EXTIOI_EN; 596 } 597 return 0ULL; 598 } 599 600 static const MemoryRegionOps loongarch_qemu_ops = { 601 .read = loongarch_qemu_read, 602 .write = loongarch_qemu_write, 603 .endianness = DEVICE_LITTLE_ENDIAN, 604 .valid = { 605 .min_access_size = 4, 606 .max_access_size = 8, 607 }, 608 .impl = { 609 .min_access_size = 8, 610 .max_access_size = 8, 611 }, 612 }; 613 #endif 614 615 static void loongarch_cpu_init(Object *obj) 616 { 617 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 618 619 cpu_set_cpustate_pointers(cpu); 620 621 #ifndef CONFIG_USER_ONLY 622 CPULoongArchState *env = &cpu->env; 623 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 624 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 625 &loongarch_constant_timer_cb, cpu); 626 memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, 627 env, "iocsr", UINT64_MAX); 628 address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); 629 memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, 630 NULL, "iocsr_misc", 0x428); 631 memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); 632 #endif 633 } 634 635 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 636 { 637 ObjectClass *oc; 638 639 oc = object_class_by_name(cpu_model); 640 if (!oc) { 641 g_autofree char *typename 642 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 643 oc = object_class_by_name(typename); 644 if (!oc) { 645 return NULL; 646 } 647 } 648 649 if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) 650 && !object_class_is_abstract(oc)) { 651 return oc; 652 } 653 return NULL; 654 } 655 656 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 657 { 658 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 659 CPULoongArchState *env = &cpu->env; 660 int i; 661 662 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 663 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, 664 get_float_exception_flags(&env->fp_status)); 665 666 /* gpr */ 667 for (i = 0; i < 32; i++) { 668 if ((i & 3) == 0) { 669 qemu_fprintf(f, " GPR%02d:", i); 670 } 671 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 672 if ((i & 3) == 3) { 673 qemu_fprintf(f, "\n"); 674 } 675 } 676 677 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); 678 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); 679 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); 680 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); 681 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); 682 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); 683 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); 684 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); 685 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," 686 " PRCFG3=%016" PRIx64 "\n", 687 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); 688 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); 689 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); 690 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); 691 692 /* fpr */ 693 if (flags & CPU_DUMP_FPU) { 694 for (i = 0; i < 32; i++) { 695 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); 696 if ((i & 3) == 3) { 697 qemu_fprintf(f, "\n"); 698 } 699 } 700 } 701 } 702 703 #ifdef CONFIG_TCG 704 #include "hw/core/tcg-cpu-ops.h" 705 706 static struct TCGCPUOps loongarch_tcg_ops = { 707 .initialize = loongarch_translate_init, 708 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 709 .restore_state_to_opc = loongarch_restore_state_to_opc, 710 711 #ifndef CONFIG_USER_ONLY 712 .tlb_fill = loongarch_cpu_tlb_fill, 713 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 714 .do_interrupt = loongarch_cpu_do_interrupt, 715 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 716 #endif 717 }; 718 #endif /* CONFIG_TCG */ 719 720 #ifndef CONFIG_USER_ONLY 721 #include "hw/core/sysemu-cpu-ops.h" 722 723 static const struct SysemuCPUOps loongarch_sysemu_ops = { 724 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 725 }; 726 727 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) 728 { 729 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 730 731 return cpu->phy_id; 732 } 733 #endif 734 735 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 736 { 737 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 738 CPUClass *cc = CPU_CLASS(c); 739 DeviceClass *dc = DEVICE_CLASS(c); 740 ResettableClass *rc = RESETTABLE_CLASS(c); 741 742 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 743 &lacc->parent_realize); 744 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, 745 &lacc->parent_phases); 746 747 cc->class_by_name = loongarch_cpu_class_by_name; 748 cc->has_work = loongarch_cpu_has_work; 749 cc->dump_state = loongarch_cpu_dump_state; 750 cc->set_pc = loongarch_cpu_set_pc; 751 cc->get_pc = loongarch_cpu_get_pc; 752 #ifndef CONFIG_USER_ONLY 753 cc->get_arch_id = loongarch_cpu_get_arch_id; 754 dc->vmsd = &vmstate_loongarch_cpu; 755 cc->sysemu_ops = &loongarch_sysemu_ops; 756 #endif 757 cc->disas_set_info = loongarch_cpu_disas_set_info; 758 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 759 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 760 cc->gdb_stop_before_watchpoint = true; 761 762 #ifdef CONFIG_TCG 763 cc->tcg_ops = &loongarch_tcg_ops; 764 #endif 765 } 766 767 static gchar *loongarch32_gdb_arch_name(CPUState *cs) 768 { 769 return g_strdup("loongarch32"); 770 } 771 772 static void loongarch32_cpu_class_init(ObjectClass *c, void *data) 773 { 774 CPUClass *cc = CPU_CLASS(c); 775 776 cc->gdb_num_core_regs = 35; 777 cc->gdb_core_xml_file = "loongarch-base32.xml"; 778 cc->gdb_arch_name = loongarch32_gdb_arch_name; 779 } 780 781 static gchar *loongarch64_gdb_arch_name(CPUState *cs) 782 { 783 return g_strdup("loongarch64"); 784 } 785 786 static void loongarch64_cpu_class_init(ObjectClass *c, void *data) 787 { 788 CPUClass *cc = CPU_CLASS(c); 789 790 cc->gdb_num_core_regs = 35; 791 cc->gdb_core_xml_file = "loongarch-base64.xml"; 792 cc->gdb_arch_name = loongarch64_gdb_arch_name; 793 } 794 795 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ 796 { \ 797 .parent = TYPE_LOONGARCH##size##_CPU, \ 798 .instance_init = initfn, \ 799 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 800 } 801 802 static const TypeInfo loongarch_cpu_type_infos[] = { 803 { 804 .name = TYPE_LOONGARCH_CPU, 805 .parent = TYPE_CPU, 806 .instance_size = sizeof(LoongArchCPU), 807 .instance_init = loongarch_cpu_init, 808 809 .abstract = true, 810 .class_size = sizeof(LoongArchCPUClass), 811 .class_init = loongarch_cpu_class_init, 812 }, 813 { 814 .name = TYPE_LOONGARCH32_CPU, 815 .parent = TYPE_LOONGARCH_CPU, 816 817 .abstract = true, 818 .class_init = loongarch32_cpu_class_init, 819 }, 820 { 821 .name = TYPE_LOONGARCH64_CPU, 822 .parent = TYPE_LOONGARCH_CPU, 823 824 .abstract = true, 825 .class_init = loongarch64_cpu_class_init, 826 }, 827 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), 828 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), 829 }; 830 831 DEFINE_TYPES(loongarch_cpu_type_infos) 832