1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "sysemu/qtest.h" 14 #include "exec/exec-all.h" 15 #include "qapi/qapi-commands-machine-target.h" 16 #include "cpu.h" 17 #include "internals.h" 18 #include "fpu/softfloat-helpers.h" 19 #include "cpu-csr.h" 20 #include "sysemu/reset.h" 21 #include "tcg/tcg.h" 22 23 const char * const regnames[32] = { 24 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 25 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 26 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 27 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 28 }; 29 30 const char * const fregnames[32] = { 31 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 32 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 33 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 34 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 35 }; 36 37 static const char * const excp_names[] = { 38 [EXCCODE_INT] = "Interrupt", 39 [EXCCODE_PIL] = "Page invalid exception for load", 40 [EXCCODE_PIS] = "Page invalid exception for store", 41 [EXCCODE_PIF] = "Page invalid exception for fetch", 42 [EXCCODE_PME] = "Page modified exception", 43 [EXCCODE_PNR] = "Page Not Readable exception", 44 [EXCCODE_PNX] = "Page Not Executable exception", 45 [EXCCODE_PPI] = "Page Privilege error", 46 [EXCCODE_ADEF] = "Address error for instruction fetch", 47 [EXCCODE_ADEM] = "Address error for Memory access", 48 [EXCCODE_SYS] = "Syscall", 49 [EXCCODE_BRK] = "Break", 50 [EXCCODE_INE] = "Instruction Non-Existent", 51 [EXCCODE_IPE] = "Instruction privilege error", 52 [EXCCODE_FPD] = "Floating Point Disabled", 53 [EXCCODE_FPE] = "Floating Point Exception", 54 [EXCCODE_DBP] = "Debug breakpoint", 55 [EXCCODE_BCE] = "Bound Check Exception", 56 }; 57 58 const char *loongarch_exception_name(int32_t exception) 59 { 60 assert(excp_names[exception]); 61 return excp_names[exception]; 62 } 63 64 void G_NORETURN do_raise_exception(CPULoongArchState *env, 65 uint32_t exception, 66 uintptr_t pc) 67 { 68 CPUState *cs = env_cpu(env); 69 70 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", 71 __func__, 72 exception, 73 loongarch_exception_name(exception)); 74 cs->exception_index = exception; 75 76 cpu_loop_exit_restore(cs, pc); 77 } 78 79 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 80 { 81 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 82 CPULoongArchState *env = &cpu->env; 83 84 env->pc = value; 85 } 86 87 static vaddr loongarch_cpu_get_pc(CPUState *cs) 88 { 89 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 90 CPULoongArchState *env = &cpu->env; 91 92 return env->pc; 93 } 94 95 #ifndef CONFIG_USER_ONLY 96 #include "hw/loongarch/virt.h" 97 98 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 99 { 100 LoongArchCPU *cpu = opaque; 101 CPULoongArchState *env = &cpu->env; 102 CPUState *cs = CPU(cpu); 103 104 if (irq < 0 || irq >= N_IRQS) { 105 return; 106 } 107 108 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 109 110 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 111 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 112 } else { 113 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 114 } 115 } 116 117 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 118 { 119 bool ret = 0; 120 121 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 122 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 123 124 return ret; 125 } 126 127 /* Check if there is pending and not masked out interrupt */ 128 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 129 { 130 uint32_t pending; 131 uint32_t status; 132 133 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 134 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 135 136 return (pending & status) != 0; 137 } 138 139 static void loongarch_cpu_do_interrupt(CPUState *cs) 140 { 141 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 142 CPULoongArchState *env = &cpu->env; 143 bool update_badinstr = 1; 144 int cause = -1; 145 const char *name; 146 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 147 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 148 149 if (cs->exception_index != EXCCODE_INT) { 150 if (cs->exception_index < 0 || 151 cs->exception_index >= ARRAY_SIZE(excp_names)) { 152 name = "unknown"; 153 } else { 154 name = excp_names[cs->exception_index]; 155 } 156 157 qemu_log_mask(CPU_LOG_INT, 158 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 159 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, 160 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); 161 } 162 163 switch (cs->exception_index) { 164 case EXCCODE_DBP: 165 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 166 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 167 goto set_DERA; 168 set_DERA: 169 env->CSR_DERA = env->pc; 170 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 171 env->pc = env->CSR_EENTRY + 0x480; 172 break; 173 case EXCCODE_INT: 174 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 175 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 176 goto set_DERA; 177 } 178 QEMU_FALLTHROUGH; 179 case EXCCODE_PIF: 180 case EXCCODE_ADEF: 181 cause = cs->exception_index; 182 update_badinstr = 0; 183 break; 184 case EXCCODE_SYS: 185 case EXCCODE_BRK: 186 case EXCCODE_INE: 187 case EXCCODE_IPE: 188 case EXCCODE_FPD: 189 case EXCCODE_FPE: 190 case EXCCODE_BCE: 191 env->CSR_BADV = env->pc; 192 QEMU_FALLTHROUGH; 193 case EXCCODE_ADEM: 194 case EXCCODE_PIL: 195 case EXCCODE_PIS: 196 case EXCCODE_PME: 197 case EXCCODE_PNR: 198 case EXCCODE_PNX: 199 case EXCCODE_PPI: 200 cause = cs->exception_index; 201 break; 202 default: 203 qemu_log("Error: exception(%d) has not been supported\n", 204 cs->exception_index); 205 abort(); 206 } 207 208 if (update_badinstr) { 209 env->CSR_BADI = cpu_ldl_code(env, env->pc); 210 } 211 212 /* Save PLV and IE */ 213 if (tlbfill) { 214 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 215 FIELD_EX64(env->CSR_CRMD, 216 CSR_CRMD, PLV)); 217 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 218 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 219 /* set the DA mode */ 220 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 221 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 222 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 223 PC, (env->pc >> 2)); 224 } else { 225 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 226 EXCODE_MCODE(cause)); 227 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 228 EXCODE_SUBCODE(cause)); 229 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 230 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 231 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 232 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 233 env->CSR_ERA = env->pc; 234 } 235 236 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 237 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 238 239 if (vec_size) { 240 vec_size = (1 << vec_size) * 4; 241 } 242 243 if (cs->exception_index == EXCCODE_INT) { 244 /* Interrupt */ 245 uint32_t vector = 0; 246 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 247 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 248 249 /* Find the highest-priority interrupt. */ 250 vector = 31 - clz32(pending); 251 env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size; 252 qemu_log_mask(CPU_LOG_INT, 253 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 254 " cause %d\n" " A " TARGET_FMT_lx " D " 255 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 256 TARGET_FMT_lx "\n", 257 __func__, env->pc, env->CSR_ERA, 258 cause, env->CSR_BADV, env->CSR_DERA, vector, 259 env->CSR_ECFG, env->CSR_ESTAT); 260 } else { 261 if (tlbfill) { 262 env->pc = env->CSR_TLBRENTRY; 263 } else { 264 env->pc = env->CSR_EENTRY; 265 env->pc += EXCODE_MCODE(cause) * vec_size; 266 } 267 qemu_log_mask(CPU_LOG_INT, 268 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 269 " cause %d%s\n, ESTAT " TARGET_FMT_lx 270 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 271 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 272 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 273 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 274 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 275 env->CSR_ECFG, 276 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 277 env->CSR_BADI, env->gpr[11], cs->cpu_index, 278 env->CSR_ASID); 279 } 280 cs->exception_index = -1; 281 } 282 283 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 284 vaddr addr, unsigned size, 285 MMUAccessType access_type, 286 int mmu_idx, MemTxAttrs attrs, 287 MemTxResult response, 288 uintptr_t retaddr) 289 { 290 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 291 CPULoongArchState *env = &cpu->env; 292 293 if (access_type == MMU_INST_FETCH) { 294 do_raise_exception(env, EXCCODE_ADEF, retaddr); 295 } else { 296 do_raise_exception(env, EXCCODE_ADEM, retaddr); 297 } 298 } 299 300 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 301 { 302 if (interrupt_request & CPU_INTERRUPT_HARD) { 303 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 304 CPULoongArchState *env = &cpu->env; 305 306 if (cpu_loongarch_hw_interrupts_enabled(env) && 307 cpu_loongarch_hw_interrupts_pending(env)) { 308 /* Raise it */ 309 cs->exception_index = EXCCODE_INT; 310 loongarch_cpu_do_interrupt(cs); 311 return true; 312 } 313 } 314 return false; 315 } 316 #endif 317 318 #ifdef CONFIG_TCG 319 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 320 const TranslationBlock *tb) 321 { 322 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 323 CPULoongArchState *env = &cpu->env; 324 325 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 326 env->pc = tb->pc; 327 } 328 329 static void loongarch_restore_state_to_opc(CPUState *cs, 330 const TranslationBlock *tb, 331 const uint64_t *data) 332 { 333 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 334 CPULoongArchState *env = &cpu->env; 335 336 env->pc = data[0]; 337 } 338 #endif /* CONFIG_TCG */ 339 340 static bool loongarch_cpu_has_work(CPUState *cs) 341 { 342 #ifdef CONFIG_USER_ONLY 343 return true; 344 #else 345 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 346 CPULoongArchState *env = &cpu->env; 347 bool has_work = false; 348 349 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 350 cpu_loongarch_hw_interrupts_pending(env)) { 351 has_work = true; 352 } 353 354 return has_work; 355 #endif 356 } 357 358 static void loongarch_la464_initfn(Object *obj) 359 { 360 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 361 CPULoongArchState *env = &cpu->env; 362 int i; 363 364 for (i = 0; i < 21; i++) { 365 env->cpucfg[i] = 0x0; 366 } 367 368 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 369 env->cpucfg[0] = 0x14c010; /* PRID */ 370 371 uint32_t data = 0; 372 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 373 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 374 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 375 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); 376 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 377 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 378 data = FIELD_DP32(data, CPUCFG1, RI, 1); 379 data = FIELD_DP32(data, CPUCFG1, EP, 1); 380 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 381 data = FIELD_DP32(data, CPUCFG1, HP, 1); 382 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 383 env->cpucfg[1] = data; 384 385 data = 0; 386 data = FIELD_DP32(data, CPUCFG2, FP, 1); 387 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 388 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 389 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 390 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 391 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 392 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 393 env->cpucfg[2] = data; 394 395 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 396 397 data = 0; 398 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 399 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 400 env->cpucfg[5] = data; 401 402 data = 0; 403 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 404 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 405 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 406 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 407 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 408 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 409 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 410 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 411 env->cpucfg[16] = data; 412 413 data = 0; 414 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 415 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 416 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 417 env->cpucfg[17] = data; 418 419 data = 0; 420 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 421 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 422 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 423 env->cpucfg[18] = data; 424 425 data = 0; 426 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 427 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 428 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 429 env->cpucfg[19] = data; 430 431 data = 0; 432 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 433 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 434 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 435 env->cpucfg[20] = data; 436 437 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 438 } 439 440 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) 441 { 442 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 443 444 qemu_printf("%s\n", typename); 445 } 446 447 void loongarch_cpu_list(void) 448 { 449 GSList *list; 450 list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false); 451 g_slist_foreach(list, loongarch_cpu_list_entry, NULL); 452 g_slist_free(list); 453 } 454 455 static void loongarch_cpu_reset_hold(Object *obj) 456 { 457 CPUState *cs = CPU(obj); 458 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 459 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); 460 CPULoongArchState *env = &cpu->env; 461 462 if (lacc->parent_phases.hold) { 463 lacc->parent_phases.hold(obj); 464 } 465 466 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 467 env->fcsr0 = 0x0; 468 469 int n; 470 /* Set csr registers value after reset */ 471 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 472 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 473 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 474 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 475 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); 476 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); 477 478 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 479 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 480 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 481 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 482 483 env->CSR_MISC = 0; 484 485 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 486 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 487 488 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 489 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 490 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 491 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 492 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 493 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 494 495 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 496 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 497 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 498 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 499 500 for (n = 0; n < 4; n++) { 501 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 502 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 503 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 504 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 505 } 506 507 #ifndef CONFIG_USER_ONLY 508 env->pc = 0x1c000000; 509 memset(env->tlb, 0, sizeof(env->tlb)); 510 #endif 511 512 restore_fp_status(env); 513 cs->exception_index = -1; 514 } 515 516 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 517 { 518 info->print_insn = print_insn_loongarch; 519 } 520 521 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 522 { 523 CPUState *cs = CPU(dev); 524 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 525 Error *local_err = NULL; 526 527 cpu_exec_realizefn(cs, &local_err); 528 if (local_err != NULL) { 529 error_propagate(errp, local_err); 530 return; 531 } 532 533 loongarch_cpu_register_gdb_regs_for_features(cs); 534 535 cpu_reset(cs); 536 qemu_init_vcpu(cs); 537 538 lacc->parent_realize(dev, errp); 539 } 540 541 #ifndef CONFIG_USER_ONLY 542 static void loongarch_qemu_write(void *opaque, hwaddr addr, 543 uint64_t val, unsigned size) 544 { 545 } 546 547 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 548 { 549 switch (addr) { 550 case FEATURE_REG: 551 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 552 1ULL << IOCSRF_CSRIPI; 553 case VENDOR_REG: 554 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 555 case CPUNAME_REG: 556 return 0x303030354133ULL; /* "3A5000" */ 557 case MISC_FUNC_REG: 558 return 1ULL << IOCSRM_EXTIOI_EN; 559 } 560 return 0ULL; 561 } 562 563 static const MemoryRegionOps loongarch_qemu_ops = { 564 .read = loongarch_qemu_read, 565 .write = loongarch_qemu_write, 566 .endianness = DEVICE_LITTLE_ENDIAN, 567 .valid = { 568 .min_access_size = 4, 569 .max_access_size = 8, 570 }, 571 .impl = { 572 .min_access_size = 8, 573 .max_access_size = 8, 574 }, 575 }; 576 #endif 577 578 static void loongarch_cpu_init(Object *obj) 579 { 580 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 581 582 cpu_set_cpustate_pointers(cpu); 583 584 #ifndef CONFIG_USER_ONLY 585 CPULoongArchState *env = &cpu->env; 586 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 587 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 588 &loongarch_constant_timer_cb, cpu); 589 memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, 590 env, "iocsr", UINT64_MAX); 591 address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); 592 memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, 593 NULL, "iocsr_misc", 0x428); 594 memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); 595 #endif 596 } 597 598 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 599 { 600 ObjectClass *oc; 601 602 oc = object_class_by_name(cpu_model); 603 if (!oc) { 604 g_autofree char *typename 605 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 606 oc = object_class_by_name(typename); 607 if (!oc) { 608 return NULL; 609 } 610 } 611 612 if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) 613 && !object_class_is_abstract(oc)) { 614 return oc; 615 } 616 return NULL; 617 } 618 619 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 620 { 621 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 622 CPULoongArchState *env = &cpu->env; 623 int i; 624 625 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 626 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, 627 get_float_exception_flags(&env->fp_status)); 628 629 /* gpr */ 630 for (i = 0; i < 32; i++) { 631 if ((i & 3) == 0) { 632 qemu_fprintf(f, " GPR%02d:", i); 633 } 634 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 635 if ((i & 3) == 3) { 636 qemu_fprintf(f, "\n"); 637 } 638 } 639 640 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); 641 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); 642 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); 643 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); 644 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); 645 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); 646 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); 647 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); 648 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," 649 " PRCFG3=%016" PRIx64 "\n", 650 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); 651 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); 652 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); 653 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); 654 655 /* fpr */ 656 if (flags & CPU_DUMP_FPU) { 657 for (i = 0; i < 32; i++) { 658 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]); 659 if ((i & 3) == 3) { 660 qemu_fprintf(f, "\n"); 661 } 662 } 663 } 664 } 665 666 #ifdef CONFIG_TCG 667 #include "hw/core/tcg-cpu-ops.h" 668 669 static struct TCGCPUOps loongarch_tcg_ops = { 670 .initialize = loongarch_translate_init, 671 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 672 .restore_state_to_opc = loongarch_restore_state_to_opc, 673 674 #ifndef CONFIG_USER_ONLY 675 .tlb_fill = loongarch_cpu_tlb_fill, 676 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 677 .do_interrupt = loongarch_cpu_do_interrupt, 678 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 679 #endif 680 }; 681 #endif /* CONFIG_TCG */ 682 683 #ifndef CONFIG_USER_ONLY 684 #include "hw/core/sysemu-cpu-ops.h" 685 686 static const struct SysemuCPUOps loongarch_sysemu_ops = { 687 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 688 }; 689 #endif 690 691 static gchar *loongarch_gdb_arch_name(CPUState *cs) 692 { 693 return g_strdup("loongarch64"); 694 } 695 696 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 697 { 698 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 699 CPUClass *cc = CPU_CLASS(c); 700 DeviceClass *dc = DEVICE_CLASS(c); 701 ResettableClass *rc = RESETTABLE_CLASS(c); 702 703 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 704 &lacc->parent_realize); 705 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, 706 &lacc->parent_phases); 707 708 cc->class_by_name = loongarch_cpu_class_by_name; 709 cc->has_work = loongarch_cpu_has_work; 710 cc->dump_state = loongarch_cpu_dump_state; 711 cc->set_pc = loongarch_cpu_set_pc; 712 cc->get_pc = loongarch_cpu_get_pc; 713 #ifndef CONFIG_USER_ONLY 714 dc->vmsd = &vmstate_loongarch_cpu; 715 cc->sysemu_ops = &loongarch_sysemu_ops; 716 #endif 717 cc->disas_set_info = loongarch_cpu_disas_set_info; 718 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 719 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 720 cc->disas_set_info = loongarch_cpu_disas_set_info; 721 cc->gdb_num_core_regs = 35; 722 cc->gdb_core_xml_file = "loongarch-base64.xml"; 723 cc->gdb_stop_before_watchpoint = true; 724 cc->gdb_arch_name = loongarch_gdb_arch_name; 725 726 #ifdef CONFIG_TCG 727 cc->tcg_ops = &loongarch_tcg_ops; 728 #endif 729 } 730 731 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ 732 { \ 733 .parent = TYPE_LOONGARCH_CPU, \ 734 .instance_init = initfn, \ 735 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 736 } 737 738 static const TypeInfo loongarch_cpu_type_infos[] = { 739 { 740 .name = TYPE_LOONGARCH_CPU, 741 .parent = TYPE_CPU, 742 .instance_size = sizeof(LoongArchCPU), 743 .instance_init = loongarch_cpu_init, 744 745 .abstract = true, 746 .class_size = sizeof(LoongArchCPUClass), 747 .class_init = loongarch_cpu_class_init, 748 }, 749 DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn), 750 }; 751 752 DEFINE_TYPES(loongarch_cpu_type_infos) 753 754 static void loongarch_cpu_add_definition(gpointer data, gpointer user_data) 755 { 756 ObjectClass *oc = data; 757 CpuDefinitionInfoList **cpu_list = user_data; 758 CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1); 759 const char *typename = object_class_get_name(oc); 760 761 info->name = g_strndup(typename, 762 strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU)); 763 info->q_typename = g_strdup(typename); 764 765 QAPI_LIST_PREPEND(*cpu_list, info); 766 } 767 768 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 769 { 770 CpuDefinitionInfoList *cpu_list = NULL; 771 GSList *list; 772 773 list = object_class_get_list(TYPE_LOONGARCH_CPU, false); 774 g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list); 775 g_slist_free(list); 776 777 return cpu_list; 778 } 779