1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "sysemu/qtest.h" 14 #include "exec/exec-all.h" 15 #include "qapi/qapi-commands-machine-target.h" 16 #include "cpu.h" 17 #include "internals.h" 18 #include "fpu/softfloat-helpers.h" 19 #include "cpu-csr.h" 20 #include "sysemu/reset.h" 21 #include "hw/loader.h" 22 23 const char * const regnames[32] = { 24 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 25 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 26 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 27 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 28 }; 29 30 const char * const fregnames[32] = { 31 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 32 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 33 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 34 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 35 }; 36 37 static const char * const excp_names[] = { 38 [EXCCODE_INT] = "Interrupt", 39 [EXCCODE_PIL] = "Page invalid exception for load", 40 [EXCCODE_PIS] = "Page invalid exception for store", 41 [EXCCODE_PIF] = "Page invalid exception for fetch", 42 [EXCCODE_PME] = "Page modified exception", 43 [EXCCODE_PNR] = "Page Not Readable exception", 44 [EXCCODE_PNX] = "Page Not Executable exception", 45 [EXCCODE_PPI] = "Page Privilege error", 46 [EXCCODE_ADEF] = "Address error for instruction fetch", 47 [EXCCODE_ADEM] = "Address error for Memory access", 48 [EXCCODE_SYS] = "Syscall", 49 [EXCCODE_BRK] = "Break", 50 [EXCCODE_INE] = "Instruction Non-Existent", 51 [EXCCODE_IPE] = "Instruction privilege error", 52 [EXCCODE_FPE] = "Floating Point Exception", 53 [EXCCODE_DBP] = "Debug breakpoint", 54 }; 55 56 const char *loongarch_exception_name(int32_t exception) 57 { 58 assert(excp_names[exception]); 59 return excp_names[exception]; 60 } 61 62 void G_NORETURN do_raise_exception(CPULoongArchState *env, 63 uint32_t exception, 64 uintptr_t pc) 65 { 66 CPUState *cs = env_cpu(env); 67 68 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", 69 __func__, 70 exception, 71 loongarch_exception_name(exception)); 72 cs->exception_index = exception; 73 74 cpu_loop_exit_restore(cs, pc); 75 } 76 77 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 78 { 79 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 80 CPULoongArchState *env = &cpu->env; 81 82 env->pc = value; 83 } 84 85 #include "hw/loongarch/virt.h" 86 87 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 88 { 89 LoongArchCPU *cpu = opaque; 90 CPULoongArchState *env = &cpu->env; 91 CPUState *cs = CPU(cpu); 92 93 if (irq < 0 || irq >= N_IRQS) { 94 return; 95 } 96 97 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 98 99 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 100 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 101 } else { 102 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 103 } 104 } 105 106 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 107 { 108 bool ret = 0; 109 110 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 111 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 112 113 return ret; 114 } 115 116 /* Check if there is pending and not masked out interrupt */ 117 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 118 { 119 uint32_t pending; 120 uint32_t status; 121 bool r; 122 123 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 124 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 125 126 r = (pending & status) != 0; 127 return r; 128 } 129 130 static void loongarch_cpu_do_interrupt(CPUState *cs) 131 { 132 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 133 CPULoongArchState *env = &cpu->env; 134 bool update_badinstr = 1; 135 int cause = -1; 136 const char *name; 137 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 138 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 139 140 if (cs->exception_index != EXCCODE_INT) { 141 if (cs->exception_index < 0 || 142 cs->exception_index > ARRAY_SIZE(excp_names)) { 143 name = "unknown"; 144 } else { 145 name = excp_names[cs->exception_index]; 146 } 147 148 qemu_log_mask(CPU_LOG_INT, 149 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 150 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, 151 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); 152 } 153 154 switch (cs->exception_index) { 155 case EXCCODE_DBP: 156 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 157 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 158 goto set_DERA; 159 set_DERA: 160 env->CSR_DERA = env->pc; 161 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 162 env->pc = env->CSR_EENTRY + 0x480; 163 break; 164 case EXCCODE_INT: 165 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 166 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 167 goto set_DERA; 168 } 169 QEMU_FALLTHROUGH; 170 case EXCCODE_PIF: 171 cause = cs->exception_index; 172 update_badinstr = 0; 173 break; 174 case EXCCODE_ADEM: 175 case EXCCODE_SYS: 176 case EXCCODE_BRK: 177 case EXCCODE_PIL: 178 case EXCCODE_PIS: 179 case EXCCODE_PME: 180 case EXCCODE_PNR: 181 case EXCCODE_PNX: 182 case EXCCODE_PPI: 183 case EXCCODE_INE: 184 case EXCCODE_IPE: 185 case EXCCODE_FPE: 186 cause = cs->exception_index; 187 break; 188 default: 189 qemu_log("Error: exception(%d) '%s' has not been supported\n", 190 cs->exception_index, excp_names[cs->exception_index]); 191 abort(); 192 } 193 194 if (update_badinstr) { 195 env->CSR_BADI = cpu_ldl_code(env, env->pc); 196 } 197 198 /* Save PLV and IE */ 199 if (tlbfill) { 200 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 201 FIELD_EX64(env->CSR_CRMD, 202 CSR_CRMD, PLV)); 203 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 204 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 205 /* set the DA mode */ 206 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 207 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 208 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 209 PC, (env->pc >> 2)); 210 } else { 211 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause); 212 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 213 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 214 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 215 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 216 env->CSR_ERA = env->pc; 217 } 218 219 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 220 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 221 222 if (cs->exception_index == EXCCODE_INT) { 223 /* Interrupt */ 224 uint32_t vector = 0; 225 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 226 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 227 228 /* Find the highest-priority interrupt. */ 229 vector = 31 - clz32(pending); 230 env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size; 231 qemu_log_mask(CPU_LOG_INT, 232 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 233 " cause %d\n" " A " TARGET_FMT_lx " D " 234 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 235 TARGET_FMT_lx "\n", 236 __func__, env->pc, env->CSR_ERA, 237 cause, env->CSR_BADV, env->CSR_DERA, vector, 238 env->CSR_ECFG, env->CSR_ESTAT); 239 } else { 240 if (tlbfill) { 241 env->pc = env->CSR_TLBRENTRY; 242 } else { 243 env->pc = env->CSR_EENTRY; 244 env->pc += cause * vec_size; 245 } 246 qemu_log_mask(CPU_LOG_INT, 247 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 248 " cause %d%s\n, ESTAT " TARGET_FMT_lx 249 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 250 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 251 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 252 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 253 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 254 env->CSR_ECFG, 255 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 256 env->CSR_BADI, env->gpr[11], cs->cpu_index, 257 env->CSR_ASID); 258 } 259 cs->exception_index = -1; 260 } 261 262 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 263 vaddr addr, unsigned size, 264 MMUAccessType access_type, 265 int mmu_idx, MemTxAttrs attrs, 266 MemTxResult response, 267 uintptr_t retaddr) 268 { 269 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 270 CPULoongArchState *env = &cpu->env; 271 272 if (access_type == MMU_INST_FETCH) { 273 do_raise_exception(env, EXCCODE_ADEF, retaddr); 274 } else { 275 do_raise_exception(env, EXCCODE_ADEM, retaddr); 276 } 277 } 278 279 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 280 { 281 if (interrupt_request & CPU_INTERRUPT_HARD) { 282 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 283 CPULoongArchState *env = &cpu->env; 284 285 if (cpu_loongarch_hw_interrupts_enabled(env) && 286 cpu_loongarch_hw_interrupts_pending(env)) { 287 /* Raise it */ 288 cs->exception_index = EXCCODE_INT; 289 loongarch_cpu_do_interrupt(cs); 290 return true; 291 } 292 } 293 return false; 294 } 295 296 #ifdef CONFIG_TCG 297 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 298 const TranslationBlock *tb) 299 { 300 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 301 CPULoongArchState *env = &cpu->env; 302 303 env->pc = tb->pc; 304 } 305 #endif /* CONFIG_TCG */ 306 307 static bool loongarch_cpu_has_work(CPUState *cs) 308 { 309 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 310 CPULoongArchState *env = &cpu->env; 311 bool has_work = false; 312 313 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 314 cpu_loongarch_hw_interrupts_pending(env)) { 315 has_work = true; 316 } 317 318 return has_work; 319 } 320 321 static void loongarch_la464_initfn(Object *obj) 322 { 323 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 324 CPULoongArchState *env = &cpu->env; 325 int i; 326 327 for (i = 0; i < 21; i++) { 328 env->cpucfg[i] = 0x0; 329 } 330 331 env->cpucfg[0] = 0x14c010; /* PRID */ 332 333 uint32_t data = 0; 334 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 335 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 336 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 337 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); 338 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 339 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 340 data = FIELD_DP32(data, CPUCFG1, RI, 1); 341 data = FIELD_DP32(data, CPUCFG1, EP, 1); 342 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 343 data = FIELD_DP32(data, CPUCFG1, HP, 1); 344 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 345 env->cpucfg[1] = data; 346 347 data = 0; 348 data = FIELD_DP32(data, CPUCFG2, FP, 1); 349 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 350 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 351 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 352 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 353 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 354 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 355 env->cpucfg[2] = data; 356 357 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 358 359 data = 0; 360 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 361 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 362 env->cpucfg[5] = data; 363 364 data = 0; 365 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 366 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 367 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 368 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 369 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 370 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 371 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 372 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 373 env->cpucfg[16] = data; 374 375 data = 0; 376 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 377 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 378 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 379 env->cpucfg[17] = data; 380 381 data = 0; 382 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 383 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 384 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 385 env->cpucfg[18] = data; 386 387 data = 0; 388 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 389 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 390 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 391 env->cpucfg[19] = data; 392 393 data = 0; 394 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 395 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 396 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 6); 397 env->cpucfg[20] = data; 398 399 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 400 } 401 402 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) 403 { 404 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 405 406 qemu_printf("%s\n", typename); 407 } 408 409 void loongarch_cpu_list(void) 410 { 411 GSList *list; 412 list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false); 413 g_slist_foreach(list, loongarch_cpu_list_entry, NULL); 414 g_slist_free(list); 415 } 416 417 static void loongarch_cpu_reset(DeviceState *dev) 418 { 419 CPUState *cs = CPU(dev); 420 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 421 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); 422 CPULoongArchState *env = &cpu->env; 423 424 lacc->parent_reset(dev); 425 426 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 427 env->fcsr0 = 0x0; 428 429 int n; 430 /* Set csr registers value after reset */ 431 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 432 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 433 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 434 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 435 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); 436 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); 437 438 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 439 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 440 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 441 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 442 443 env->CSR_MISC = 0; 444 445 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 446 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 447 448 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 449 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 450 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 451 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 452 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 453 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 454 455 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 456 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 457 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 458 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 459 460 for (n = 0; n < 4; n++) { 461 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 462 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 463 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 464 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 465 } 466 467 env->pc = 0x1c000000; 468 469 restore_fp_status(env); 470 cs->exception_index = -1; 471 } 472 473 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 474 { 475 info->print_insn = print_insn_loongarch; 476 } 477 478 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 479 { 480 CPUState *cs = CPU(dev); 481 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 482 Error *local_err = NULL; 483 484 cpu_exec_realizefn(cs, &local_err); 485 if (local_err != NULL) { 486 error_propagate(errp, local_err); 487 return; 488 } 489 490 loongarch_cpu_register_gdb_regs_for_features(cs); 491 492 cpu_reset(cs); 493 qemu_init_vcpu(cs); 494 495 lacc->parent_realize(dev, errp); 496 } 497 498 static void loongarch_qemu_write(void *opaque, hwaddr addr, 499 uint64_t val, unsigned size) 500 { 501 } 502 503 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 504 { 505 switch (addr) { 506 case FEATURE_REG: 507 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 508 1ULL << IOCSRF_CSRIPI; 509 case VENDOR_REG: 510 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 511 case CPUNAME_REG: 512 return 0x303030354133ULL; /* "3A5000" */ 513 case MISC_FUNC_REG: 514 return 1ULL << IOCSRM_EXTIOI_EN; 515 } 516 return 0ULL; 517 } 518 519 static const MemoryRegionOps loongarch_qemu_ops = { 520 .read = loongarch_qemu_read, 521 .write = loongarch_qemu_write, 522 .endianness = DEVICE_LITTLE_ENDIAN, 523 .valid = { 524 .min_access_size = 4, 525 .max_access_size = 8, 526 }, 527 .impl = { 528 .min_access_size = 8, 529 .max_access_size = 8, 530 }, 531 }; 532 533 static void loongarch_cpu_init(Object *obj) 534 { 535 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 536 CPULoongArchState *env = &cpu->env; 537 538 cpu_set_cpustate_pointers(cpu); 539 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 540 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 541 &loongarch_constant_timer_cb, cpu); 542 memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, 543 env, "iocsr", UINT64_MAX); 544 address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); 545 memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, 546 NULL, "iocsr_misc", 0x428); 547 memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); 548 } 549 550 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 551 { 552 ObjectClass *oc; 553 char *typename; 554 555 typename = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 556 oc = object_class_by_name(typename); 557 g_free(typename); 558 return oc; 559 } 560 561 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 562 { 563 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 564 CPULoongArchState *env = &cpu->env; 565 int i; 566 567 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 568 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, 569 get_float_exception_flags(&env->fp_status)); 570 571 /* gpr */ 572 for (i = 0; i < 32; i++) { 573 if ((i & 3) == 0) { 574 qemu_fprintf(f, " GPR%02d:", i); 575 } 576 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 577 if ((i & 3) == 3) { 578 qemu_fprintf(f, "\n"); 579 } 580 } 581 582 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); 583 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); 584 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); 585 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); 586 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); 587 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); 588 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); 589 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); 590 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," 591 " PRCFG3=%016" PRIx64 "\n", 592 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); 593 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); 594 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); 595 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); 596 597 /* fpr */ 598 if (flags & CPU_DUMP_FPU) { 599 for (i = 0; i < 32; i++) { 600 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]); 601 if ((i & 3) == 3) { 602 qemu_fprintf(f, "\n"); 603 } 604 } 605 } 606 } 607 608 #ifdef CONFIG_TCG 609 #include "hw/core/tcg-cpu-ops.h" 610 611 static struct TCGCPUOps loongarch_tcg_ops = { 612 .initialize = loongarch_translate_init, 613 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 614 615 .tlb_fill = loongarch_cpu_tlb_fill, 616 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 617 .do_interrupt = loongarch_cpu_do_interrupt, 618 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 619 }; 620 #endif /* CONFIG_TCG */ 621 622 #include "hw/core/sysemu-cpu-ops.h" 623 624 static const struct SysemuCPUOps loongarch_sysemu_ops = { 625 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 626 }; 627 628 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 629 { 630 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 631 CPUClass *cc = CPU_CLASS(c); 632 DeviceClass *dc = DEVICE_CLASS(c); 633 634 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 635 &lacc->parent_realize); 636 device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset); 637 638 cc->class_by_name = loongarch_cpu_class_by_name; 639 cc->has_work = loongarch_cpu_has_work; 640 cc->dump_state = loongarch_cpu_dump_state; 641 cc->set_pc = loongarch_cpu_set_pc; 642 dc->vmsd = &vmstate_loongarch_cpu; 643 cc->sysemu_ops = &loongarch_sysemu_ops; 644 cc->disas_set_info = loongarch_cpu_disas_set_info; 645 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 646 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 647 cc->disas_set_info = loongarch_cpu_disas_set_info; 648 cc->gdb_num_core_regs = 34; 649 cc->gdb_core_xml_file = "loongarch-base64.xml"; 650 cc->gdb_stop_before_watchpoint = true; 651 652 #ifdef CONFIG_TCG 653 cc->tcg_ops = &loongarch_tcg_ops; 654 #endif 655 } 656 657 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ 658 { \ 659 .parent = TYPE_LOONGARCH_CPU, \ 660 .instance_init = initfn, \ 661 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 662 } 663 664 static const TypeInfo loongarch_cpu_type_infos[] = { 665 { 666 .name = TYPE_LOONGARCH_CPU, 667 .parent = TYPE_CPU, 668 .instance_size = sizeof(LoongArchCPU), 669 .instance_init = loongarch_cpu_init, 670 671 .abstract = true, 672 .class_size = sizeof(LoongArchCPUClass), 673 .class_init = loongarch_cpu_class_init, 674 }, 675 DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn), 676 }; 677 678 DEFINE_TYPES(loongarch_cpu_type_infos) 679 680 static void loongarch_cpu_add_definition(gpointer data, gpointer user_data) 681 { 682 ObjectClass *oc = data; 683 CpuDefinitionInfoList **cpu_list = user_data; 684 CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1); 685 const char *typename = object_class_get_name(oc); 686 687 info->name = g_strndup(typename, 688 strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU)); 689 info->q_typename = g_strdup(typename); 690 691 QAPI_LIST_PREPEND(*cpu_list, info); 692 } 693 694 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 695 { 696 CpuDefinitionInfoList *cpu_list = NULL; 697 GSList *list; 698 699 list = object_class_get_list(TYPE_LOONGARCH_CPU, false); 700 g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list); 701 g_slist_free(list); 702 703 return cpu_list; 704 } 705