1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CSRs 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef LOONGARCH_CPU_CSR_H 9 #define LOONGARCH_CPU_CSR_H 10 11 #include "hw/registerfields.h" 12 13 /* Base on kernal definitions: arch/loongarch/include/asm/loongarch.h */ 14 15 /* Basic CSRs */ 16 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ 17 18 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */ 19 FIELD(CSR_PRMD, PPLV, 0, 2) 20 FIELD(CSR_PRMD, PIE, 2, 1) 21 FIELD(CSR_PRMD, PWE, 3, 1) 22 23 #define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */ 24 FIELD(CSR_EUEN, FPE, 0, 1) 25 FIELD(CSR_EUEN, SXE, 1, 1) 26 FIELD(CSR_EUEN, ASXE, 2, 1) 27 FIELD(CSR_EUEN, BTE, 3, 1) 28 29 #define LOONGARCH_CSR_MISC 0x3 /* Misc config */ 30 FIELD(CSR_MISC, VA32, 0, 4) 31 FIELD(CSR_MISC, DRDTL, 4, 4) 32 FIELD(CSR_MISC, RPCNTL, 8, 4) 33 FIELD(CSR_MISC, ALCL, 12, 4) 34 FIELD(CSR_MISC, DWPL, 16, 3) 35 36 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ 37 FIELD(CSR_ECFG, LIE, 0, 13) 38 FIELD(CSR_ECFG, VS, 16, 3) 39 40 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ 41 FIELD(CSR_ESTAT, IS, 0, 13) 42 FIELD(CSR_ESTAT, ECODE, 16, 6) 43 FIELD(CSR_ESTAT, ESUBCODE, 22, 9) 44 45 #define LOONGARCH_CSR_ERA 0x6 /* Exception return address */ 46 47 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ 48 49 #define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */ 50 51 #define LOONGARCH_CSR_EENTRY 0xc /* Exception entry address */ 52 53 /* TLB related CSRs */ 54 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */ 55 FIELD(CSR_TLBIDX, INDEX, 0, 12) 56 FIELD(CSR_TLBIDX, PS, 24, 6) 57 FIELD(CSR_TLBIDX, NE, 31, 1) 58 59 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */ 60 FIELD(CSR_TLBEHI, VPPN, 13, 35) 61 62 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */ 63 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */ 64 FIELD(TLBENTRY, V, 0, 1) 65 FIELD(TLBENTRY, D, 1, 1) 66 FIELD(TLBENTRY, PLV, 2, 2) 67 FIELD(TLBENTRY, MAT, 4, 2) 68 FIELD(TLBENTRY, G, 6, 1) 69 FIELD(TLBENTRY, PPN, 12, 36) 70 FIELD(TLBENTRY, NR, 61, 1) 71 FIELD(TLBENTRY, NX, 62, 1) 72 FIELD(TLBENTRY, RPLV, 63, 1) 73 74 #define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */ 75 FIELD(CSR_ASID, ASID, 0, 10) 76 FIELD(CSR_ASID, ASIDBITS, 16, 8) 77 78 /* Page table base address when badv[47] = 0 */ 79 #define LOONGARCH_CSR_PGDL 0x19 80 /* Page table base address when badv[47] = 1 */ 81 #define LOONGARCH_CSR_PGDH 0x1a 82 83 #define LOONGARCH_CSR_PGD 0x1b /* Page table base address */ 84 85 /* Page walk controller's low addr */ 86 #define LOONGARCH_CSR_PWCL 0x1c 87 FIELD(CSR_PWCL, PTBASE, 0, 5) 88 FIELD(CSR_PWCL, PTWIDTH, 5, 5) 89 FIELD(CSR_PWCL, DIR1_BASE, 10, 5) 90 FIELD(CSR_PWCL, DIR1_WIDTH, 15, 5) 91 FIELD(CSR_PWCL, DIR2_BASE, 20, 5) 92 FIELD(CSR_PWCL, DIR2_WIDTH, 25, 5) 93 FIELD(CSR_PWCL, PTEWIDTH, 30, 2) 94 95 /* Page walk controller's high addr */ 96 #define LOONGARCH_CSR_PWCH 0x1d 97 FIELD(CSR_PWCH, DIR3_BASE, 0, 6) 98 FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6) 99 FIELD(CSR_PWCH, DIR4_BASE, 12, 6) 100 FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6) 101 102 #define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */ 103 FIELD(CSR_STLBPS, PS, 0, 5) 104 105 #define LOONGARCH_CSR_RVACFG 0x1f /* Reduced virtual address config */ 106 FIELD(CSR_RVACFG, RBITS, 0, 4) 107 108 /* Config CSRs */ 109 #define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */ 110 111 #define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */ 112 FIELD(CSR_PRCFG1, SAVE_NUM, 0, 4) 113 FIELD(CSR_PRCFG1, TIMER_BITS, 4, 8) 114 FIELD(CSR_PRCFG1, VSMAX, 12, 3) 115 116 #define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */ 117 118 #define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */ 119 FIELD(CSR_PRCFG3, TLB_TYPE, 0, 4) 120 FIELD(CSR_PRCFG3, MTLB_ENTRY, 4, 8) 121 FIELD(CSR_PRCFG3, STLB_WAYS, 12, 8) 122 FIELD(CSR_PRCFG3, STLB_SETS, 20, 8) 123 124 /* 125 * Save registers count can read from PRCFG1.SAVE_NUM 126 * The Min count is 1. Max count is 15. 127 */ 128 #define LOONGARCH_CSR_SAVE(N) (0x30 + N) 129 130 /* Timer CSRs */ 131 #define LOONGARCH_CSR_TID 0x40 /* Timer ID */ 132 133 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ 134 FIELD(CSR_TCFG, EN, 0, 1) 135 FIELD(CSR_TCFG, PERIODIC, 1, 1) 136 FIELD(CSR_TCFG, INIT_VAL, 2, 46) 137 138 #define LOONGARCH_CSR_TVAL 0x42 /* Timer ticks remain */ 139 140 #define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */ 141 142 #define LOONGARCH_CSR_TICLR 0x44 /* Timer interrupt clear */ 143 144 /* LLBCTL CSRs */ 145 #define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */ 146 FIELD(CSR_LLBCTL, ROLLB, 0, 1) 147 FIELD(CSR_LLBCTL, WCLLB, 1, 1) 148 FIELD(CSR_LLBCTL, KLO, 2, 1) 149 150 /* Implement dependent */ 151 #define LOONGARCH_CSR_IMPCTL1 0x80 /* LoongArch config1 */ 152 153 #define LOONGARCH_CSR_IMPCTL2 0x81 /* LoongArch config2*/ 154 155 /* TLB Refill CSRs */ 156 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception address */ 157 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */ 158 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */ 159 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KScratch for TLB refill */ 160 FIELD(CSR_TLBRERA, ISTLBR, 0, 1) 161 FIELD(CSR_TLBRERA, PC, 2, 62) 162 #define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */ 163 #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */ 164 #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */ 165 FIELD(CSR_TLBREHI, PS, 0, 6) 166 FIELD(CSR_TLBREHI, VPPN, 13, 35) 167 #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */ 168 FIELD(CSR_TLBRPRMD, PPLV, 0, 2) 169 FIELD(CSR_TLBRPRMD, PIE, 2, 1) 170 FIELD(CSR_TLBRPRMD, PWE, 4, 1) 171 172 /* Machine Error CSRs */ 173 #define LOONGARCH_CSR_MERRCTL 0x90 /* ERRCTL */ 174 FIELD(CSR_MERRCTL, ISMERR, 0, 1) 175 #define LOONGARCH_CSR_MERRINFO1 0x91 176 #define LOONGARCH_CSR_MERRINFO2 0x92 177 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception base */ 178 #define LOONGARCH_CSR_MERRERA 0x94 /* MError exception PC */ 179 #define LOONGARCH_CSR_MERRSAVE 0x95 /* KScratch for error exception */ 180 181 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ 182 183 /* Direct map windows CSRs*/ 184 #define LOONGARCH_CSR_DMW(N) (0x180 + N) 185 FIELD(CSR_DMW, PLV0, 0, 1) 186 FIELD(CSR_DMW, PLV1, 1, 1) 187 FIELD(CSR_DMW, PLV2, 2, 1) 188 FIELD(CSR_DMW, PLV3, 3, 1) 189 FIELD(CSR_DMW, MAT, 4, 2) 190 FIELD(CSR_DMW, VSEG, 60, 4) 191 192 #define dmw_va2pa(va) \ 193 (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)) 194 195 /* Debug CSRs */ 196 #define LOONGARCH_CSR_DBG 0x500 /* debug config */ 197 FIELD(CSR_DBG, DST, 0, 1) 198 FIELD(CSR_DBG, DREV, 1, 7) 199 FIELD(CSR_DBG, DEI, 8, 1) 200 FIELD(CSR_DBG, DCL, 9, 1) 201 FIELD(CSR_DBG, DFW, 10, 1) 202 FIELD(CSR_DBG, DMW, 11, 1) 203 FIELD(CSR_DBG, ECODE, 16, 6) 204 205 #define LOONGARCH_CSR_DERA 0x501 /* Debug era */ 206 #define LOONGARCH_CSR_DSAVE 0x502 /* Debug save */ 207 208 #endif /* LOONGARCH_CPU_CSR_H */ 209