1 /* 2 * i386 TCG cpu class initialization 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "helper-tcg.h" 23 #include "qemu/accel.h" 24 #include "hw/core/accel-cpu.h" 25 26 #include "tcg-cpu.h" 27 28 /* Frob eflags into and out of the CPU temporary format. */ 29 30 static void x86_cpu_exec_enter(CPUState *cs) 31 { 32 X86CPU *cpu = X86_CPU(cs); 33 CPUX86State *env = &cpu->env; 34 35 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 36 env->df = 1 - (2 * ((env->eflags >> 10) & 1)); 37 CC_OP = CC_OP_EFLAGS; 38 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 39 } 40 41 static void x86_cpu_exec_exit(CPUState *cs) 42 { 43 X86CPU *cpu = X86_CPU(cs); 44 CPUX86State *env = &cpu->env; 45 46 env->eflags = cpu_compute_eflags(env); 47 } 48 49 static void x86_cpu_synchronize_from_tb(CPUState *cs, 50 const TranslationBlock *tb) 51 { 52 /* The instruction pointer is always up to date with CF_PCREL. */ 53 if (!(tb_cflags(tb) & CF_PCREL)) { 54 CPUX86State *env = cpu_env(cs); 55 56 if (tb->flags & HF_CS64_MASK) { 57 env->eip = tb->pc; 58 } else { 59 env->eip = (uint32_t)(tb->pc - tb->cs_base); 60 } 61 } 62 } 63 64 static void x86_restore_state_to_opc(CPUState *cs, 65 const TranslationBlock *tb, 66 const uint64_t *data) 67 { 68 X86CPU *cpu = X86_CPU(cs); 69 CPUX86State *env = &cpu->env; 70 int cc_op = data[1]; 71 72 if (tb_cflags(tb) & CF_PCREL) { 73 env->eip = (env->eip & TARGET_PAGE_MASK) | data[0]; 74 } else if (tb->flags & HF_CS64_MASK) { 75 env->eip = data[0]; 76 } else { 77 env->eip = (uint32_t)(data[0] - tb->cs_base); 78 } 79 if (cc_op != CC_OP_DYNAMIC) { 80 env->cc_op = cc_op; 81 } 82 } 83 84 #ifndef CONFIG_USER_ONLY 85 static bool x86_debug_check_breakpoint(CPUState *cs) 86 { 87 X86CPU *cpu = X86_CPU(cs); 88 CPUX86State *env = &cpu->env; 89 90 /* RF disables all architectural breakpoints. */ 91 return !(env->eflags & RF_MASK); 92 } 93 #endif 94 95 #include "hw/core/tcg-cpu-ops.h" 96 97 static const struct TCGCPUOps x86_tcg_ops = { 98 .initialize = tcg_x86_init, 99 .synchronize_from_tb = x86_cpu_synchronize_from_tb, 100 .restore_state_to_opc = x86_restore_state_to_opc, 101 .cpu_exec_enter = x86_cpu_exec_enter, 102 .cpu_exec_exit = x86_cpu_exec_exit, 103 #ifdef CONFIG_USER_ONLY 104 .fake_user_interrupt = x86_cpu_do_interrupt, 105 .record_sigsegv = x86_cpu_record_sigsegv, 106 .record_sigbus = x86_cpu_record_sigbus, 107 #else 108 .tlb_fill = x86_cpu_tlb_fill, 109 .do_interrupt = x86_cpu_do_interrupt, 110 .cpu_exec_interrupt = x86_cpu_exec_interrupt, 111 .do_unaligned_access = x86_cpu_do_unaligned_access, 112 .debug_excp_handler = breakpoint_handler, 113 .debug_check_breakpoint = x86_debug_check_breakpoint, 114 #endif /* !CONFIG_USER_ONLY */ 115 }; 116 117 static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 118 { 119 /* for x86, all cpus use the same set of operations */ 120 cc->tcg_ops = &x86_tcg_ops; 121 } 122 123 static void tcg_cpu_class_init(CPUClass *cc) 124 { 125 cc->init_accel_cpu = tcg_cpu_init_ops; 126 } 127 128 static void tcg_cpu_xsave_init(void) 129 { 130 #define XO(bit, field) \ 131 x86_ext_save_areas[bit].offset = offsetof(X86XSaveArea, field); 132 133 XO(XSTATE_FP_BIT, legacy); 134 XO(XSTATE_SSE_BIT, legacy); 135 XO(XSTATE_YMM_BIT, avx_state); 136 XO(XSTATE_BNDREGS_BIT, bndreg_state); 137 XO(XSTATE_BNDCSR_BIT, bndcsr_state); 138 XO(XSTATE_OPMASK_BIT, opmask_state); 139 XO(XSTATE_ZMM_Hi256_BIT, zmm_hi256_state); 140 XO(XSTATE_Hi16_ZMM_BIT, hi16_zmm_state); 141 XO(XSTATE_PKRU_BIT, pkru_state); 142 143 #undef XO 144 } 145 146 /* 147 * TCG-specific defaults that override cpudef models when using TCG. 148 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 149 */ 150 static PropValue tcg_default_props[] = { 151 { "vme", "off" }, 152 { NULL, NULL }, 153 }; 154 155 static void tcg_cpu_instance_init(CPUState *cs) 156 { 157 X86CPU *cpu = X86_CPU(cs); 158 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 159 160 if (xcc->model) { 161 /* Special cases not set in the X86CPUDefinition structs: */ 162 x86_cpu_apply_props(cpu, tcg_default_props); 163 } 164 165 tcg_cpu_xsave_init(); 166 } 167 168 static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 169 { 170 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 171 172 #ifndef CONFIG_USER_ONLY 173 acc->cpu_target_realize = tcg_cpu_realizefn; 174 #endif /* CONFIG_USER_ONLY */ 175 176 acc->cpu_class_init = tcg_cpu_class_init; 177 acc->cpu_instance_init = tcg_cpu_instance_init; 178 } 179 static const TypeInfo tcg_cpu_accel_type_info = { 180 .name = ACCEL_CPU_NAME("tcg"), 181 182 .parent = TYPE_ACCEL_CPU, 183 .class_init = tcg_cpu_accel_class_init, 184 .abstract = true, 185 }; 186 static void tcg_cpu_accel_register_types(void) 187 { 188 type_register_static(&tcg_cpu_accel_type_info); 189 } 190 type_init(tcg_cpu_accel_register_types); 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