1 /* 2 * x86 misc helpers 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "exec/exec-all.h" 24 #include "helper-tcg.h" 25 26 /* 27 * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 28 * after generating a call to a helper that uses this. 29 */ 30 void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask) 31 { 32 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 33 CC_OP = CC_OP_EFLAGS; 34 env->df = 1 - (2 * ((eflags >> 10) & 1)); 35 env->eflags = (env->eflags & ~update_mask) | 36 (eflags & update_mask) | 0x2; 37 } 38 39 void helper_into(CPUX86State *env, int next_eip_addend) 40 { 41 int eflags; 42 43 eflags = cpu_cc_compute_all(env, CC_OP); 44 if (eflags & CC_O) { 45 raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend); 46 } 47 } 48 49 void helper_cpuid(CPUX86State *env) 50 { 51 uint32_t eax, ebx, ecx, edx; 52 53 cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0, GETPC()); 54 55 cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], 56 &eax, &ebx, &ecx, &edx); 57 env->regs[R_EAX] = eax; 58 env->regs[R_EBX] = ebx; 59 env->regs[R_ECX] = ecx; 60 env->regs[R_EDX] = edx; 61 } 62 63 void helper_lmsw(CPUX86State *env, target_ulong t0) 64 { 65 /* only 4 lower bits of CR0 are modified. PE cannot be set to zero 66 if already set to one. */ 67 t0 = (env->cr[0] & ~0xe) | (t0 & 0xf); 68 helper_write_crN(env, 0, t0); 69 } 70 71 void helper_invlpg(CPUX86State *env, target_ulong addr) 72 { 73 X86CPU *cpu = env_archcpu(env); 74 75 cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); 76 tlb_flush_page(CPU(cpu), addr); 77 } 78 79 void helper_rdtsc(CPUX86State *env) 80 { 81 uint64_t val; 82 83 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { 84 raise_exception_ra(env, EXCP0D_GPF, GETPC()); 85 } 86 cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0, GETPC()); 87 88 val = cpu_get_tsc(env) + env->tsc_offset; 89 env->regs[R_EAX] = (uint32_t)(val); 90 env->regs[R_EDX] = (uint32_t)(val >> 32); 91 } 92 93 void helper_rdtscp(CPUX86State *env) 94 { 95 helper_rdtsc(env); 96 env->regs[R_ECX] = (uint32_t)(env->tsc_aux); 97 } 98 99 void helper_rdpmc(CPUX86State *env) 100 { 101 if (((env->cr[4] & CR4_PCE_MASK) == 0 ) && 102 ((env->hflags & HF_CPL_MASK) != 0)) { 103 raise_exception_ra(env, EXCP0D_GPF, GETPC()); 104 } 105 cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0, GETPC()); 106 107 /* currently unimplemented */ 108 qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n"); 109 raise_exception_err(env, EXCP06_ILLOP, 0); 110 } 111 112 static void do_pause(X86CPU *cpu) 113 { 114 CPUState *cs = CPU(cpu); 115 116 /* Just let another CPU run. */ 117 cs->exception_index = EXCP_INTERRUPT; 118 cpu_loop_exit(cs); 119 } 120 121 static void do_hlt(X86CPU *cpu) 122 { 123 CPUState *cs = CPU(cpu); 124 CPUX86State *env = &cpu->env; 125 126 env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ 127 cs->halted = 1; 128 cs->exception_index = EXCP_HLT; 129 cpu_loop_exit(cs); 130 } 131 132 void helper_hlt(CPUX86State *env, int next_eip_addend) 133 { 134 X86CPU *cpu = env_archcpu(env); 135 136 cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); 137 env->eip += next_eip_addend; 138 139 do_hlt(cpu); 140 } 141 142 void helper_monitor(CPUX86State *env, target_ulong ptr) 143 { 144 if ((uint32_t)env->regs[R_ECX] != 0) { 145 raise_exception_ra(env, EXCP0D_GPF, GETPC()); 146 } 147 /* XXX: store address? */ 148 cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC()); 149 } 150 151 void helper_mwait(CPUX86State *env, int next_eip_addend) 152 { 153 CPUState *cs = env_cpu(env); 154 X86CPU *cpu = env_archcpu(env); 155 156 if ((uint32_t)env->regs[R_ECX] != 0) { 157 raise_exception_ra(env, EXCP0D_GPF, GETPC()); 158 } 159 cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC()); 160 env->eip += next_eip_addend; 161 162 /* XXX: not complete but not completely erroneous */ 163 if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { 164 do_pause(cpu); 165 } else { 166 do_hlt(cpu); 167 } 168 } 169 170 void helper_pause(CPUX86State *env, int next_eip_addend) 171 { 172 X86CPU *cpu = env_archcpu(env); 173 174 cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); 175 env->eip += next_eip_addend; 176 177 do_pause(cpu); 178 } 179 180 void helper_debug(CPUX86State *env) 181 { 182 CPUState *cs = env_cpu(env); 183 184 cs->exception_index = EXCP_DEBUG; 185 cpu_loop_exit(cs); 186 } 187 188 uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx) 189 { 190 if ((env->cr[4] & CR4_PKE_MASK) == 0) { 191 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); 192 } 193 if (ecx != 0) { 194 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 195 } 196 197 return env->pkru; 198 } 199 200 void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val) 201 { 202 CPUState *cs = env_cpu(env); 203 204 if ((env->cr[4] & CR4_PKE_MASK) == 0) { 205 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); 206 } 207 if (ecx != 0 || (val & 0xFFFFFFFF00000000ull)) { 208 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 209 } 210 211 env->pkru = val; 212 tlb_flush(cs); 213 } 214